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 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T46,T47,T82
1	1	0	Covered	T560,T452,T628
1	1	1	Covered	T402,T69,T136

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T82
1	0	1	Covered	T46,T301,T694
1	1	0	Covered	T467,T560,T596
1	1	1	Covered	T70,T452,T562

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T70,T415,T452
1	1	0	Not Covered
1	1	1	Covered	T8,T5,T6

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T70,T415,T452
1	1	0	Covered	T697
1	1	1	Covered	T8,T5,T6

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T8,T5,T6
1	0	1	Covered	T70,T415,T452
1	1	0	Covered	T698
1	1	1	Covered	T2,T3,T4