Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T128 T328 T334 | T128 T328 T334 | T128 T328 T335 | T128 T328 T335 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T128 T328 T334 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T129 T130 T131 | T30 T328 T65 | T30 T328 T65 | T30 T328 T65 | T30 T328 T65 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T30 T328 T65 | T28 T328 T66 | T28 T328 T66 | T28 T328 T66 | T28 T328 T66 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T28 T328 T66 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T12 T124 T226 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T15 T124 T53 | T124 T189 T190 | T124 T189 T190 | T59 T338 T138 | T59 T338 T138 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T59 T338 T60 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T61 T338 T341 | T61 T338 T341 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T61 T62 T338 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T63 T338 T64 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T32 T124 T134 | T32 T124 T189 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T287 T343 T192 | T46 T82 T191 | T338 T301 T339 | T47 T192 T338 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T6 T7 T342 | T67 T328 T234 | T139 T338 T140 | T329 T258 T361 | T257 T258 T343 | T179 T124 T344 | T124 T189 T190 | T5 T146 T330 | T5 T146 T330 | T146 T330 T338 | T146 T330 T338 | T5 T146 T330 | T338 T339 T340 | T331 T332 T345 | T338 T339 T340 | T338 T339 T340 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T161 T124 T182 | T124 T189 T190 | T338 T339 T340 | T346 T338 T339 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T346 T338 T339 | T338 T339 T340 | T346 T338 T339 | T338 T339 T340
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T275 T276 T327 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T15 T12 | T15 T275 T124 | T15 T275 T124 | T15 T12 T13 | T15 T12 T13 | T15 T275 T124 | T275 T124 T328 | T275 T124 T328 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T59 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T275 T124 T328 | T61 T62 T275 | T62 T275 T124 | T275 T124 T328 | T62 T275 T124 | T62 T275 T124 | T62 T275 T124 | T63 T275 T124 | T63 T275 T124 | T275 T124 T328 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T275 T124 T328 | T63 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T32 T275 T124 | T32 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T46 T47 T82 | T46 T47 T82 | T46 T47 T82 | T46 T47 T82 | T12 T13 T275 | T12 T13 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T6 T7 T329 | T67 T275 T124 | T139 T275 T124 | T46 T47 T82 | T46 T257 T47 | T179 T275 T124 | T275 T124 T328 | T5 T146 T330 | T5 T146 T330 | T5 T146 T330 | T5 T146 T330 | T5 T146 T330 | T275 T124 T328 | T331 T332 T275 | T331 T332 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T5 T6 T7 | T32 T30 T28 | T30 T28 T29 | T32 T29 T15 | T5 T6 T7 | T30 T28 T128 | T28 T29 T275 | T29 T15 T12 | T32 T61 T62 | T6 T7 T46 | T5 T146 T330 | T128 T129 T130 | T30 T28 T129 | T28 T29 T275 | T29 T275 T124 | T29 T15 T12 | T61 T59 T275 | T61 T62 T63 | T32 T63 T287 | T46 T47 T82 | T6 T7 T257 | T5 T146 T330 | T275 T124 T328 | T128 T275 T124 | T128 T129 T130 | T30 T129 T130 | T30 T28 T275 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T12 T275 | T15 T12 T59 | T59 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T63 T275 | T63 T275 T124 | T32 T287 T343 | T46 T47 T82 | T275 T124 T328 | T275 T124 T328 | T6 T7 T46 | T5 T146 T330 | T161 T275 T124 | T275 T124 T328 | T128 T275 T124 | T128 T275 T124 | T128 T129 T130 | T129 T130 T131 | T30 T129 T130 | T30 T275 T124 | T30 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T15 T12 | T15 T12 T13 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T63 T275 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T32 T275 T124 | T287 T343 T275 | T46 T47 T82 | T12 T13 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T6 T7 T67 | T46 T257 T47 | T5 T146 T330 | T5 T146 T330 | T275 T124 T328 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T30 T129 T130 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T15 T12 | T15 T275 T124 | T15 T12 T13 | T15 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T275 T124 | T62 T275 T124 | T62 T63 T275 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T275 T124 T328 | T275 T124 T328 | T32 T275 T124 | T275 T124 T328 | T46 T47 T82 | T46 T47 T82 | T46 T47 T82 | T12 T13 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T6 T7 T329 | T67 T139 T275 | T46 T257 T47 | T179 T275 T124 | T5 T146 T330 | T5 T146 T330 | T5 T146 T330 | T331 T332 T275 | T275 T124 T328 | T275 T124 T328 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T5 T6 T7 | T32 T30 T28 | T5 T6 T7 | T30 T28 T29 | T32 T29 T15 | T5 T6 T7 | T30 T28 T128 | T28 T29 T328 | T29 T15 T12 | T32 T61 T62 | T6 T7 T46 | T5 T146 T330 | T128 T129 T130 | T30 T28 T129 | T28 T29 T328 | T29 T338 T44 | T29 T15 T12 | T61 T59 T338 | T61 T62 T63 | T32 T63 T287 | T46 T47 T82 | T6 T7 T257 | T5 T146 T330 | T346 T338 T339 | T128 T328 T335 | T128 T129 T130 | T30 T129 T130 | T30 T28 T328 | T28 T29 T328 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T12 T124 | T15 T59 T124 | T59 T338 T60 | T61 T338 T341 | T61 T62 T338 | T63 T338 T64 | T63 T338 T64 | T32 T287 T343 | T46 T47 T82 | T328 T336 T337 | T328 T336 T337 | T6 T7 T257 | T5 T146 T330 | T161 T124 T346 | T346 T338 T339 | T346 T338 T339 | T128 T328 T335 | T128 T328 T335 | T128 T129 T130 | T129 T130 T131 | T30 T129 T130 | T30 T328 T65 | T30 T328 T65 | T28 T328 T66 | T328 T336 T337 | T28 T29 T328 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T12 T124 | T15 T124 T53 | T59 T124 T338 | T338 T339 T340 | T59 T338 T60 | T338 T339 T340 | T61 T338 T341 | T338 T339 T340 | T61 T62 T338 | T63 T338 T64 | T63 T338 T64 | T338 T339 T340 | T63 T338 T64 | T32 T124 T338 | T287 T343 T192 | T46 T47 T82 | T124 T328 T189 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T6 T7 T67 | T257 T329 T258 | T5 T146 T330 | T5 T146 T330 | T124 T338 T189 | T161 T124 T346 | T338 T339 T340 | T346 T338 T339 | T346 T338 T339 | T128 T328 T334 | T128 T328 T335 | T128 T328 T335 | T328 T336 T337 | T128 T328 T334 | T129 T130 T131 | T129 T130 T131 | T328 T336 T337 | T328 T336 T337 | T30 T129 T130 | T30 T328 T65 | T30 T328 T65 | T328 T336 T337 | T30 T328 T65 | T28 T328 T66 | T28 T328 T66 | T328 T336 T337 | T328 T336 T337 | T28 T29 T328 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T12 T124 | T124 T189 T190 | T124 T189 T190 | T15 T124 T53 | T59 T124 T338 | T59 T338 T138 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T59 T338 T60 | T338 T339 T340 | T338 T339 T340 | T61 T338 T341 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T61 T62 T338 | T338 T339 T340 | T338 T339 T340 | T63 T338 T64 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T32 T124 T134 | T124 T189 T190 | T287 T343 T192 | T46 T82 T191 | T47 T192 T124 | T124 T189 T190 | T124 T328 T189 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T6 T7 T342 | T67 T139 T328 | T257 T329 T258 | T179 T124 T344 | T5 T146 T330 | T146 T330 T338 | T5 T146 T330 | T331 T332 T345 | T124 T338 T189 | T124 T189 T190 | T161 T124 T182 | T346 T338 T339 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T346 T338 T339 | T346 T338 T339
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T5 T6 T7 | T32 T30 T28 | T5 T6 T7 | T30 T28 T29 | T32 T29 T15 | T5 T6 T7 | T30 T28 T128 | T28 T29 T328 | T29 T15 T12 | T32 T61 T62 | T6 T7 T257 | T5 T146 T330 | T128 T129 T130 | T30 T28 T129 | T28 T29 T328 | T29 T338 T44 | T29 T15 T12 | T61 T59 T338 | T61 T62 T63 | T32 T63 T287 | T47 T192 T124 | T6 T7 T257 | T5 T146 T330 | T346 T338 T339 | T128 T328 T335 | T128 T129 T130 | T30 T129 T130 | T30 T28 T328 | T28 T29 T328 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T12 T124 | T15 T59 T124 | T59 T338 T60 | T61 T338 T341 | T61 T62 T338 | T63 T338 T64 | T63 T338 T64 | T32 T287 T343 | T47 T192 T124 | T328 T336 T337 | T328 T336 T337 | T6 T7 T257 | T5 T146 T330 | T161 T124 T346 | T346 T338 T339 | T338 T339 T340 | T128 T328 T335 | T328 T336 T337 | T128 T129 T130 | T129 T130 T131 | T30 T129 T130 | T30 T328 T65 | T30 T328 T65 | T28 T328 T66 | T328 T336 T337 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T12 T124 T226 | T15 T124 T53 | T59 T338 T138 | T338 T339 T340 | T59 T338 T60 | T338 T339 T340 | T61 T338 T341 | T338 T339 T340 | T61 T62 T338 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T32 T124 T338 | T287 T343 T192 | T47 T192 T124 | T124 T328 T189 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T6 T7 T67 | T257 T258 T179 | T5 T146 T330 | T331 T332 T345 | T124 T189 T190 | T124 T346 T338 | T338 T339 T340 | T346 T338 T339 | T338 T339 T340 | T128 T328 T334 | T128 T328 T335 | T328 T336 T337 | T328 T336 T337 | T128 T328 T334 | T129 T130 T131 | T129 T130 T131 | T328 T336 T337 | T328 T336 T337 | T30 T328 T65 | T30 T328 T65 | T328 T336 T337 | T328 T336 T337 | T30 T328 T65 | T28 T328 T66 | T28 T328 T66 | T328 T336 T337 | T328 T336 T337 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T29 T338 T44 | T12 T124 T226 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T59 T338 T138 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T61 T338 T341 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T61 T62 T338 | T338 T339 T340 | T338 T339 T340 | T63 T338 T64 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T32 T124 T189 | T124 T189 T190 | T287 T343 T192 | T338 T301 T339 | T124 T189 T190 | T124 T189 T190 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T328 T336 T337 | T6 T7 T342 | T139 T338 T140 | T257 T258 T343 | T124 T189 T190 | T5 T146 T330 | T146 T330 T338 | T338 T339 T340 | T338 T339 T340 | T124 T189 T190 | T124 T189 T190 | T124 T189 T190 | T346 T338 T339 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340 | T338 T339 T340
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T5 T6 T7 | T32 T30 T28 | T5 T6 T7 | T30 T28 T29 | T32 T29 T15 | T5 T6 T7 | T30 T28 T128 | T28 T29 T275 | T29 T15 T12 | T32 T61 T62 | T6 T7 T46 | T5 T146 T330 | T128 T129 T130 | T30 T28 T129 | T28 T29 T275 | T29 T275 T124 | T29 T15 T12 | T61 T59 T275 | T61 T62 T63 | T32 T63 T287 | T46 T47 T82 | T6 T7 T257 | T5 T146 T330 | T275 T124 T328 | T128 T275 T124 | T128 T129 T130 | T30 T129 T130 | T30 T28 T275 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T12 T275 | T15 T12 T59 | T59 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T63 T275 | T63 T275 T124 | T32 T287 T343 | T46 T47 T82 | T275 T124 T328 | T275 T124 T328 | T6 T7 T46 | T5 T146 T330 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T128 T275 T124 | T128 T275 T124 | T128 T129 T130 | T129 T130 T131 | T30 T129 T130 | T30 T275 T124 | T30 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T15 T12 | T15 T12 T13 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T63 T275 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T32 T275 T124 | T287 T343 T275 | T46 T47 T82 | T12 T13 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T6 T7 T67 | T46 T257 T47 | T5 T146 T330 | T5 T146 T330 | T275 T124 T328 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T128 T275 T124 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T129 T130 T131 | T30 T129 T130 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T30 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T275 T124 | T28 T29 T275 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T275 T124 | T29 T15 T12 | T15 T275 T124 | T15 T12 T13 | T15 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T59 T275 T124 | T275 T124 T328 | T275 T124 T328 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T275 T124 | T61 T62 T275 | T62 T275 T124 | T62 T275 T124 | T62 T63 T275 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T63 T275 T124 | T275 T124 T328 | T275 T124 T328 | T32 T275 T124 | T275 T124 T328 | T46 T47 T82 | T46 T47 T82 | T46 T47 T82 | T12 T13 T275 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T6 T7 T329 | T67 T139 T275 | T46 T257 T47 | T179 T275 T124 | T5 T146 T330 | T5 T146 T330 | T5 T146 T330 | T331 T332 T275 | T275 T124 T328 | T275 T124 T328 | T161 T275 T124 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328 | T275 T124 T328
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T5 T6 T7
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T5 T6 T7
101 1/1 assign max_value_o = max_tree[0];
Tests: T5 T6 T7
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);