Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142568	1			T97	2		T98	5		T102	4
values[2]	11202	1			T184	2		T309	2		T480	1
values[3]	4587	1			T565	11		T497	3		T660	1
values[4]	2524	1			T565	15		T497	6		T660	2
values[5]	1570	1			T565	13		T497	15		T660	2
values[6]	1051	1			T565	18		T497	3		T660	1
values[7]	715	1			T565	9		T497	8		T660	5
values[8]	466	1			T565	13		T497	5		T660	3
values[9]	396	1			T565	27		T497	8		T660	3
values[10]	360	1			T565	16		T497	13		T660	4
values[11]	311	1			T565	12		T497	6		T660	4
values[12]	302	1			T565	17		T497	5		T660	1
values[13]	294	1			T565	11		T497	9		T660	1
values[14]	313	1			T565	11		T497	19		T660	2
values[15]	254	1			T565	7		T497	10		T660	5
values[16]	325	1			T565	21		T497	3		T660	3
values[17]	250	1			T565	13		T497	6		T660	2
values[18]	250	1			T565	15		T497	7		T660	1
values[19]	256	1			T565	27		T497	2		T660	3
values[20]	294	1			T565	12		T497	5		T660	1
values[21]	293	1			T565	13		T497	11		T660	1
values[22]	291	1			T565	9		T497	33		T660	2
values[23]	232	1			T565	22		T497	3		T660	2
values[24]	238	1			T565	21		T497	7		T660	1
values[25]	274	1			T565	18		T497	3		T660	2
values[26]	263	1			T565	16		T497	5		T660	2
values[27]	250	1			T565	21		T497	5		T660	2
values[28]	252	1			T565	30		T497	3		T660	1
values[29]	238	1			T565	10		T497	8		T660	1
values[30]	263	1			T565	24		T497	4		T660	3
values[31]	271	1			T565	12		T497	17		T660	1
values[32]	249	1			T565	11		T497	5		T660	3
values[33]	308	1			T565	14		T497	4		T660	2
values[34]	276	1			T565	19		T497	15		T660	1
values[35]	258	1			T565	18		T497	3		T660	2
values[36]	218	1			T565	17		T497	6		T660	2
values[37]	234	1			T565	16		T497	8		T660	4
values[38]	251	1			T565	7		T497	7		T660	8
values[39]	260	1			T565	10		T497	4		T660	2
values[40]	259	1			T565	16		T497	5		T660	2
values[41]	242	1			T565	13		T497	3		T660	1
values[42]	215	1			T565	13		T497	7		T660	2
values[43]	226	1			T565	10		T497	7		T660	2
values[44]	230	1			T565	7		T497	6		T660	1
values[45]	260	1			T565	23		T497	6		T660	1
values[46]	254	1			T565	13		T497	15		T660	7
values[47]	257	1			T565	11		T497	33		T660	2
values[48]	244	1			T565	17		T497	15		T660	3
values[49]	281	1			T565	13		T497	6		T660	4
values[50]	221	1			T565	20		T497	3		T660	6
values[51]	207	1			T565	10		T497	3		T660	4
values[52]	210	1			T565	14		T497	10		T660	3
values[53]	216	1			T565	26		T497	3		T660	5
values[54]	230	1			T565	15		T497	3		T660	1
values[55]	212	1			T565	10		T497	6		T660	3
values[56]	208	1			T565	9		T497	6		T660	3
values[57]	229	1			T565	2		T497	4		T660	1
values[58]	205	1			T565	12		T497	2		T660	2
values[59]	209	1			T565	8		T497	5		T660	2
values[60]	176	1			T565	4		T497	5		T660	1
values[61]	190	1			T565	5		T497	11		T660	1
values[62]	195	1			T565	6		T497	9		T660	1
values[63]	179	1			T565	4		T497	4		T660	2
values[64]	154	1			T565	10		T497	5		T660	1
values[65]	118	1			T497	5		T660	4		T603	7
values[66]	149	1			T497	4		T660	1		T603	6
values[67]	156	1			T497	5		T660	2		T603	3
values[68]	113	1			T497	4		T660	1		T603	5
values[69]	118	1			T497	3		T660	4		T603	6
values[70]	101	1			T497	9		T660	3		T603	5
values[71]	107	1			T497	13		T660	2		T603	2
values[72]	97	1			T497	2		T660	3		T603	3
values[73]	92	1			T497	9		T660	3		T603	2
values[74]	92	1			T497	13		T660	2		T603	2
values[75]	76	1			T497	11		T660	3		T603	4
values[76]	57	1			T497	1		T660	3		T603	1
values[77]	56	1			T660	5		T603	3		T486	1
values[78]	59	1			T660	3		T603	2		T486	1
values[79]	52	1			T660	3		T603	2		T486	1
values[80]	55	1			T660	3		T603	2		T486	1
values[81]	45	1			T660	2		T603	2		T486	1
values[82]	32	1			T660	1		T603	1		T486	1
values[83]	49	1			T660	2		T603	3		T486	1
values[84]	51	1			T660	2		T603	1		T486	1
values[85]	49	1			T660	5		T603	3		T486	1
values[86]	53	1			T660	4		T603	5		T486	1
values[87]	56	1			T660	4		T603	3		T486	1
values[88]	70	1			T660	8		T603	6		T486	1
values[89]	60	1			T660	4		T603	10		T486	1
values[90]	56	1			T660	1		T603	7		T486	1
values[91]	45	1			T660	1		T603	6		T486	1
values[92]	37	1			T660	1		T603	6		T486	1
values[93]	48	1			T660	3		T603	5		T486	1
values[94]	57	1			T660	5		T603	3		T486	1
values[95]	63	1			T660	12		T603	6		T486	1
values[96]	47	1			T660	9		T603	4		T486	1
values[97]	65	1			T660	15		T603	3		T486	1
values[98]	57	1			T660	4		T603	1		T486	1
values[99]	57	1			T660	4		T603	10		T486	1
values[100]	63	1			T660	3		T603	9		T486	1
values[101]	52	1			T660	2		T603	6		T486	7
values[102]	60	1			T660	2		T603	4		T486	6
values[103]	53	1			T660	7		T603	2		T486	2
values[104]	48	1			T660	7		T603	4		T486	2
values[105]	52	1			T660	4		T603	3		T486	2
values[106]	40	1			T660	2		T603	4		T486	3
values[107]	34	1			T660	2		T603	1		T486	1
values[108]	21	1			T603	2		T486	1		T525	1
values[109]	35	1			T603	9		T486	4		T525	1
values[110]	30	1			T603	6		T486	1		T525	1
values[111]	37	1			T603	3		T486	2		T525	1
values[112]	41	1			T603	3		T486	8		T525	1
values[113]	38	1			T603	3		T486	1		T525	1
values[114]	40	1			T603	1		T486	5		T525	1
values[115]	35	1			T486	2		T525	1		T552	12
values[116]	29	1			T486	1		T525	3		T552	3
values[117]	31	1			T486	1		T525	2		T552	4
values[118]	32	1			T486	2		T525	3		T552	3
values[119]	24	1			T486	4		T525	1		T552	1
values[120]	31	1			T486	3		T525	2		T552	2
values[121]	36	1			T486	10		T525	1		T552	3
values[122]	27	1			T486	5		T525	3		T552	3
values[123]	40	1			T486	1		T525	4		T552	1
values[124]	23	1			T486	1		T525	1		T806	1
values[125]	27	1			T486	1		T525	2		T806	1
values[126]	44	1			T486	6		T525	4		T806	1
values[127]	370	1			T486	40		T525	35		T806	32
values[128]	3336	1			T486	311		T525	386		T806	354