Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.50 94.21 95.38 95.05 97.40 99.53


Total tests in report: 2927
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.19 40.19 45.11 45.11 46.68 46.68 27.72 27.72 63.22 63.22 58.25 58.25 0.14 0.14 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1017041522
47.52 7.33 49.43 4.32 56.11 9.43 27.95 0.23 69.77 6.55 80.93 22.68 0.94 0.80 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1114105163
52.84 5.32 60.63 11.20 63.75 7.65 31.01 3.06 79.80 10.03 80.93 0.00 0.94 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2168310784
56.78 3.94 67.69 7.06 65.12 1.37 37.32 6.31 80.07 0.28 80.93 0.00 9.56 8.62 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3980442905
60.49 3.70 74.12 6.43 68.90 3.77 44.89 7.57 82.22 2.14 82.99 2.06 9.80 0.23 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4232706083
64.02 3.54 74.12 0.00 69.06 0.16 44.89 0.00 82.25 0.03 82.99 0.00 30.83 21.03 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.29717394
67.07 3.04 78.91 4.79 72.87 3.81 48.39 3.50 83.94 1.70 87.46 4.47 30.83 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.219116538
69.80 2.73 78.91 0.00 72.87 0.01 48.39 0.00 83.94 0.00 87.46 0.00 47.21 16.38 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2136643750
72.23 2.44 78.91 0.00 72.87 0.00 63.02 14.63 83.94 0.00 87.46 0.00 47.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.556691759
74.55 2.32 80.34 1.43 75.45 2.58 68.53 5.51 85.74 1.79 87.63 0.17 49.63 2.42 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2916141271
76.53 1.98 80.34 0.00 75.46 0.01 68.53 0.00 85.74 0.00 87.63 0.00 61.49 11.86 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1766614744
78.14 1.61 83.67 3.33 76.85 1.39 71.45 2.92 86.73 1.00 88.66 1.03 61.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2599017475
79.53 1.39 85.30 1.63 78.51 1.67 72.45 0.99 88.03 1.30 91.41 2.75 61.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.920746383
80.88 1.35 85.40 0.10 78.59 0.08 80.03 7.58 88.20 0.17 91.58 0.17 61.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2040772036
82.17 1.29 87.76 2.36 80.54 1.95 80.75 0.72 90.90 2.69 91.58 0.00 61.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.587245404
83.43 1.26 87.76 0.00 80.54 0.00 80.75 0.00 90.90 0.00 91.58 0.00 69.03 7.54 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1039117122
84.61 1.18 87.80 0.03 81.43 0.89 80.75 0.00 90.91 0.02 91.58 0.00 75.16 6.13 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2956982845
85.77 1.17 87.80 0.00 81.43 0.00 80.75 0.00 90.91 0.00 91.58 0.00 82.15 6.99 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.284762315
86.47 0.70 88.80 1.00 82.12 0.70 81.74 0.99 91.59 0.67 92.44 0.86 82.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.3984999652
87.17 0.70 88.97 0.18 82.24 0.12 81.76 0.01 91.70 0.11 96.22 3.78 82.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3378090671
87.86 0.68 88.98 0.01 85.91 3.67 81.76 0.00 91.70 0.00 96.22 0.00 82.56 0.41 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3681683417
88.51 0.66 88.98 0.00 86.26 0.35 81.76 0.00 91.73 0.03 96.22 0.00 86.14 3.57 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1335213831
89.13 0.61 89.98 0.99 86.31 0.04 82.68 0.92 91.73 0.00 96.22 0.00 87.84 1.70 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2890711009
89.63 0.50 90.88 0.91 87.20 0.89 83.17 0.49 92.45 0.71 96.22 0.00 87.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4163753470
90.08 0.45 90.88 0.00 87.20 0.00 83.17 0.00 92.45 0.00 96.22 0.00 90.55 2.71 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2311844298
90.45 0.37 91.69 0.81 87.53 0.34 83.86 0.69 92.64 0.19 96.39 0.17 90.59 0.04 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3934723241
90.80 0.35 91.69 0.00 87.53 0.00 85.96 2.10 92.64 0.00 96.39 0.00 90.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3933029184
91.12 0.31 92.42 0.73 87.92 0.39 86.42 0.46 92.95 0.31 96.39 0.00 90.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1897410602
91.42 0.30 92.43 0.01 87.93 0.01 88.24 1.81 92.95 0.00 96.39 0.00 90.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.610775461
91.71 0.29 92.96 0.53 88.40 0.48 88.50 0.27 93.41 0.46 96.39 0.00 90.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3183794226
91.99 0.28 92.96 0.00 88.40 0.00 88.50 0.00 93.41 0.00 96.39 0.00 92.26 1.67 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.651475806
92.26 0.28 92.96 0.00 88.40 0.00 90.16 1.66 93.41 0.00 96.39 0.00 92.26 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2155783782
92.53 0.26 92.96 0.00 88.40 0.00 90.16 0.00 93.41 0.00 96.39 0.00 93.84 1.59 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1526585726
92.77 0.25 92.96 0.01 88.47 0.06 90.16 0.00 93.44 0.02 96.39 0.00 95.23 1.39 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3633544686
93.01 0.24 92.96 0.00 88.47 0.00 90.16 0.00 93.44 0.00 96.39 0.00 96.65 1.42 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2672153535
93.22 0.21 93.28 0.32 89.25 0.78 90.30 0.14 93.47 0.03 96.39 0.00 96.65 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.4107628954
93.43 0.21 93.62 0.35 89.29 0.04 91.13 0.83 93.50 0.03 96.39 0.00 96.65 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.855501349
93.61 0.18 93.62 0.00 90.34 1.05 91.13 0.00 93.50 0.00 96.39 0.00 96.65 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2466353031
93.78 0.17 93.88 0.26 90.61 0.28 91.36 0.22 93.79 0.29 96.39 0.00 96.65 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3235153940
93.93 0.15 93.92 0.03 90.74 0.13 91.36 0.00 93.80 0.01 96.39 0.00 97.36 0.70 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3331512030
94.07 0.14 93.96 0.04 91.11 0.36 91.39 0.03 94.21 0.41 96.39 0.00 97.36 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2339607432
94.20 0.13 93.96 0.00 91.11 0.00 92.16 0.77 94.21 0.00 96.39 0.00 97.36 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3166371858
94.31 0.11 94.17 0.21 91.25 0.14 92.33 0.18 94.35 0.15 96.39 0.00 97.36 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.769202229
94.41 0.10 94.17 0.00 91.25 0.01 92.33 0.00 94.35 0.00 96.39 0.00 97.96 0.60 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2573654108
94.50 0.09 94.17 0.00 91.25 0.00 92.86 0.53 94.35 0.00 96.39 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3840057766
94.58 0.08 94.25 0.09 91.32 0.07 93.09 0.23 94.47 0.11 96.39 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.1529615321
94.66 0.08 94.26 0.01 91.81 0.49 93.10 0.01 94.47 0.00 96.39 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.3019660326
94.75 0.08 94.28 0.03 92.03 0.22 93.10 0.01 94.71 0.24 96.39 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1527974808
94.82 0.07 94.31 0.03 92.09 0.07 93.21 0.11 94.76 0.05 96.56 0.17 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2779994431
94.88 0.06 94.31 0.00 92.45 0.36 93.21 0.00 94.76 0.00 96.56 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.4153605040
94.93 0.05 94.31 0.00 92.45 0.00 93.53 0.32 94.76 0.00 96.56 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1480540105
94.98 0.05 94.34 0.03 92.48 0.02 93.56 0.03 94.78 0.02 96.74 0.17 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.4062550809
95.02 0.05 94.40 0.06 92.66 0.18 93.60 0.04 94.78 0.00 96.74 0.00 97.96 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1897016986
95.07 0.04 94.40 0.00 92.66 0.01 93.60 0.00 94.78 0.00 96.74 0.00 98.21 0.26 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.34605470
95.11 0.04 94.47 0.07 92.66 0.00 93.77 0.16 94.79 0.01 96.74 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2576254047
95.15 0.04 94.47 0.00 92.67 0.01 93.99 0.23 94.79 0.00 96.74 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1308404856
95.18 0.04 94.48 0.01 92.68 0.01 93.99 0.00 94.82 0.02 96.91 0.17 98.23 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1104190532
95.22 0.04 94.49 0.01 92.70 0.02 93.99 0.00 94.82 0.01 97.08 0.17 98.24 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2111063661
95.26 0.04 94.49 0.01 92.71 0.01 94.00 0.01 94.83 0.01 97.25 0.17 98.25 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1216797606
95.29 0.04 94.49 0.00 92.73 0.02 94.19 0.19 94.83 0.00 97.25 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.914880037
95.32 0.03 94.53 0.04 92.77 0.04 94.31 0.12 94.84 0.01 97.25 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2142558478
95.35 0.03 94.53 0.00 92.77 0.01 94.31 0.00 94.84 0.00 97.42 0.17 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.2683236176
95.38 0.03 94.60 0.07 92.81 0.04 94.34 0.03 94.86 0.02 97.42 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.292433476
95.41 0.03 94.60 0.00 92.97 0.16 94.34 0.00 94.86 0.00 97.42 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.163518294
95.43 0.03 94.67 0.07 93.00 0.03 94.34 0.01 94.91 0.05 97.42 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3681013869
95.46 0.02 94.67 0.00 93.00 0.00 94.48 0.14 94.91 0.00 97.42 0.00 98.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2141313338
95.48 0.02 94.67 0.00 93.05 0.05 94.48 0.00 94.93 0.02 97.42 0.00 98.31 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1818732517
95.50 0.02 94.68 0.01 93.07 0.01 94.59 0.11 94.93 0.00 97.42 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2447793611
95.52 0.02 94.73 0.06 93.11 0.05 94.59 0.00 94.95 0.02 97.42 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.452018037
95.54 0.02 94.74 0.01 93.16 0.05 94.61 0.02 94.99 0.04 97.42 0.00 98.31 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3374540243
95.56 0.02 94.74 0.00 93.16 0.00 94.64 0.03 94.99 0.00 97.42 0.00 98.39 0.08 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3954314092
95.58 0.02 94.74 0.00 93.18 0.02 94.73 0.09 94.99 0.00 97.42 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4181930633
95.59 0.02 94.74 0.00 93.29 0.11 94.73 0.00 94.99 0.00 97.42 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.2733111295
95.61 0.02 94.74 0.00 93.39 0.10 94.73 0.00 94.99 0.00 97.42 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.110697521
95.63 0.02 94.76 0.02 93.46 0.07 94.74 0.01 94.99 0.00 97.42 0.00 98.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3999688865
95.64 0.02 94.76 0.00 93.46 0.00 94.82 0.08 94.99 0.00 97.42 0.00 98.40 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3025151314
95.65 0.01 94.76 0.00 93.47 0.01 94.82 0.00 94.99 0.00 97.42 0.00 98.47 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1677620162
95.67 0.01 94.76 0.00 93.47 0.00 94.89 0.08 94.99 0.00 97.42 0.00 98.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.984229189
95.68 0.01 94.77 0.01 93.52 0.05 94.89 0.00 95.00 0.02 97.42 0.00 98.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.4181157037
95.69 0.01 94.77 0.00 93.56 0.04 94.89 0.00 95.00 0.00 97.42 0.00 98.51 0.04 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2649260881
95.70 0.01 94.77 0.00 93.60 0.04 94.89 0.00 95.00 0.00 97.42 0.00 98.53 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.495840413
95.71 0.01 94.80 0.03 93.62 0.02 94.89 0.00 95.01 0.01 97.42 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.1329516983
95.72 0.01 94.80 0.00 93.68 0.06 94.89 0.00 95.01 0.00 97.42 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3994824076
95.73 0.01 94.82 0.02 93.69 0.01 94.90 0.01 95.03 0.02 97.42 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3208265549
95.74 0.01 94.85 0.02 93.69 0.01 94.90 0.01 95.04 0.02 97.42 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.4124032552
95.75 0.01 94.85 0.01 93.71 0.02 94.93 0.03 95.04 0.00 97.42 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2874826192
95.76 0.01 94.85 0.00 93.71 0.00 94.93 0.00 95.04 0.00 97.42 0.00 98.58 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1474173806
95.76 0.01 94.85 0.00 93.71 0.00 94.97 0.05 95.04 0.00 97.42 0.00 98.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2850809453
95.77 0.01 94.85 0.00 93.71 0.00 95.02 0.05 95.04 0.00 97.42 0.00 98.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2328974446
95.78 0.01 94.86 0.01 93.72 0.01 95.05 0.03 95.04 0.00 97.42 0.00 98.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.414912800
95.79 0.01 94.86 0.00 93.76 0.04 95.05 0.00 95.04 0.00 97.42 0.00 98.58 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1265886180
95.79 0.01 94.86 0.00 93.79 0.03 95.05 0.00 95.04 0.00 97.42 0.00 98.59 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3641830950
95.80 0.01 94.86 0.01 93.82 0.02 95.06 0.01 95.04 0.00 97.42 0.00 98.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2012710219
95.81 0.01 94.86 0.00 93.82 0.00 95.06 0.00 95.04 0.00 97.42 0.00 98.63 0.04 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4278245731
95.81 0.01 94.86 0.00 93.82 0.00 95.06 0.00 95.04 0.00 97.42 0.00 98.66 0.04 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3419685282
95.82 0.01 94.86 0.00 93.82 0.00 95.10 0.03 95.04 0.00 97.42 0.00 98.66 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1646353644
95.82 0.01 94.86 0.00 93.84 0.02 95.10 0.00 95.04 0.00 97.42 0.00 98.67 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1990408379
95.83 0.01 94.86 0.00 93.84 0.00 95.12 0.03 95.04 0.00 97.42 0.00 98.67 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1518813390
95.83 0.01 94.87 0.01 93.85 0.01 95.13 0.01 95.04 0.00 97.42 0.00 98.67 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1802325029
95.84 0.01 94.87 0.00 93.88 0.02 95.13 0.01 95.04 0.00 97.42 0.00 98.67 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3781985042
95.84 0.01 94.87 0.01 93.88 0.00 95.16 0.02 95.04 0.00 97.42 0.00 98.67 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2737997627
95.84 0.01 94.87 0.00 93.88 0.00 95.17 0.01 95.04 0.00 97.42 0.00 98.68 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1530841587
95.85 0.01 94.87 0.00 93.90 0.02 95.17 0.00 95.04 0.00 97.42 0.00 98.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1332312119
95.85 0.01 94.87 0.00 93.93 0.02 95.17 0.00 95.04 0.00 97.42 0.00 98.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3119267226
95.86 0.01 94.87 0.00 93.95 0.02 95.17 0.00 95.04 0.00 97.42 0.00 98.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1457526317
95.86 0.01 94.87 0.00 93.98 0.02 95.17 0.00 95.04 0.00 97.42 0.00 98.68 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1975296015
95.87 0.01 94.87 0.00 93.98 0.00 95.17 0.00 95.04 0.00 97.42 0.00 98.71 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2128861870
95.87 0.01 94.87 0.00 93.98 0.00 95.19 0.02 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.919569235
95.87 0.01 94.87 0.00 93.98 0.00 95.21 0.02 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.4110767861
95.87 0.01 94.87 0.00 93.99 0.02 95.21 0.00 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.3869813051
95.88 0.01 94.87 0.00 94.01 0.02 95.21 0.00 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1591991205
95.88 0.01 94.87 0.00 94.03 0.02 95.21 0.00 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.2668685436
95.88 0.01 94.87 0.00 94.03 0.01 95.22 0.01 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.1289773501
95.89 0.01 94.87 0.00 94.03 0.00 95.24 0.02 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.4191650497
95.89 0.01 94.87 0.00 94.03 0.00 95.26 0.02 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1609657568
95.89 0.01 94.89 0.01 94.03 0.00 95.26 0.01 95.04 0.00 97.42 0.00 98.71 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3737897695
95.89 0.01 94.89 0.00 94.04 0.01 95.26 0.00 95.04 0.00 97.42 0.00 98.72 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2333248338
95.90 0.01 94.89 0.00 94.05 0.01 95.26 0.00 95.04 0.00 97.42 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.991186316
95.90 0.01 94.89 0.00 94.06 0.01 95.26 0.00 95.04 0.00 97.42 0.00 98.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3457265854
95.90 0.01 94.89 0.00 94.06 0.00 95.26 0.01 95.04 0.00 97.42 0.00 98.73 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063923301
95.90 0.01 94.89 0.00 94.06 0.00 95.26 0.01 95.04 0.00 97.42 0.00 98.74 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2450868542
95.91 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.75 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.524645495
95.91 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.77 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1708689090
95.91 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.78 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1315763618
95.91 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.79 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2453457734
95.91 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.80 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.3147145862
95.92 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.81 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127463789
95.92 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.83 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.36792037
95.92 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.84 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2505494647
95.92 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.85 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.907407549
95.92 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.86 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1216056097
95.93 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.87 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.104823591
95.93 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.88 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400101923
95.93 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.90 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.412104565
95.93 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.91 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2902215730
95.93 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.92 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262617271
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.93 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.809691225
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.94 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948424470
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.95 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1690645857
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.97 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914345312
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.98 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.58232884
95.94 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 98.99 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1377484075
95.95 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.00 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1898856546
95.95 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.01 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.721254218
95.95 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.02 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2354917191
95.95 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.04 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1780258400
95.95 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.05 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.3268824622
95.96 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.06 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193222170
95.96 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.07 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2487084611
95.96 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.08 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.656083257
95.96 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.10 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2600854547
95.96 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.11 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.163196560
95.97 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.12 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1905397460
95.97 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.13 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3317378642
95.97 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.14 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1650310017
95.97 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.15 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1773894741
95.97 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.17 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066722066
95.98 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.18 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1585710898
95.98 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.19 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.740215737
95.98 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.20 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2008557787
95.98 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.21 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2901640149
95.98 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.22 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2082998751
95.99 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.24 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639146307
95.99 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.25 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.462190850
95.99 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.26 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1264144273
95.99 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.27 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.3522174427
95.99 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.28 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1824500839
96.00 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.30 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.213753802
96.00 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.31 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2862853242
96.00 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.32 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055359889
96.00 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.33 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.501453644
96.00 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.34 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.416632256
96.01 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.35 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060238638
96.01 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.37 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.3336419152
96.01 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.38 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.4254429399
96.01 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.39 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169745454
96.01 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.40 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2722149628
96.02 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.41 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285925286
96.02 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.42 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669904732
96.02 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.44 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.134700869
96.02 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.45 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144752577
96.02 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.46 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.776528235
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.47 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246761196
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.48 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.3617013163
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.49 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069001756
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.51 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1090702688
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.52 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3397592315
96.03 0.01 94.89 0.00 94.06 0.00 95.26 0.00 95.04 0.00 97.42 0.00 99.53 0.01 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2687396940
96.04 0.01 94.89 0.00 94.06 0.00 95.28 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3394578108
96.04 0.01 94.89 0.00 94.07 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.878461655
96.04 0.01 94.89 0.00 94.09 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1460101633
96.04 0.01 94.89 0.00 94.10 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1748201265
96.04 0.01 94.89 0.00 94.11 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.636735758
96.05 0.01 94.89 0.00 94.12 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1504641449
96.05 0.01 94.89 0.00 94.13 0.01 95.28 0.00 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2308704245
96.05 0.01 94.89 0.00 94.13 0.00 95.29 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2417225561
96.05 0.01 94.89 0.01 94.13 0.00 95.29 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.957335725
96.05 0.01 94.89 0.01 94.13 0.00 95.30 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.3251527192
96.05 0.01 94.89 0.00 94.13 0.00 95.31 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.3502388654
96.06 0.01 94.89 0.00 94.13 0.00 95.32 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3842239022
96.06 0.01 94.90 0.01 94.13 0.01 95.32 0.01 95.04 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.1535820881
96.06 0.01 94.90 0.00 94.13 0.00 95.32 0.00 95.05 0.01 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2089496395
96.06 0.01 94.90 0.00 94.14 0.01 95.32 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4189899582
96.06 0.01 94.90 0.00 94.15 0.01 95.32 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3044397418
96.06 0.01 94.90 0.00 94.15 0.01 95.32 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.2145664846
96.06 0.01 94.90 0.00 94.16 0.01 95.32 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2924241317
96.06 0.01 94.90 0.00 94.17 0.01 95.32 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.3680472417
96.07 0.01 94.90 0.00 94.17 0.00 95.33 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3804847533
96.07 0.01 94.90 0.00 94.17 0.00 95.34 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3049583587
96.07 0.01 94.90 0.00 94.17 0.00 95.34 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.259895308
96.07 0.01 94.90 0.00 94.17 0.00 95.34 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1771060082
96.07 0.01 94.90 0.00 94.17 0.00 95.35 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.3020518949
96.07 0.01 94.90 0.00 94.17 0.00 95.35 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2798023119
96.07 0.01 94.90 0.00 94.17 0.00 95.36 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2806894862
96.07 0.01 94.90 0.00 94.17 0.00 95.36 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1167968821
96.07 0.01 94.90 0.00 94.17 0.00 95.37 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.758068997
96.07 0.01 94.90 0.00 94.17 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1309814332
96.07 0.01 94.90 0.00 94.17 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2476526404
96.07 0.01 94.90 0.00 94.18 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.3729628860
96.07 0.01 94.90 0.00 94.18 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3612842492
96.08 0.01 94.90 0.00 94.18 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3625808636
96.08 0.01 94.90 0.00 94.19 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.71741360
96.08 0.01 94.90 0.00 94.19 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3798538734
96.08 0.01 94.90 0.00 94.19 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.2821020226
96.08 0.01 94.90 0.00 94.20 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2195632867
96.08 0.01 94.90 0.00 94.20 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.945212594
96.08 0.01 94.90 0.00 94.21 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.899390021
96.08 0.01 94.90 0.00 94.21 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1266312426
96.08 0.01 94.90 0.00 94.21 0.01 95.37 0.00 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2457284784
96.08 0.01 94.90 0.00 94.21 0.00 95.37 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.182316120
96.08 0.01 94.90 0.00 94.21 0.00 95.37 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3046491122
96.08 0.01 94.90 0.00 94.21 0.00 95.38 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2114088684
96.08 0.01 94.90 0.00 94.21 0.00 95.38 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.559297190
96.08 0.01 94.90 0.00 94.21 0.00 95.38 0.01 95.05 0.00 97.42 0.00 99.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3621929772

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2756148561
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.676311531
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2724267911
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.599762315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2175842322
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3534869393
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4096490687
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1687471598
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3148716772
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3958783033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3284765941
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.849247758
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1033887215
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2355309139
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4109851683
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1690345493
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3066138805
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2478044198
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.3930571861
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1867702500
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3547176424
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3249522732
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3686535022
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1519948007
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1804284465
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3063078577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2944445023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2203927853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.397395083
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1560924674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3001606727
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1301760472
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2033198908
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.647557173
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3076844110
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.766595874
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.765900565
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2341715773
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1005102123
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1324537667
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3345065460
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3186158398
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3217749159
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.202234382
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.265646749
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1773086628
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3014930638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3552714323
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.4043278700
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.3136441366
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.718101520
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3665709065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.4080318528
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.504474624
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1926777467
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3188808659
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2754097408
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.4284414920
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1032354397
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.1242782906
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1666300659
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2759691942
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1689655408
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1729776633
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.840644128
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3123497157
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.1234051207
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.3752834286
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3203468858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3282785318
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.1166090399
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.63658859
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3047837160
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2104853306
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3534791654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3046110762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2276145765
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2799376113
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1325189762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.779082543
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.972385228
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.757822416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2884542380
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.4066955137
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.732438818
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.3947334431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3050945687
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.4007958237
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.3615450557
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2130524392
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3419424422
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2372799545
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1967192105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.579253969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2107210157
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.438875153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.517047745
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2161376735
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.4171460822
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1638706964
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3284861881
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.539101899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3656487738
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1314659340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3717538900
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1079030232
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.377030769
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.1669903452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3368581136
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2126310802
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.773601686
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4045234695
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1785370377
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3165662840
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1408111623
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4256381456
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3807262679
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2990837935
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3740186533
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1033310750
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2011568414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1649930535
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1473812925
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2313236855
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3752365380
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.2952107192
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.258028260
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3763652044
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.370219109
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.4006330791
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.841301970
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.3479746715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.773253789
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2644212526
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3251141969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2640977558
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2713052709
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1719705752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.314240957
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3895929860
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.2717932208
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.2868202625
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2788621375
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3911966141
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1396092055
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3845034450
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.1035650478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1438559131
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.555936241
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1718271535
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.86464572
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.360060475
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3425531436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.390773801
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.18223962
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2571043381
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.362356168
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.275933692
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1417900807
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3698212383
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.430248865
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1889383638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.940796836
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3692270002
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1209673123
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.1304133976
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3947781203
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2151362377
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.697907695
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2896662265
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.3710837495
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.4034017280
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3189189463
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2026006248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1887879927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2607819532
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1502759208
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3004868994
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.930459764
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2706989335
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.1351405684
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2722333386
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2739819974
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.275334840
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.74714083
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3594217773
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.2324508500
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2920960886
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2831739933
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2067947670
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.2203277510
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.3151492247
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.4101055225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3218075918
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2906649162
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1358114347
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3176792557
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.1365033618
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.340813403
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1652501933
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.2191047629
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.956511022
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.901925414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1078561395
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.4148368056
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.2405037880
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2087651762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2951308768
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1386328031
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.161568828
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.2318473505
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.2973722464
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3866068632
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2184531828
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1630328580
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3537606424
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.75319882
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.2450086759
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1840999629
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3703927094
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3304444441
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1402777167
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3919277137
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3530906715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3892431726
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2906159399
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.237758205
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.1760089457
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3111273473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2034084958
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1669315682
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.2021412761
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.21975105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2017468498
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.1068994895
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2458529174
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2819918793
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2091518414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2954962668
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1862903915
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1968179948
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2702081367
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.2293705035
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.3232494744
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.97086509
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.2732466332
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.917656952
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2706329177
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.37442986
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2255379715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3316322745
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1389367866
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.4063161417
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2758074815
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.3056369116
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.87570495
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.4284409133
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.121559051
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.3418037558
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3747951834
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2513607317
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2871985277
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.461355753
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1074960779
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1970421884
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.3467485092
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.2950393150
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.318883729
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1461293507
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.4137156747
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2936694151
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.527633577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.3511651504
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3437666845
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3953469505
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2039667912
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3495325455
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1257797248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2203272954
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.709942913
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.1117443194
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1670109654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2950014219
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.539396094
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.2384733266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1928046866
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.4145594360
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2689346834
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2725981799
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3815634064
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3408010277
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.247126894
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.241209036
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4242026046
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2457761414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2278584597
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2878021576
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.572182700
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3110230
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3856758073
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2193790279
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3823139331
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.4025241509
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.3874146503
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.4008219013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3571807300
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3582833750
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1717865867
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.689506546
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2718634650
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2732311790
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2741697085
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.2015123512
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2924301349
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1590556431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.412345408
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2999075190
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.4284708503
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.530599352
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1855429388
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.786641755
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.668206386
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.3337849057
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.38188062
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3713458590
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1529000038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.3336119044
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.4263010541
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.97734588
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.1650437003
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.560562863
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3515905531
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.2891764433
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1324375335
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3710245382
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3014331770
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.673245559
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2357900322
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2366578669
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2761926512
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.245837406
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.167790083
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2157884862
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.218208923
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.797782755
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.3477394153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1928950
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.2341911841
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.183070746
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2426965567
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3195897241
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1128640199
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.457595058
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1776615707
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4235113084
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3458041099
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2542064634
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1819312762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.495677118
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2247776423
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1866264217
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2125940984
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3323823075
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.3475458293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.748361550
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3086308990
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.3257070521
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.3377195295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.825959728
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1971327087
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.270434108
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.2519812976
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.2211039933
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1875660740
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1470853083
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2134664654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3992156819
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3129520845
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2439265436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2327641988
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1373484958
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1082030322
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.3327704713
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1141575144
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3189728583
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2731948447
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3429653693
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.4104122028
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1073466632
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3975122351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1800288672
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.2360842307
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3843389756
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3317456111
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2526667004
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.2132319295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1098571916
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.797401715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.4080105151
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.3606589691
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.36208692
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.446271969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.923182702
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2864534928
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.610928273
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3514118311
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.4175098416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2533174441
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3421895909
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.3110897588
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1612200784
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3291108762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.408280827
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2583254946
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1957758493
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4095848831
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1765528645
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.313937849
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3535964549
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2401564450
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.823646705
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.3292629126
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2239669580
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1512594689
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1142014299
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1048486841
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1473121430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.152751115
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3628221030
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3969198917
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3057865919
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3418012908
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.608326554
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2543906827
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2224281081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3810648776
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3169990318
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2733122627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.719758758
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1477254847
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.4002471236
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3593308952
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1610305667
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2184594922
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4275711458
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2480947992
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3392293766
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1292158227
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1062943737
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3925787501
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1356201518
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3839180129
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2267985017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2967299617
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1143366866
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3850900018
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.3750326902
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.410333745
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.4116043713
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.629881285
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3875085225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.189243755
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3831566462
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2693287945
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.250660984
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.1672336681
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2791622826
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3087563788
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.3975095595
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3126501247
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.751135312
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4275843718
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3720483414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.1064508886
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.3819650759
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.3852801218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1379425435
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.18678721
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.3096175726
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.4076225544
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.4177932922
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1135702184
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.920675566
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1307684588
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3223553471
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.623283967
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1006272316
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2297839000
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3552429019
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3257093715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2695726360
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.2819412518
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.213939889
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.2982309524
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1611984514
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.311839753
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2430162834
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.4094636117
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4122435397
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3544905539
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.3252207405
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2631661124
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2888643772
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.3096838041
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.1767773675
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3590171757
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1034161023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.155432871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2278450587
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.4185585065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4032148167
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.331087763
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.530940727
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3604549960
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2725407626
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1138924274
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1237230335
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.2491123501
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1557570446
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.995332740
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.3060400564
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.2758398589
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3155439940
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2362570874
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1769305891
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.1647999792
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2285903760
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2884281568
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1673344245
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.4025590017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.595026089
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2274675305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3409517176
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3070333191
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.518000379
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2388928755
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3111179948
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2817096417
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.248426726
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.749284602
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3262868957
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3917817494
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1141555470
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3283804583
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.250270121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.4162295567
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.2867417949
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1364691257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.3831224115
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2158338
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.114982420
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.4061413148
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.179589616
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3816289585
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.640484919
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2908133647
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.1630872952
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2492111701
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.772663943
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1622854567
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.1210555257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1680664639
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.77594075
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.2705613840
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.24701559
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2726600308
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.3549151272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3363981503
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4182871977
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1435142366
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3912531661
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.611180532
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.309460122
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1903363553
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2907512694
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.1365899123
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3597752371
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4288242724
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1177023451
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.1627059481
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.666428945
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1059210122
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2525004382
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.690082134
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.3928807069
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3490632427
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1835520561
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.647615244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3680991772
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.1761065961
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2073390485
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3783656707
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1333062674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1764270290
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1133860129
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3173889305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3584087296
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3936670038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2897126132
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2313524334
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2177537960
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3044665963
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.3247931954
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.2209991834
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1985729667
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3205228949
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3778093096
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3548451572
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.417603285
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.592676125
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1227631238
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.631376140
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2631815797
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4243257853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.433175186
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.3884392382
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1316877295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.4094999257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.1951318087
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.2152980605
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2118338445
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1192515589
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3090111444
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3795341028
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.854282926
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2778883473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3863950468
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3569260771
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.442379017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.542680050
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2417166844
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.945013699
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3778420379
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.3907558823
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.3280002998
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.944951315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3157594805
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3771959126
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2988837630
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.1928699292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2742515861
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3705791857
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2083762133
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1293399065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.4277853579
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2755467862
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.67017211
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.2376904928
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.3487941232
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1924085143
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.940941969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2846398791
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.2045102117
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3113869902
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3518537483
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2482879358
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.4242056621
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.1017662334
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1071515385
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.946641444
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.2727331385
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1476798524
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.675653291
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.2991425044
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2300460173
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.4040139099
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2370035441
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4148433060
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2801140955
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1883842493
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1146570065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.843694186
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1351145561
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.885562574
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2930159736
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.1870998208
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2856158047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1549482183
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.3537416260
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.983731047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3649952225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2797991594
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4206697419
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.802283544
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.290854152
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.143084716
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1066919312
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2684155429
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.950929528
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3359140040
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.559606152
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.1961439622
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3637409075
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.2849689272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2324674676
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.744025671
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.2214918954
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.761953741
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2240326224
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2137575819
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.156433542
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3354744340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.3220194417
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3797127088
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.853384650
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.3926298548
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.4257910806
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4075534352
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2755947068
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1819769351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.3981638783
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3534659497
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1488649604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.997031218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.1523958884
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.147311057
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.4094080600
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1522804281
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3910968906
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3297053410
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3987098632
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3439535415
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.789757392
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2872260379
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.599954553
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2087057740
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.2452478558
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1612423087
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2038799960
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2295368395
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.4114018903
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.317656272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1561495830
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2920128023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2773483430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2424890659
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.3572542501
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2416098248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1314936931
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3109742460
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3943486901
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.1233848765
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3348439429
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3800240682
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.2538463597
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.3912641305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.279736989
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.152570028
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3338628927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.4050131429
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.3845432378
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.572986149
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2469335379
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.648227390
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3243138407
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.244826990
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2996405743
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3017819349
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.415339588
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.1245921469
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.789614410
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3960768090
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.3928899226
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.71537735
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3097731793
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2068117274
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2332647062
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2963092087
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1045982281
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2047073634
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2191884988
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2535070103
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3906396393
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3654133376
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1728278160
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2482048212
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.4162423245
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.786334107
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3834964930
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2690422596
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2147472913
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.992186837
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.722301243
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1011722812
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.582261772
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.579984946
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3388385559
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.2269606719
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2804488113
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2199495131
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3290216176
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3462330509
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3488442509
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.4206092248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.361620047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.2870993513
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2725124288
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1530323004
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.1933543147
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.855203732
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2531151907
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.723525603
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.2088089725
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2496672831
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.74693768
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2243898361
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.279068923
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3188495569
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2293397744
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1208954529
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1802749784
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1237833633
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3063609929
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.584895757
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.4049999708
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2557381470
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3512400590
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1054413180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1191699645
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1221766832
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.1543706766
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.2526414364
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.4284091198
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.234839249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3757483589
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1830299221
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.4000324698
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.641096715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.344401461
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2149467523
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.4110472538
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.309972714
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.535506218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4211735574
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.1019297371
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2869445359
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2079974354
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.867157374
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3873121105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3251185237
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1912964179
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.1036842540
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2059364121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1735825257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.306695909
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1775771868
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.4105054720
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3376002878
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1163016200
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.307697051
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.834103950
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.883540733
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.347146507
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1594486410
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.909046198
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3672005057
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2203789115
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1738332556
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.324325472
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1725110856
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4093555522
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2973268916
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3618715579
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.539965298
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2094047045
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2686926682
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3039485301
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.433331612
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2121631784
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.369840585
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3979175011
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.55646474
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.936048277
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1918677149
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1837848297
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.3836107074
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.3596718349
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3838047871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.517160611
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3539082356
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.4000554381
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2744876231
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3711574638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.906771449
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3833724751
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.382166052
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1209959787
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3160056196
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.132503535
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1618612974
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1265703543
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3861862234
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.99019500
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.1095521849
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.953489635
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1034156903
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.4294360927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2619321648
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3016209511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1437685412
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2350998420
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4004585182
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1791026924
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.3386740627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.954220209
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2293865900
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.4287663060
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.484901743
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2771783096
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.4245282148
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2495930727
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.139324816
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.108924449
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3647549400
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2852639107
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3796052494
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1434369703
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3440189817
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2984801464
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3251908578
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1927017520
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.1969909764
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3508822148
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1087134194
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1788939351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.98344093
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.2001499397
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2370317806
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1770220790
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.2301842233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2539167154
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.3832998296
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.731008303
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2181382710
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2887169430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.3098071400
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.4254116925
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2169089244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2907311490
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.3308234046
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1766556914
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4050755603
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3689486121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.834694239
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.963006786
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3906397153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1181158360
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3751442262
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2994105678
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.2930517769
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.554850150
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4119210895
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3765001652
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2348976247
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2567441093
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2370827722
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.292096653
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3578072537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2051138829
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2641362931
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3662007295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.883694822
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2054016668
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.714655852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3221784712
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.148224662
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.710299801
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.925353425
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.4094408187
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3733432127
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1597838577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.582696880
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2988745284
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2082962894
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2300672802
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.322651572
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.1257418405
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2601587375
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.658217278
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.89516515
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1672066051
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1930446885
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.124575912
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.4000994103
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4057433431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.4131867616
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3289040235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4281735628
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3458712988
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.1952554904
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.1770930013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4252348001
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.117023024
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2367863961
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.515760899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3892968211
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3358578591
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.25683296
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.3726792585
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.581435346
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.249746066
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.3023290615
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.473864404
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3825210956
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.255507326
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1451985956
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3003648536
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1255189008
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.434625707
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2837884761
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2407937320
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.299435206
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.3555557435
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1616373192
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3767571349
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.856106430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1380733212
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3046864504
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.2230818262
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.2242759163
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.699119342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.451662676
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.460746143
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.159884325
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.215227938
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.2731911953
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1945689391
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1438889520
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3852026404
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.1684329264
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3573217030
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1656902085
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3892515085
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.4257598764
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3999311587
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.396170098
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.123203666
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2650884949
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.911755165
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.2603099433
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.182898169
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.432265759
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.888655534
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.144011913
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.564823580
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3814703544
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1492664104
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1139507244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.4063229359
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.2500090894
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1252238934
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1449819264
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1584231713
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3879269705
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.406516797
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2341860986
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.422028523
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3947072337
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.2437892856
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3722764684
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.4194794540
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2574983661
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.4218359537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3067636640
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2306289640
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4107646526
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.4156907081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.4221593326
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2079140411
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.3842628778
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1994665237
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.1814357366
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1782498233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.3332629613
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.43551825
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.261827984
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.2696285645
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.2316838270
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3702838598
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1851650355
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.3456221810
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.3686461860
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1741354592
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.764391738
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2556888065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3435396006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1160302411
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.466212437
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.934937179
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2431240852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1941156315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.1308410691
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.941586647
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.1649246517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3434199628
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2240649262
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1005898167
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3107513378
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.1706817430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.686952477
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3268449643
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2151563595
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1666955838
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.309379651
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2912786698
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1344666672
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3621944475
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.282011326
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.3722227295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3466062996
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.4040654939
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2953703816
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.722681068
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.2188594112
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1025733063
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1830083293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.2990028819
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.3586392040
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3803509868
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2616249511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.1979836649
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1756088491
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1351667201
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1623068861
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.3673233913
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3286711121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.85808292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.3576672656
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3975980782
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1426291576
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.1734350626
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.2902819313
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.632542425
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2228673266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1665106386
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2804078488
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3554686469
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.340541293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3798519754
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.686660000
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3127685234
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2978062661
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.1785061547
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.167765038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3762225156
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.1771964153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3074980072
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.370215434
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1232324105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.3338359581
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.227047506
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3977705398
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2605250475
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.794724744
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1325897888
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3494098170
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3709634287
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2304152611
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.564592244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3756134957
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4100386752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2464071800
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.1858350120
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3388983577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.3334449814
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.3003074474
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.229739700
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.212739381
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2035257809
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2015905750
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2091559143
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.2564181127
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1191485894
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.781002730
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2236271809
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1503230180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1792480443
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1262692633
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1214835649
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.3862331959
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2041211495
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.1034413309
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2668398323
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2997150638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.4006917676
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2089902578
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3297408787
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1736976637
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1193747225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.4189383737
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3259821248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3229029598
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.2526194013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.3485287090
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2196965645
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.424311012
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.1686114256
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.4018033035
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3954290294
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.1302926558
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1400545392
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.4142283768
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1794959362
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.632688911
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3060031390
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2794925255
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.2062795895
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3800237199
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3329880061
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3833383676
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3813741251
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.4025920375
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2740627034
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.678730011
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.135218085
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.2649346701
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3939683062
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.1812591571
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.741219079
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.946372805
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.3254296966
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1887500211
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3155335531
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2389017551
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1532965295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3978419671
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2387179221
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1042373933
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.230668561
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2549147800
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3429261936
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.4035981377
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1261719571
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2348324503
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.1054223682
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.2188866127
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.1651583048
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.13641376
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2088192995
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.774076630
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3717580622
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.4034128359
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.3893371601
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.2900216011
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.161419215
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3670306345
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.1397007963
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3735815953
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4153274190
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.1768320390
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2355762617
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.740400359
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1625612459
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.1582527641
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.500037009
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.2740249865
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.560590260
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3432669212
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.262182105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.313132729
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.700542339
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2030758530
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.808677062
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1720676018
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3120867120
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2979399986
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.4124375418
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.439542666
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2473922820
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.503255426
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2539453016
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3127869328
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.3349238949
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3638754833
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3494830235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3399704858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.1516421560
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4212773980
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1234133409
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3901339338
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.1041680457
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2570806679
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2800715261
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.3326981803
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2376936959
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2060364347
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3992360781
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.601297328
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.2911051416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1257635154
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3627421641
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.4022746396
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1523318921
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.240823716
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.490710025
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1999542910
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1946611766
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1220996280
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1328595478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.169077412
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.205643351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3202704611
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3269913591
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1100887990
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3115739020
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.3427953233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.2015133159
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3295725118
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1924022879
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2448200759
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.976544689
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2334212251
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.3753626688
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3608847880
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1394284379
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1532528551
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.1066407272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.793805004
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4094268170
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.899788814
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1322811445
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3719031733
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.79421159
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.794046033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3774167420
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.4192698452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2109830640
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3293365837
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.827491700
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.2785987330
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1503888289
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.4218663141
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3375171091
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1197799186
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.581404954
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2840831887
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.4164489385
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.3244815008
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.260526769
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.7199748
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3803388429
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2269684257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3098805554
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2439209359
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1005627078
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.46809646
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1543678605
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1857004688
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2555572030
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3250634110
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3112477791
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.3336004342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3708072722
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.148121253
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3243799012
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.4225843644
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2330469362
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.574306335
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.600625638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.1358411896
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.201295428
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2371629315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.92160131
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.780665532
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3820252829
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.37159153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2009290559
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2315587922
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2938598473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3430763085
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2277275323
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.746624282
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1706871342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2445912375
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.2515378914
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1268380675
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2638564852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.749144853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.3203762810
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.4229632716
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.468893209
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2328325830
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2813521011
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3049077180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.975825947
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1627573389
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1450019452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2304554235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3412627411
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3966822893
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.504973509
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.4189172404
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.2788960332
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3379560257
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3944925518
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2503746983
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.1540619995
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.1452089917
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.3290112076
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.133119641
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.276083527
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2004856568
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.705339803
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2418633322
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.381608468
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.162048417
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.905384904
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1887297707
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.773640297
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2742360003
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3286222300
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.694151099
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2423129125
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.2640184007
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.2987963931
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.1453477626
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.3575978031
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3923128542
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1412885113
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.683983187
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1161733708
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4162020536
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.635363696
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.522244235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1220869994
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1644941014
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.529101837
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2126746932
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.4031714180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3468918886
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.4192890394
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3859918121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.1191662779
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3829873222
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1691257858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1752126022
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.3333003334
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.3820557791
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1539936873
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.993398551
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3497509449
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.621576075
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2613761049
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4187585595
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.2509055381
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.4930639
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3286965033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.15011138
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1175399253
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.580810195
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1648453383
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1233058560
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3887355772
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2912781545
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.1302092013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.1594055222
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.84973186
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.309518365
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.2521082796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3881264361
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3481642654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3793571361
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2224286659
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1731883223
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2228867775
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.758489557
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.447126025
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4004604728
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.413630474
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.4069937864
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.172437406
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.1836516075
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2487612912
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3372310585
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1205267661
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.2012536799
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2087089622
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.970762835
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.650079395
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2561631222
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.712621720
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2057180251
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2746473033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2938931785
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.2507104843
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4293451925
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1444870181
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.1317905076
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.808549431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.2811924013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.2774982505
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2646635612
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.590890242
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.2647917742
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1505018463
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.444511244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.185638394
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1455604130
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1527468038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1167915957
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2813342610
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.213507439
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.716787281
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3861316873
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2132158361
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.1688104861
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1068224077
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.1664118096
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.4266073302
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.553009183
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3120742895
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3421689130
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2041423089
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1018955707
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.41646408
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1993968465
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3657043653
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1895629965
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3579008610
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.1297643409
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.4216321710
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.221968
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1926178890
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1653397844
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.406111566
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3732169347
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.193171195
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.55664493
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.602690673
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2821536097
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.3379740388
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3088380040
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3593942784
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3134445924
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.4035569457
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3238151614
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2256424249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3128860644
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3080643973
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1421374476
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.354338166
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3473085494
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.1417924718
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.992694299
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.1299499457
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3022328903
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.1148051234
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.2963528259
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1285051005
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3711015305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2999443554
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.3450503947
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.1532583140
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.374800003
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3498432704
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.4199331763
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.50103033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1666434463
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.4271973343
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2516737038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.13249025
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.804915294
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.2687645231
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2613601361
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.1466552132
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.889541062
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.456061297
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.361251891
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.1723097965
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2069713478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1808727108
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1606209287
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3021307231
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3448620235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1343427077
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3792837839
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3128975538
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1636857961
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.927571016
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.1997411345
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3854144463
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1021400517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.858705947
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.1187750612
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2064122305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1948744638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2828917430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.73559823
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2212684848
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.389461393
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.195074311
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2077974356
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2039775300
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3885298292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.463396641
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3188871683
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.3785714226
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2337779220
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.9525656
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2398362821
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1253622014
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1025712659
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2784336077
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2963457250
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.622063625
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.512980225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3038611188
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.4089369948
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3351839367
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2877546215
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2318826573
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.2600555853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.4163081309
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.3004246774
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1104895701
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1883584872
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.505291265
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.404360591
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.1817699811
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.4263086416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2507178174
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3989069564
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3331520704
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1118687109
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.846651951
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.92675283
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.1798827985
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.768441674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.4039034156
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.157062529
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3961820353
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.1186892430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.3376191788
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1467027250
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.1507657858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.2473372462
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2944843010
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1275712218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1195407064
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.166884478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.689526432
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1211494084
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2178167924
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.2244701401
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1128448340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.853005059
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2406167718
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3314085334
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2211998237
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3122802546
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3257462789
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2365159929
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1489783751
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.3094306290
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.439294372
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1444720619
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2476529752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1717943795
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2161386881
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1193649852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2252470105
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2083542911
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1468733340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1402137787
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.940467419
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1006147815
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.984489182
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1102088206
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.907377899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.661520871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.2861113261
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2785620674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1767246792
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3224879433
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1332663780
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1212886131
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.334154013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.175931588
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.1275152586
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1466784266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3910572767
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2972658658
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.297842440
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3338315129
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.34725033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3076039737
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3452881044
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3439381826
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.395840400
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.2968549436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.4152433458
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.3042942927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.689469479
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.238696229
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.964466947
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2059664804
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.3125161656
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.3562162088
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2957195807
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.845643430
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3493130952
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1505675149
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.121548819
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1933937869
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.222344763
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2333628248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.1987885746
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.733540805
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3687683650
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.112412567
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.1578636268
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1111526776
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.867854196
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2020552318
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.521994897
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.706430779
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1843188448
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1863124006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1333851695
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1819868517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1933523477
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.508630896
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.1487983727
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.3876612494
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.2262802528
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.3573586332
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1822978489
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.725104755
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1711932107
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.3220226079
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.337522852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2683172965
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.2095111950
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.3203634483
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2032633453
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4046085627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.2710512657
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2786518663
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3291765091
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3965567846
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.3744457017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.1749888092
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.1445789313
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.2713767677
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.58031080
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.2044452761
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.1950718448
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.2781556073
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.991227899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.3678870336
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.707052598
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.1049559526
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3302760471
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.799106118
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.920965706
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.669956866
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.800310386
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.748535714
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.1496652815
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.453428797
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.1796674156
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.2743008032
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.1211053627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.3094844722
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.3240975114
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.2476904478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2457915304
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1841411531
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.3549994640
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.3434324450
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2906244757
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.4138250973
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.971790492
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.1325229702
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2721129110
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1392603019
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.4058174204
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.1180085244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.1036802024
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.2518059836
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.3940499248
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.248412247
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.1066300072
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.1245799282
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.897655824
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2985524160
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.1670838621
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.2304905823
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1838113318
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1604285327
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.1891228307
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.3686980493
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.953508940
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2356241282
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.3818673580
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.1169452497
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.152127517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.1888442291
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.719864919
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.657320800
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.3439116017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.3796172431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.2445641865
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3683258965
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.2161940526
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2088059363
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.650123761
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1574157419
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.1647892309
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.1568686799
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.727670903
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2951057091
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.2850292876
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.2942732286
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1127818788
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.3049257627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.3974658627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.3898653753
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.2200304307
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.1432454560
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.45231471
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.4073658340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.1469978796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.1476821714
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1419139476
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.209099546
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.3564489832
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.1035984073
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2653131988
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1181343142
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.770824017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.4174649853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.1782337655
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.50198266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.126033156
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.758340769
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.2406456407
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.3276901365
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3794870274
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3688393886
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.1124031436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.1469532867
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3152306932
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.726597715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.2515362390
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2455400219
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3563373002
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2161702129
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.2022698833
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.938126845
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1234789305
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.1273244198
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.1860954443
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3848122765
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.624480999
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1732668905
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2468736233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3446029116
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2138524438
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.831342067
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.970538901
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.359463969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2950313513
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3723380473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.2089998402
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4240357464
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.524951240
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3722340291
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.986089782
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1451684926
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2789325209
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2503195342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4262001754
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1587941861
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2368805069
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2932916040
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2810008940
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.83697129
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.2680851698
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2094286449
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.2878103742
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3171880918
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.4174326888
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.155150920
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.4546582
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1743548018
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.1508246867
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.3659671537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3180008190
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2237774170
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.2436567565
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2400793452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.446219428
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.3093436488
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2932102769
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.1633324796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.4200767854
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.874206852
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.47383752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.843347104
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4245917666
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1959144563
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2260930423
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2853374121
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.3542467403
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1913843342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.4189452592
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2509410371
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1718712223
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.2883613609
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.499297306
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1018493031
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2230894896
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2686249500
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.2271188521
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.757158354
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.543075429
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.740556428
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1426447293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.1036997562
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.4287763142
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3368346858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1124771225
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3859743762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.1134056236
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1280049055
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2210995281
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.260461090
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.3977695081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2741167024
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.457865414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.579923109
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1715504080
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.139436694
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1142364953
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1608137601
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.257151213
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3397516666
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3105973175
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.739942384
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1708366613
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3157354272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3041725218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.247372935
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3887917009
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1374941739
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3173144495
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.3991747898
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.287910166
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1811666601
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3769929356
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.745164733
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.258350796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.558644368
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2102369699
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.2568134383
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.3714212290
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4110965674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1535208431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.535720006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3118402489
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2924071327
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3499104006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2825717698
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1920805612
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.128196796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3432902260
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1713991631
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.4256747425
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3749667028
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.981314096
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1212746244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.235091244
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2345511395
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.616095669
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1097969752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2057871963
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3879613064
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.421335324
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1718067872
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2192632277
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.918921931
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.4233380259
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1897091210
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2746232793
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.4224878159
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3870200904
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1379988778
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.16953961
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1809217754
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.1204481092
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3849369689
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1587332738
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.1116160285
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2064138019
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2015791927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2055983235
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2991114080
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.652127133
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2081224103
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1493618630
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.4178637774
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2359138298
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1261842292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3143998320
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2440828424
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1621175163
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.4114732841
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3825439684
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1392094576
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.199675243
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.4115587973
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3037102081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3317909017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.3483163604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3901001387
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2994679243
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2783644630
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2333737608
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1947768969
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3512582692
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3671775328
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.631480574
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3769338935
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2853799399
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.295667482
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2659622108
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4237599332
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2650279698
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3584876586
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2387845140
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.387670995
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.431911016
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.2593264089
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.706139148
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2340382352
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.833627263
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.363603357
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4288931511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.2720360537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3054344388
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1331962470
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3706493632
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2620130668
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1341685611
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1662309646
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2207145661
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2594636295
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2874626396
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.897156180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2594981077
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1593158529
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3235376233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1273026376
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3970623802
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2378062535
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.410445422
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2068193312
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1798352245
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.2197271177
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.799252186
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1071503718
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.2840814907
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3239811604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.2659548201
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.1376003888
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.991417759
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3451061532
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.3513167167
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3095134206
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1693568255
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.2326916036
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.62189504
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.897620314
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2135192742
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3270207206
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3995844702
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1507752604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1062980064
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3731954310
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2866385606
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1307040572
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3415076815
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1757392071
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.930254792
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2502065654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.100667943
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2294893935
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4107362835
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1047133021
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3396947789
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1324946537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3397388614
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.826243416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.245316984
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.213023218
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.115138342
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1390055526
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2879554937
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2777810589
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3416295733
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1635847269
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2277484587
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2976618424
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1411941744
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4033276582
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.2078856970
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.703192273
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.86608641
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2308841916
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.840586563
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.457412182
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.4281304040
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4078506496
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1905346968
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1783699643
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1399297278
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.913423114
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1169362989
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2918508586
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3318412133
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.771198610
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.192017002
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2857854413
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1266491749
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2652885905
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1437224194
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3212592818
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1226680381
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2845407653
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3326931115
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2216153550
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.2215412202
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2515149356
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1609255551
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.438349230
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.1326746444
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.886474948
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.121327799
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2133395301
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1284093249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1831358090
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.552497311
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1704380694
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.4258252538
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1606460536
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.284874125
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2011831027
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.423454292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4126807577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.774632069
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.3744497351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.129812684
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2705958202
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1626657577
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4117652049
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2156208475
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.905312193
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.1512232580
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3939183556
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2693515337
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2570686404
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.797994232
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.3230891723
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1538845262
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.883414502
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3850974196
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.523364753
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2924166516
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4076028230
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2622984279
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1316736655
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.233518551
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.4207841618
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.1080077450
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1191622087
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.2942970118
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2998029614
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4294962118
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1310026151
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2992758665
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.1859739355
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3003226673
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.376852411
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.836599044
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.667590539
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4155757173
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1849447576
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3522588047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1509928617
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3242456521
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.3230348161
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.2941800548
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.1063879627
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.3132156662
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.3861880522
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4249518671
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.957760112
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.471816591
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.320683443
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2355887638
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1243416166
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1043811626
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2417198865
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1879410511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2592944053
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3450783074
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.127857045
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1223559623
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1938195112
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2974119111
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1801599763
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3802733929
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2006953079
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1626828027
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3302491985
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.463490605
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.507445286
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4080265180
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1888609274
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3598834428
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.668630574
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.725325138
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.911901617
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.369738246
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2728348071
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3238904887
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.2710701783
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3393412436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3317964658
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3446175788
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.335712708
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1235749106
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1093504607
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2978168890
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.376439047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3952939272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2835044699
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.23061023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.1627967858
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.4206260499
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2801529109
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.710556674
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2240418687
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1252208870
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1067666881
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4184172038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3438017412
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3293359598
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3431618023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1240510800
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2902479024
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1106518685
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.525004020
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.703566333
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1390074360
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.909660201
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.3450550401
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1902790474
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1509337082
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2527487738
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.3615488317
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2613277787
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1066755868
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.3149663208
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3698799497
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1158275546
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.789131340
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.562990173
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.1236263568
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.1359815936
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.2565298847
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.406639190
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1168725812
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1928637712
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2337216924
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.954548579
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.4135520599
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.1745237477
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1938618125
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.4222081427
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.3037657871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.520560292
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.1345983315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.3318341853
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3736764664
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3758956019
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.2540877329
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.351263824
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3220287166
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.118708386
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.4277131081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1013953215
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.4050404096
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2399520517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4154647788
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.2500164944
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.658189902
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.1545092924
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4214539843
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.3406653958
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2593470905
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.677814731
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592014188
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.1026570036
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.353188917
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2854351579
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3016434704
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1683093436
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.215593715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2777561717
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.277856825
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1526711098
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2235261709
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2077459867
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2305148249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3982274151
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.4086429304
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2734312266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3391319249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.154328014
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.1432497269
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.225557851
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.265546921
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.610567511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2275278415
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.1466348410
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.1921250553
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1375965111
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.2232964844
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3277762733
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3880201162
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3953970946
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3347146047
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.2361315398
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1392124238
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2669154137
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1566207380
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1027802923
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.196844995
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1415390655
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3808378602
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3801421684
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2720179575
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.478936851
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2581167694
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.596170473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1152991473
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2271804403
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1131203341
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.3935470261
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1013581450
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2228887414
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.1025144977
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1732209964
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3258023752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1047543531
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.3772700716
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2756352071
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2532099321
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.3002379084
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3960504023
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.3089753127
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.2460596472
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.834138074
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3765857229
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.4230612978
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3964168410
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.4144673795
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.1254215052
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.83984137
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.1989003595
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3828803242
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.4108868363
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.1340832018
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3931009896
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.88630195
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3955119665
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1505164136
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4209207203
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2408769123
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2908864877
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2054663025
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2786133476
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2554276859
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2500836294
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2531031838
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3956622182
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3982899111
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.3005696749
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1377042139
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.2462169801
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.3589594317
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2308789478
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3388136016
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4240086469
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1182816058
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.2684845084
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.1024046351
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.4258132201
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.737285737
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4011076208
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.3151034397
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.761202608
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1117635916
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.617100765
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1658788504
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1039895431
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.2593510113
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2450318010
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2692332665
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2289290211
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.1229381651
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1504664128
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.220285387
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4179044995
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3508776066
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.4023186601
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1693113949
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2975919590
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.533611953
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.782131193
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1669490720
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2234729032
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.3928759565
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.1978615175
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1145086099
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.1732901287
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1519832233
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4112255068
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1076204960
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.188695724
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2186246840
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.1167999814
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2687461710
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.1311027134
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2378526814
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1023648025
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1855499593
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1940302452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2968304171
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2294046980
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.1831288779
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.2072265708
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.635487168
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1823129515
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.1334676143
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.705966950
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1986155495
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.753981416
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.776500383
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3526439511
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3924256527
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.571418271
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2123416654
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.254533576
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1676726197
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.181009426
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.10209581
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.408981775
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3287713192
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2192412017
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1111234021
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4204643981
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2857391014
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.344848486
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.904257982
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2548950963
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.505547330
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.23629081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2148465250
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.811997965
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3105691249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3936664338
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2949000033
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1474978293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.675393688
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2396879285
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.190015629
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1328976256
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.2341832104
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.918610945
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3341208998
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3331469242
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3794024822
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3874982370
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.242920848
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.4270752649
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.957032760
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2915805935
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3742076593
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1603518373
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.3598732745
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.2892408899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4283086736
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3683930435
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1115838874
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.1502955482
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3058810844
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3514328899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1889360020
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.667868633
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2057256857
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1151342020
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4149604926
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2355067266
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.1321448205
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.882367174
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4010691603
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3214688291
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.1990618537
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3786842826
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.477639547
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2842113985
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.2826596880
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.739906335
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.2096046212
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2641880231
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2779500517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3214525712
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3229746981
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1457037803
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.1665268856
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1525643800
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.325684604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2030297549
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2509649480
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.626635143
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3242126341
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.320211291
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.232057039
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.3659307708
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.190871631
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.4077757422
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.2566181770
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.903442748
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2241130353
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3186078894
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303197667
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.546083517
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.426392893
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3066854849
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1701578081
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.534738264
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.288270651
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.3923950604
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.623662474
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3329790272
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2028361557
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3438193420
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.3596327870
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3834357605
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.284710693
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3243961267
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2890263796
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.366487263
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1782101447
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.997288341
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.3150879020
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.2576218525
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.4122010990
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.3657547582
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3308237534
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1199413865
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1346158724
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.2780703550
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.376837774
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.1713180443
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050622703
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3692369897
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1711923837
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.316020543
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4114435879
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091861065
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3744511685
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4276749453
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.432422678
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1366862962
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1016317672
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2689573902
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.3615470168
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2626279802
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2437903544
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.1478990285
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1286619369
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.2074082926
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.1907694586
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.392288781
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2392619832
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.2623252976
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2090049293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990940172
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1338264161
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3013495715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.4173337592
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391523190
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3767327095
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1730940397
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142189764
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379505422
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1479334628
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1747647647
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3307607896
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.529288888
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601955049
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3102600456
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3718578131
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1243127833
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.73736116
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380706714
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2693759201
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2722483289
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.1469910135
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839841540
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3718729485
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3983798293
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2193230762
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.4100780639
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1554951920
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069797338
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.4161083927
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451162138
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3001715497
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1596250518
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.217744452
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2482757809
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2686022640
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003971919
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969728475
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888386722
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.612700802
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.631642310
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687474899
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.200498265
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3345595170
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4017109277
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.416644006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1103341871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424453409
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.439590754
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.3954156527
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1884539066
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.388351929
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3576588953
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3998375695
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126866006
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3253652391
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1691004158
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258410671
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.4241105748
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3146476249
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.464205669
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388290513
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3579991962
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2933338460
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.3527376741
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2309881013
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.308529871
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.3286064977
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703655848
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.2946680354
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243703630
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2232510153
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.63449308
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3338695575
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1156849534
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2679189536
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641127488
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1433395049
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.315037259
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.250897112
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879100317
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.379109752
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2696962496
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3232231482
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.5254849
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.721422454
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2281789076
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.811929512
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1345859585
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.967979999
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3817777363
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.963512038
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3468470699
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1149779018
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4100843786
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4150588286
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.600945303
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2778189373
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4108049596
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2303097715
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1499468315
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3414339516



Total test records in report: 2927
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.182316120 Oct 10 01:44:01 AM UTC 24 Oct 10 01:48:24 AM UTC 24 2807494194 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.446219428 Oct 10 01:44:39 AM UTC 24 Oct 10 01:48:49 AM UTC 24 3167354764 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.1633324796 Oct 10 01:47:20 AM UTC 24 Oct 10 01:50:07 AM UTC 24 2822166696 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2440828424 Oct 10 01:45:28 AM UTC 24 Oct 10 01:50:24 AM UTC 24 2900338340 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2932102769 Oct 10 01:46:46 AM UTC 24 Oct 10 01:50:27 AM UTC 24 2800841892 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.3093436488 Oct 10 01:47:17 AM UTC 24 Oct 10 01:50:42 AM UTC 24 2638324234 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1017041522 Oct 10 01:47:23 AM UTC 24 Oct 10 01:51:43 AM UTC 24 3360528258 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.1535820881 Oct 10 01:47:22 AM UTC 24 Oct 10 01:51:46 AM UTC 24 3224967500 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2102369699 Oct 10 01:46:36 AM UTC 24 Oct 10 01:52:08 AM UTC 24 3435782824 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3374540243 Oct 10 01:46:29 AM UTC 24 Oct 10 01:52:09 AM UTC 24 3554033316 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4232706083 Oct 10 01:44:01 AM UTC 24 Oct 10 01:52:09 AM UTC 24 4678011070 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3825439684 Oct 10 01:47:05 AM UTC 24 Oct 10 01:52:10 AM UTC 24 2196390184 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1308404856 Oct 10 01:46:29 AM UTC 24 Oct 10 01:52:32 AM UTC 24 3324234212 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2746232793 Oct 10 01:46:58 AM UTC 24 Oct 10 01:52:35 AM UTC 24 3390687976 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.2874826192 Oct 10 01:43:14 AM UTC 24 Oct 10 01:52:38 AM UTC 24 4502547462 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.3984999652 Oct 10 01:47:21 AM UTC 24 Oct 10 01:53:04 AM UTC 24 3588814816 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.1529615321 Oct 10 01:46:04 AM UTC 24 Oct 10 01:53:51 AM UTC 24 4342344776 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.2012710219 Oct 10 01:44:39 AM UTC 24 Oct 10 01:54:14 AM UTC 24 4361819360 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.1621175163 Oct 10 01:46:14 AM UTC 24 Oct 10 01:54:42 AM UTC 24 3688058040 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3933029184 Oct 10 01:48:07 AM UTC 24 Oct 10 01:55:00 AM UTC 24 3698021752 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1280049055 Oct 10 01:51:05 AM UTC 24 Oct 10 01:55:08 AM UTC 24 3034870374 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2447793611 Oct 10 01:44:52 AM UTC 24 Oct 10 01:55:35 AM UTC 24 4685657138 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1959144563 Oct 10 01:50:02 AM UTC 24 Oct 10 01:55:38 AM UTC 24 3707185340 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1715504080 Oct 10 01:51:18 AM UTC 24 Oct 10 01:55:49 AM UTC 24 2896351292 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.757158354 Oct 10 01:46:05 AM UTC 24 Oct 10 01:55:59 AM UTC 24 4230692328 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1809217754 Oct 10 01:46:58 AM UTC 24 Oct 10 01:56:12 AM UTC 24 4892235051 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1897410602 Oct 10 01:47:05 AM UTC 24 Oct 10 01:56:33 AM UTC 24 3639199256 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1608137601 Oct 10 01:54:36 AM UTC 24 Oct 10 01:57:03 AM UTC 24 3725224478 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.1591991205 Oct 10 01:45:23 AM UTC 24 Oct 10 01:57:16 AM UTC 24 4412980868 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.2779994431 Oct 10 01:46:04 AM UTC 24 Oct 10 01:57:21 AM UTC 24 5165973136 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1142364953 Oct 10 01:54:38 AM UTC 24 Oct 10 01:57:30 AM UTC 24 3657310065 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2328974446 Oct 10 01:54:13 AM UTC 24 Oct 10 01:57:43 AM UTC 24 2585793851 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3397516666 Oct 10 01:56:23 AM UTC 24 Oct 10 01:58:11 AM UTC 24 1892775105 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.16953961 Oct 10 01:47:06 AM UTC 24 Oct 10 01:58:35 AM UTC 24 6696012394 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1426447293 Oct 10 01:45:40 AM UTC 24 Oct 10 01:58:52 AM UTC 24 5117501090 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3840057766 Oct 10 01:54:24 AM UTC 24 Oct 10 01:58:53 AM UTC 24 2627097569 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2450868542 Oct 10 01:46:28 AM UTC 24 Oct 10 01:59:19 AM UTC 24 4640094638 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.4178637774 Oct 10 01:47:15 AM UTC 24 Oct 10 01:59:23 AM UTC 24 4733419388 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.287910166 Oct 10 01:54:33 AM UTC 24 Oct 10 01:59:30 AM UTC 24 3413960767 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.139436694 Oct 10 01:54:48 AM UTC 24 Oct 10 01:59:41 AM UTC 24 3105758416 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.3680472417 Oct 10 01:47:10 AM UTC 24 Oct 10 01:59:48 AM UTC 24 4416132100 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3105973175 Oct 10 01:57:50 AM UTC 24 Oct 10 01:59:49 AM UTC 24 2873579945 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3781985042 Oct 10 01:47:40 AM UTC 24 Oct 10 01:59:49 AM UTC 24 3657431794 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.2057871963 Oct 10 01:56:15 AM UTC 24 Oct 10 02:00:35 AM UTC 24 2553566400 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.740556428 Oct 10 01:47:21 AM UTC 24 Oct 10 02:01:01 AM UTC 24 5427939932 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.543075429 Oct 10 01:47:22 AM UTC 24 Oct 10 02:01:29 AM UTC 24 5346222620 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.258350796 Oct 10 01:51:50 AM UTC 24 Oct 10 02:01:33 AM UTC 24 3898805384 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3118402489 Oct 10 01:57:20 AM UTC 24 Oct 10 02:02:31 AM UTC 24 4364230312 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.3166371858 Oct 10 01:54:15 AM UTC 24 Oct 10 02:02:59 AM UTC 24 5162597490 ps
T670 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.1097969752 Oct 10 01:57:18 AM UTC 24 Oct 10 02:03:00 AM UTC 24 3965403826 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.3991747898 Oct 10 01:54:37 AM UTC 24 Oct 10 02:03:56 AM UTC 24 4763281344 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2081224103 Oct 10 01:46:13 AM UTC 24 Oct 10 02:04:06 AM UTC 24 8154322141 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3432902260 Oct 10 02:01:11 AM UTC 24 Oct 10 02:05:17 AM UTC 24 3067099908 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.918921931 Oct 10 02:01:09 AM UTC 24 Oct 10 02:05:22 AM UTC 24 2963735740 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.257151213 Oct 10 01:54:08 AM UTC 24 Oct 10 02:05:28 AM UTC 24 7102111538 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.47383752 Oct 10 01:49:23 AM UTC 24 Oct 10 02:06:01 AM UTC 24 5895633221 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3842239022 Oct 10 01:57:40 AM UTC 24 Oct 10 02:06:27 AM UTC 24 7666868375 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.981314096 Oct 10 02:00:01 AM UTC 24 Oct 10 02:06:41 AM UTC 24 5078116740 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2737997627 Oct 10 01:58:26 AM UTC 24 Oct 10 02:06:53 AM UTC 24 9714028376 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.874206852 Oct 10 01:49:03 AM UTC 24 Oct 10 02:07:16 AM UTC 24 5407067512 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.4062550809 Oct 10 01:58:18 AM UTC 24 Oct 10 02:07:31 AM UTC 24 5925385866 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2015791927 Oct 10 02:01:19 AM UTC 24 Oct 10 02:07:39 AM UTC 24 3745885331 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.4224878159 Oct 10 01:44:43 AM UTC 24 Oct 10 02:07:52 AM UTC 24 8599933208 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2064138019 Oct 10 02:01:08 AM UTC 24 Oct 10 02:08:00 AM UTC 24 3461770424 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.831342067 Oct 10 02:01:19 AM UTC 24 Oct 10 02:08:40 AM UTC 24 4033820968 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1167968821 Oct 10 01:59:57 AM UTC 24 Oct 10 02:08:58 AM UTC 24 8418014640 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.938126845 Oct 10 02:04:48 AM UTC 24 Oct 10 02:09:12 AM UTC 24 2636840334 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.235091244 Oct 10 02:01:53 AM UTC 24 Oct 10 02:09:22 AM UTC 24 3474781694 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2825717698 Oct 10 01:58:25 AM UTC 24 Oct 10 02:09:36 AM UTC 24 6132619852 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.1860954443 Oct 10 02:06:10 AM UTC 24 Oct 10 02:09:54 AM UTC 24 2354989820 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4245917666 Oct 10 01:51:05 AM UTC 24 Oct 10 02:10:03 AM UTC 24 5388903036 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.970538901 Oct 10 02:01:18 AM UTC 24 Oct 10 02:10:10 AM UTC 24 7387443430 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.2022698833 Oct 10 02:04:47 AM UTC 24 Oct 10 02:11:02 AM UTC 24 3319855830 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.414912800 Oct 10 02:00:50 AM UTC 24 Oct 10 02:11:10 AM UTC 24 6625748292 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.769202229 Oct 10 02:01:17 AM UTC 24 Oct 10 02:11:32 AM UTC 24 4710543150 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.247372935 Oct 10 02:03:40 AM UTC 24 Oct 10 02:11:54 AM UTC 24 3939954334 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.2916141271 Oct 10 02:06:14 AM UTC 24 Oct 10 02:11:54 AM UTC 24 3019683726 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3049583587 Oct 10 02:02:18 AM UTC 24 Oct 10 02:11:56 AM UTC 24 17857102740 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3723380473 Oct 10 02:02:17 AM UTC 24 Oct 10 02:12:52 AM UTC 24 5630283884 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.3848122765 Oct 10 02:06:11 AM UTC 24 Oct 10 02:12:52 AM UTC 24 3202982497 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3749667028 Oct 10 01:57:27 AM UTC 24 Oct 10 02:12:56 AM UTC 24 7971620280 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1811666601 Oct 10 01:52:31 AM UTC 24 Oct 10 02:13:39 AM UTC 24 7758372280 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.2436567565 Oct 10 02:09:34 AM UTC 24 Oct 10 02:13:46 AM UTC 24 3287553644 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.1273244198 Oct 10 02:09:19 AM UTC 24 Oct 10 02:13:57 AM UTC 24 2255421744 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063923301 Oct 10 02:07:51 AM UTC 24 Oct 10 02:14:00 AM UTC 24 3918156888 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.155150920 Oct 10 02:10:14 AM UTC 24 Oct 10 02:14:35 AM UTC 24 2608672424 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1732668905 Oct 10 02:09:12 AM UTC 24 Oct 10 02:15:04 AM UTC 24 3217367349 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2237774170 Oct 10 02:10:51 AM UTC 24 Oct 10 02:15:08 AM UTC 24 3105073256 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.2138524438 Oct 10 02:07:02 AM UTC 24 Oct 10 02:15:09 AM UTC 24 4171244910 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2924071327 Oct 10 01:58:26 AM UTC 24 Oct 10 02:15:19 AM UTC 24 10573656002 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.2468736233 Oct 10 02:06:38 AM UTC 24 Oct 10 02:16:03 AM UTC 24 4485123908 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.499297306 Oct 10 02:13:03 AM UTC 24 Oct 10 02:16:21 AM UTC 24 2691778185 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.2040772036 Oct 10 01:56:50 AM UTC 24 Oct 10 02:16:22 AM UTC 24 11184578620 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1261842292 Oct 10 01:43:59 AM UTC 24 Oct 10 02:16:29 AM UTC 24 8040331328 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.745164733 Oct 10 01:54:33 AM UTC 24 Oct 10 02:16:49 AM UTC 24 8395050840 ps
T671 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.2883613609 Oct 10 02:13:02 AM UTC 24 Oct 10 02:17:14 AM UTC 24 3266155892 ps
T672 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2686249500 Oct 10 02:12:56 AM UTC 24 Oct 10 02:17:19 AM UTC 24 2688539296 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3769929356 Oct 10 01:52:31 AM UTC 24 Oct 10 02:17:22 AM UTC 24 9202276332 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.945212594 Oct 10 02:04:44 AM UTC 24 Oct 10 02:18:11 AM UTC 24 4520405934 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1718712223 Oct 10 02:12:09 AM UTC 24 Oct 10 02:18:24 AM UTC 24 2792268158 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3046491122 Oct 10 02:09:23 AM UTC 24 Oct 10 02:18:29 AM UTC 24 3096519014 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.4174326888 Oct 10 02:10:51 AM UTC 24 Oct 10 02:18:32 AM UTC 24 4407849510 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3887917009 Oct 10 02:02:18 AM UTC 24 Oct 10 02:18:59 AM UTC 24 5929037944 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.260461090 Oct 10 02:14:46 AM UTC 24 Oct 10 02:19:18 AM UTC 24 2516370176 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2950313513 Oct 10 02:01:52 AM UTC 24 Oct 10 02:19:18 AM UTC 24 10756774866 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1480540105 Oct 10 02:10:10 AM UTC 24 Oct 10 02:19:31 AM UTC 24 5922722760 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.1134056236 Oct 10 02:16:09 AM UTC 24 Oct 10 02:19:34 AM UTC 24 2376563446 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.3977695081 Oct 10 02:15:10 AM UTC 24 Oct 10 02:20:27 AM UTC 24 2905743824 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2210995281 Oct 10 02:16:10 AM UTC 24 Oct 10 02:20:58 AM UTC 24 2766862950 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2741167024 Oct 10 02:16:03 AM UTC 24 Oct 10 02:21:03 AM UTC 24 2850095525 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.421335324 Oct 10 02:03:40 AM UTC 24 Oct 10 02:21:33 AM UTC 24 5322794248 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.3659671537 Oct 10 02:09:57 AM UTC 24 Oct 10 02:21:57 AM UTC 24 3484719800 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.535720006 Oct 10 01:58:20 AM UTC 24 Oct 10 02:23:11 AM UTC 24 15429861058 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4110965674 Oct 10 01:57:28 AM UTC 24 Oct 10 02:23:42 AM UTC 24 12601451427 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.1897091210 Oct 10 02:18:10 AM UTC 24 Oct 10 02:23:44 AM UTC 24 2743339320 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4181930633 Oct 10 02:16:38 AM UTC 24 Oct 10 02:25:21 AM UTC 24 4596544504 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.610775461 Oct 10 02:11:50 AM UTC 24 Oct 10 02:25:32 AM UTC 24 5366982403 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.292433476 Oct 10 01:57:25 AM UTC 24 Oct 10 02:25:49 AM UTC 24 11962379220 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3737897695 Oct 10 02:20:23 AM UTC 24 Oct 10 02:25:49 AM UTC 24 2919870600 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2345511395 Oct 10 02:16:09 AM UTC 24 Oct 10 02:25:50 AM UTC 24 9591417123 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.1204481092 Oct 10 02:17:15 AM UTC 24 Oct 10 02:26:28 AM UTC 24 7420332941 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4163753470 Oct 10 02:18:11 AM UTC 24 Oct 10 02:26:34 AM UTC 24 5489151168 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3208265549 Oct 10 02:18:11 AM UTC 24 Oct 10 02:27:15 AM UTC 24 5032889834 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3025151314 Oct 10 02:21:03 AM UTC 24 Oct 10 02:27:16 AM UTC 24 3570193016 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2932916040 Oct 10 02:20:24 AM UTC 24 Oct 10 02:27:46 AM UTC 24 4546281696 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2368805069 Oct 10 02:20:20 AM UTC 24 Oct 10 02:27:46 AM UTC 24 4216373864 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2810008940 Oct 10 02:21:44 AM UTC 24 Oct 10 02:28:00 AM UTC 24 5021508636 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3183794226 Oct 10 02:19:21 AM UTC 24 Oct 10 02:28:09 AM UTC 24 4369462736 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.3502388654 Oct 10 01:50:42 AM UTC 24 Oct 10 02:28:28 AM UTC 24 25319277210 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3849369689 Oct 10 02:17:24 AM UTC 24 Oct 10 02:29:06 AM UTC 24 4802429038 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.1508246867 Oct 10 02:11:50 AM UTC 24 Oct 10 02:30:13 AM UTC 24 5427460920 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3870200904 Oct 10 02:17:28 AM UTC 24 Oct 10 02:30:39 AM UTC 24 7109937080 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3934723241 Oct 10 02:09:18 AM UTC 24 Oct 10 02:30:51 AM UTC 24 10957438964 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1379988778 Oct 10 02:17:31 AM UTC 24 Oct 10 02:30:55 AM UTC 24 8956593724 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3859743762 Oct 10 02:13:51 AM UTC 24 Oct 10 02:31:32 AM UTC 24 6370003272 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2503195342 Oct 10 02:26:45 AM UTC 24 Oct 10 02:31:46 AM UTC 24 2760420204 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3722340291 Oct 10 02:22:08 AM UTC 24 Oct 10 02:31:56 AM UTC 24 4192485370 ps
T669 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1771060082 Oct 10 02:07:36 AM UTC 24 Oct 10 02:32:39 AM UTC 24 7908952152 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2789325209 Oct 10 02:22:32 AM UTC 24 Oct 10 02:32:58 AM UTC 24 4725040600 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.587245404 Oct 10 02:19:35 AM UTC 24 Oct 10 02:33:41 AM UTC 24 5092010168 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.2680851698 Oct 10 02:26:09 AM UTC 24 Oct 10 02:33:50 AM UTC 24 3571294933 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4240357464 Oct 10 02:21:44 AM UTC 24 Oct 10 02:33:53 AM UTC 24 9274726159 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1708366613 Oct 10 01:56:41 AM UTC 24 Oct 10 02:34:50 AM UTC 24 31355785600 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1748201265 Oct 10 02:29:09 AM UTC 24 Oct 10 02:35:08 AM UTC 24 3591414530 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4262001754 Oct 10 02:26:46 AM UTC 24 Oct 10 02:35:21 AM UTC 24 3461258308 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.524951240 Oct 10 02:24:28 AM UTC 24 Oct 10 02:35:31 AM UTC 24 4078173994 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1518813390 Oct 10 02:23:47 AM UTC 24 Oct 10 02:35:37 AM UTC 24 4388227604 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.199675243 Oct 10 02:33:08 AM UTC 24 Oct 10 02:35:58 AM UTC 24 2988426110 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.1392094576 Oct 10 02:32:01 AM UTC 24 Oct 10 02:35:59 AM UTC 24 2814954480 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3446029116 Oct 10 02:09:19 AM UTC 24 Oct 10 02:36:07 AM UTC 24 7487613956 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1743548018 Oct 10 02:09:14 AM UTC 24 Oct 10 02:36:16 AM UTC 24 6654248264 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2576254047 Oct 10 02:32:15 AM UTC 24 Oct 10 02:36:28 AM UTC 24 2701958791 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2991114080 Oct 10 01:45:26 AM UTC 24 Oct 10 02:36:34 AM UTC 24 13241313084 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1451684926 Oct 10 02:26:06 AM UTC 24 Oct 10 02:36:36 AM UTC 24 4622217182 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2055983235 Oct 10 02:00:48 AM UTC 24 Oct 10 02:36:37 AM UTC 24 25299360472 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.986089782 Oct 10 02:24:27 AM UTC 24 Oct 10 02:36:44 AM UTC 24 5049304792 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.259895308 Oct 10 02:09:35 AM UTC 24 Oct 10 02:37:12 AM UTC 24 8008279648 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3499104006 Oct 10 02:28:51 AM UTC 24 Oct 10 02:37:19 AM UTC 24 6872514578 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.556691759 Oct 10 02:14:50 AM UTC 24 Oct 10 02:37:37 AM UTC 24 7301748740 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.636735758 Oct 10 02:29:40 AM UTC 24 Oct 10 02:37:41 AM UTC 24 5386698136 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.559297190 Oct 10 02:34:38 AM UTC 24 Oct 10 02:37:43 AM UTC 24 2332210388 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.2798023119 Oct 10 02:28:02 AM UTC 24 Oct 10 02:38:33 AM UTC 24 5422867008 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.914880037 Oct 10 02:10:50 AM UTC 24 Oct 10 02:38:35 AM UTC 24 7220872828 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3378090671 Oct 10 02:33:34 AM UTC 24 Oct 10 02:38:40 AM UTC 24 2954518896 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2161702129 Oct 10 02:30:50 AM UTC 24 Oct 10 02:38:42 AM UTC 24 4259104060 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1713991631 Oct 10 02:29:12 AM UTC 24 Oct 10 02:38:48 AM UTC 24 6665730366 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2094286449 Oct 10 02:26:46 AM UTC 24 Oct 10 02:39:05 AM UTC 24 5191359756 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3879613064 Oct 10 02:34:38 AM UTC 24 Oct 10 02:39:08 AM UTC 24 3219850787 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.1289773501 Oct 10 01:45:22 AM UTC 24 Oct 10 02:39:13 AM UTC 24 12342881570 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3180008190 Oct 10 02:09:59 AM UTC 24 Oct 10 02:39:18 AM UTC 24 7665326358 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1587941861 Oct 10 02:36:04 AM UTC 24 Oct 10 02:39:26 AM UTC 24 2703637781 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2168310784 Oct 10 02:19:33 AM UTC 24 Oct 10 02:39:36 AM UTC 24 6497456216 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2230894896 Oct 10 02:13:02 AM UTC 24 Oct 10 02:40:12 AM UTC 24 6747640406 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1718067872 Oct 10 02:31:40 AM UTC 24 Oct 10 02:40:15 AM UTC 24 6744860168 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.2359138298 Oct 10 02:34:39 AM UTC 24 Oct 10 02:40:22 AM UTC 24 2627536493 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2417225561 Oct 10 02:31:25 AM UTC 24 Oct 10 02:40:33 AM UTC 24 5088070440 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2089496395 Oct 10 02:31:40 AM UTC 24 Oct 10 02:40:34 AM UTC 24 5444668582 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.3542467403 Oct 10 02:35:41 AM UTC 24 Oct 10 02:41:32 AM UTC 24 2714426120 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.4115587973 Oct 10 02:32:26 AM UTC 24 Oct 10 02:41:34 AM UTC 24 6072143382 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1234789305 Oct 10 02:38:10 AM UTC 24 Oct 10 02:41:39 AM UTC 24 2518174477 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.83697129 Oct 10 02:20:19 AM UTC 24 Oct 10 02:41:44 AM UTC 24 12410955712 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1018493031 Oct 10 02:38:11 AM UTC 24 Oct 10 02:42:26 AM UTC 24 3490939243 ps
T692 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.2089998402 Oct 10 02:28:01 AM UTC 24 Oct 10 02:42:29 AM UTC 24 7184033112 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.457865414 Oct 10 02:39:23 AM UTC 24 Oct 10 02:43:11 AM UTC 24 3710548552 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.3714212290 Oct 10 02:38:14 AM UTC 24 Oct 10 02:43:55 AM UTC 24 4347063460 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3368346858 Oct 10 02:13:51 AM UTC 24 Oct 10 02:44:04 AM UTC 24 10559757221 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3563373002 Oct 10 02:26:57 AM UTC 24 Oct 10 02:45:04 AM UTC 24 13333695800 ps
T677 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.4200767854 Oct 10 02:35:28 AM UTC 24 Oct 10 02:45:25 AM UTC 24 5583940510 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1920805612 Oct 10 01:58:16 AM UTC 24 Oct 10 02:46:03 AM UTC 24 27493139305 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2853374121 Oct 10 02:36:17 AM UTC 24 Oct 10 02:46:14 AM UTC 24 4804227348 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.4189452592 Oct 10 02:42:15 AM UTC 24 Oct 10 02:46:19 AM UTC 24 3015125416 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.2568134383 Oct 10 02:38:34 AM UTC 24 Oct 10 02:49:18 AM UTC 24 4609830656 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2455400219 Oct 10 02:26:50 AM UTC 24 Oct 10 02:49:24 AM UTC 24 12955118180 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.843347104 Oct 10 02:36:20 AM UTC 24 Oct 10 02:51:24 AM UTC 24 7593304674 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1587332738 Oct 10 02:41:53 AM UTC 24 Oct 10 02:51:28 AM UTC 24 5007825940 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2260930423 Oct 10 02:40:14 AM UTC 24 Oct 10 02:57:54 AM UTC 24 5995057992 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.4287763142 Oct 10 02:13:50 AM UTC 24 Oct 10 02:58:48 AM UTC 24 12799811106 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.128196796 Oct 10 02:29:09 AM UTC 24 Oct 10 02:58:50 AM UTC 24 20410428600 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3394578108 Oct 10 02:14:49 AM UTC 24 Oct 10 03:00:06 AM UTC 24 13117125784 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1535208431 Oct 10 02:19:20 AM UTC 24 Oct 10 03:01:22 AM UTC 24 27866556325 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2142558478 Oct 10 02:29:07 AM UTC 24 Oct 10 03:04:38 AM UTC 24 24836404104 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.957335725 Oct 10 02:01:12 AM UTC 24 Oct 10 03:05:12 AM UTC 24 20202582200 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.2599017475 Oct 10 02:42:13 AM UTC 24 Oct 10 03:09:02 AM UTC 24 6284618432 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.919569235 Oct 10 02:10:14 AM UTC 24 Oct 10 03:10:08 AM UTC 24 12136457158 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.4114732841 Oct 10 01:44:42 AM UTC 24 Oct 10 03:13:10 AM UTC 24 18340343896 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1124771225 Oct 10 02:37:47 AM UTC 24 Oct 10 03:14:58 AM UTC 24 13137356100 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1913843342 Oct 10 02:38:34 AM UTC 24 Oct 10 03:20:40 AM UTC 24 20601848393 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.3020518949 Oct 10 02:14:47 AM UTC 24 Oct 10 03:23:17 AM UTC 24 14663626620 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3041725218 Oct 10 02:03:19 AM UTC 24 Oct 10 03:23:29 AM UTC 24 18660917555 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3157354272 Oct 10 02:03:15 AM UTC 24 Oct 10 03:26:51 AM UTC 24 17596601984 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2155783782 Oct 10 01:50:42 AM UTC 24 Oct 10 03:28:00 AM UTC 24 43795131530 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.2197271177 Oct 10 03:27:27 AM UTC 24 Oct 10 03:29:38 AM UTC 24 2963513969 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.1798352245 Oct 10 03:28:36 AM UTC 24 Oct 10 03:34:17 AM UTC 24 5276809502 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.295667482 Oct 10 02:43:53 AM UTC 24 Oct 10 03:37:46 AM UTC 24 10933173020 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.855501349 Oct 10 03:05:45 AM UTC 24 Oct 10 03:40:00 AM UTC 24 10907920882 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.897156180 Oct 10 02:47:17 AM UTC 24 Oct 10 03:40:18 AM UTC 24 11586296960 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2387845140 Oct 10 02:42:22 AM UTC 24 Oct 10 03:40:55 AM UTC 24 11574686764 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2068193312 Oct 10 03:34:54 AM UTC 24 Oct 10 03:41:15 AM UTC 24 3249535930 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.431911016 Oct 10 03:01:54 AM UTC 24 Oct 10 03:41:58 AM UTC 24 10581140635 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3970623802 Oct 10 02:48:40 AM UTC 24 Oct 10 03:42:37 AM UTC 24 11385636428 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.387670995 Oct 10 03:05:11 AM UTC 24 Oct 10 03:42:51 AM UTC 24 12535953178 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3173144495 Oct 10 01:53:55 AM UTC 24 Oct 10 03:44:01 AM UTC 24 26456162502 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.624480999 Oct 10 03:38:22 AM UTC 24 Oct 10 03:44:16 AM UTC 24 2843301080 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.2878103742 Oct 10 03:40:54 AM UTC 24 Oct 10 03:45:28 AM UTC 24 3024273960 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.4546582 Oct 10 03:41:33 AM UTC 24 Oct 10 03:45:31 AM UTC 24 2640344798 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.359463969 Oct 10 03:40:36 AM UTC 24 Oct 10 03:46:20 AM UTC 24 3031100082 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.2509410371 Oct 10 03:42:33 AM UTC 24 Oct 10 03:48:21 AM UTC 24 3135568064 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.2141313338 Oct 10 01:56:51 AM UTC 24 Oct 10 03:48:25 AM UTC 24 47715956936 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.2271188521 Oct 10 03:43:14 AM UTC 24 Oct 10 03:49:41 AM UTC 24 3021346088 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.2192632277 Oct 10 03:46:56 AM UTC 24 Oct 10 03:50:32 AM UTC 24 3313313040 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.558644368 Oct 10 03:44:52 AM UTC 24 Oct 10 03:50:33 AM UTC 24 3538470300 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2994679243 Oct 10 02:52:19 AM UTC 24 Oct 10 03:50:57 AM UTC 24 11443480234 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.579923109 Oct 10 03:43:28 AM UTC 24 Oct 10 03:51:49 AM UTC 24 3483752850 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2400793452 Oct 10 03:41:50 AM UTC 24 Oct 10 03:51:50 AM UTC 24 3632111690 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.4256747425 Oct 10 03:46:15 AM UTC 24 Oct 10 03:52:02 AM UTC 24 4809913954 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1212746244 Oct 10 03:46:16 AM UTC 24 Oct 10 03:53:17 AM UTC 24 6186544900 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2857854413 Oct 10 03:51:27 AM UTC 24 Oct 10 03:53:47 AM UTC 24 2024181608 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.4233380259 Oct 10 03:49:07 AM UTC 24 Oct 10 03:53:50 AM UTC 24 2680762520 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.1116160285 Oct 10 03:50:18 AM UTC 24 Oct 10 03:54:14 AM UTC 24 3254960256 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.616095669 Oct 10 03:49:07 AM UTC 24 Oct 10 03:54:24 AM UTC 24 2438377562 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.4191650497 Oct 10 02:41:36 AM UTC 24 Oct 10 03:54:26 AM UTC 24 14055152344 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2378062535 Oct 10 02:41:13 AM UTC 24 Oct 10 03:55:21 AM UTC 24 15161145056 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1273026376 Oct 10 02:52:23 AM UTC 24 Oct 10 03:55:25 AM UTC 24 14274140526 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.771198610 Oct 10 03:51:18 AM UTC 24 Oct 10 03:55:41 AM UTC 24 3515797286 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.652127133 Oct 10 03:51:17 AM UTC 24 Oct 10 03:56:20 AM UTC 24 2514933436 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2806894862 Oct 10 02:38:11 AM UTC 24 Oct 10 03:57:02 AM UTC 24 24901296736 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.192017002 Oct 10 03:52:45 AM UTC 24 Oct 10 03:57:34 AM UTC 24 3250350066 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.3235153940 Oct 10 02:42:31 AM UTC 24 Oct 10 03:57:50 AM UTC 24 31476218760 ps
T676 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.2593264089 Oct 10 03:10:44 AM UTC 24 Oct 10 03:57:59 AM UTC 24 32395670531 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3318412133 Oct 10 03:52:48 AM UTC 24 Oct 10 03:58:19 AM UTC 24 2667682920 ps
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