Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.clkmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146080	1			T97	10		T98	9		T102	3
values[2]	10109	1			T184	3		T458	4		T479	2
values[3]	3579	1			T802	14		T530	1		T484	5
values[4]	2124	1			T802	6		T484	15		T593	8
values[5]	1420	1			T802	5		T484	5		T493	2
values[6]	980	1			T802	9		T484	7		T493	6
values[7]	776	1			T802	6		T484	7		T493	5
values[8]	579	1			T802	1		T484	6		T493	5
values[9]	580	1			T802	7		T484	9		T493	11
values[10]	502	1			T802	5		T484	9		T493	7
values[11]	444	1			T802	4		T484	6		T493	2
values[12]	424	1			T802	4		T484	4		T493	1
values[13]	420	1			T802	4		T484	7		T493	1
values[14]	313	1			T802	1		T484	6		T493	3
values[15]	341	1			T802	1		T484	5		T493	5
values[16]	333	1			T484	8		T493	3		T798	6
values[17]	356	1			T484	6		T493	3		T798	3
values[18]	305	1			T484	11		T493	1		T798	20
values[19]	311	1			T484	5		T493	1		T798	6
values[20]	285	1			T484	6		T493	2		T798	5
values[21]	332	1			T484	3		T493	6		T798	6
values[22]	355	1			T484	6		T493	2		T798	7
values[23]	337	1			T484	13		T493	2		T798	10
values[24]	335	1			T484	17		T493	2		T798	13
values[25]	318	1			T484	7		T493	1		T798	12
values[26]	292	1			T484	12		T493	2		T798	7
values[27]	274	1			T484	4		T493	4		T798	3
values[28]	269	1			T484	3		T493	6		T798	5
values[29]	345	1			T484	6		T493	3		T798	6
values[30]	282	1			T484	9		T493	1		T798	6
values[31]	289	1			T484	5		T493	2		T798	2
values[32]	291	1			T484	7		T493	1		T798	18
values[33]	305	1			T484	8		T493	3		T798	8
values[34]	301	1			T484	9		T493	4		T798	7
values[35]	290	1			T484	4		T493	2		T798	5
values[36]	272	1			T484	11		T493	1		T798	10
values[37]	319	1			T484	16		T493	6		T798	7
values[38]	362	1			T484	6		T493	8		T798	11
values[39]	312	1			T484	17		T493	9		T798	13
values[40]	298	1			T484	18		T493	3		T798	16
values[41]	258	1			T484	6		T493	3		T798	6
values[42]	273	1			T484	3		T493	2		T798	3
values[43]	295	1			T484	5		T493	1		T798	3
values[44]	302	1			T484	4		T493	5		T798	26
values[45]	269	1			T484	2		T493	3		T798	5
values[46]	248	1			T484	7		T493	1		T798	2
values[47]	246	1			T484	3		T798	8		T486	1
values[48]	289	1			T484	6		T798	14		T486	1
values[49]	284	1			T484	5		T798	5		T486	1
values[50]	213	1			T484	6		T798	5		T486	1
values[51]	271	1			T484	16		T798	10		T486	1
values[52]	232	1			T484	14		T798	3		T486	1
values[53]	237	1			T484	4		T798	4		T486	1
values[54]	254	1			T484	11		T798	12		T486	1
values[55]	216	1			T484	3		T798	4		T486	1
values[56]	216	1			T484	4		T798	4		T486	1
values[57]	246	1			T484	9		T798	15		T486	1
values[58]	222	1			T484	5		T798	7		T486	1
values[59]	195	1			T484	2		T798	4		T486	1
values[60]	194	1			T484	7		T798	12		T486	1
values[61]	184	1			T484	8		T798	10		T486	1
values[62]	165	1			T484	4		T798	4		T486	1
values[63]	216	1			T484	14		T798	6		T486	1
values[64]	172	1			T484	3		T798	8		T486	1
values[65]	161	1			T484	9		T798	8		T486	1
values[66]	166	1			T484	8		T798	3		T486	1
values[67]	125	1			T484	11		T798	7		T486	1
values[68]	154	1			T484	26		T798	4		T486	1
values[69]	136	1			T484	4		T798	10		T486	1
values[70]	145	1			T484	6		T798	7		T486	1
values[71]	116	1			T484	2		T798	5		T486	1
values[72]	105	1			T484	12		T486	1		T803	6
values[73]	90	1			T484	5		T486	1		T803	7
values[74]	67	1			T486	1		T804	1		T516	1
values[75]	70	1			T486	1		T804	1		T516	1
values[76]	89	1			T486	1		T804	1		T516	1
values[77]	79	1			T486	1		T804	1		T516	1
values[78]	85	1			T486	1		T804	1		T516	1
values[79]	65	1			T486	1		T804	1		T516	1
values[80]	68	1			T486	1		T804	1		T516	1
values[81]	59	1			T486	1		T804	1		T516	1
values[82]	56	1			T486	1		T804	5		T516	1
values[83]	65	1			T486	1		T804	1		T516	1
values[84]	59	1			T486	1		T804	7		T516	1
values[85]	91	1			T486	1		T804	7		T516	1
values[86]	67	1			T486	1		T804	2		T516	1
values[87]	66	1			T486	1		T804	3		T516	1
values[88]	76	1			T486	1		T804	4		T516	1
values[89]	63	1			T486	1		T804	2		T516	1
values[90]	70	1			T486	1		T804	2		T516	2
values[91]	58	1			T486	1		T804	1		T516	1
values[92]	89	1			T486	1		T804	9		T516	1
values[93]	83	1			T486	1		T804	9		T516	1
values[94]	86	1			T486	1		T804	1		T516	1
values[95]	88	1			T486	1		T804	1		T516	1
values[96]	63	1			T486	1		T804	1		T516	1
values[97]	58	1			T486	1		T804	1		T516	1
values[98]	78	1			T486	1		T804	3		T516	1
values[99]	56	1			T486	1		T804	1		T516	1
values[100]	67	1			T486	1		T804	2		T516	1
values[101]	61	1			T486	2		T804	1		T516	1
values[102]	60	1			T486	1		T804	3		T516	1
values[103]	76	1			T486	1		T804	1		T516	1
values[104]	70	1			T486	2		T804	2		T516	1
values[105]	53	1			T486	1		T804	2		T516	1
values[106]	48	1			T486	1		T804	3		T516	1
values[107]	68	1			T486	2		T804	7		T516	1
values[108]	57	1			T486	2		T804	3		T516	1
values[109]	54	1			T486	2		T804	2		T516	1
values[110]	65	1			T486	2		T804	5		T516	1
values[111]	64	1			T486	2		T804	2		T516	1
values[112]	57	1			T486	1		T804	2		T516	1
values[113]	67	1			T486	6		T804	4		T516	1
values[114]	59	1			T486	1		T804	3		T516	1
values[115]	58	1			T486	1		T804	1		T516	1
values[116]	58	1			T486	1		T804	1		T516	1
values[117]	80	1			T486	3		T804	1		T516	1
values[118]	49	1			T486	1		T804	1		T516	2
values[119]	55	1			T486	2		T804	2		T516	1
values[120]	68	1			T486	2		T804	5		T516	1
values[121]	62	1			T486	1		T804	2		T516	1
values[122]	63	1			T486	2		T804	1		T516	1
values[123]	66	1			T486	3		T804	1		T516	2
values[124]	57	1			T486	2		T804	1		T516	1
values[125]	61	1			T486	1		T804	3		T516	2
values[126]	119	1			T486	6		T804	4		T516	3
values[127]	856	1			T486	31		T804	37		T516	32
values[128]	7481	1			T486	357		T804	252		T516	364