Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	519	1			T564	1		T575	1		T810	4
all_values[1]	504	1			T581	1		T567	1		T821	1
all_values[2]	513	1			T575	3		T810	1		T802	5
all_values[3]	503	1			T581	1		T575	2		T567	1
all_values[4]	480	1			T564	1		T575	1		T567	1
all_values[5]	472	1			T575	2		T810	3		T659	1
all_values[6]	470	1			T568	1		T821	1		T810	4
all_values[7]	519	1			T693	1		T575	3		T810	3
all_values[8]	522	1			T693	1		T581	1		T575	2
all_values[9]	507	1			T581	1		T810	3		T497	4
all_values[10]	484	1			T581	1		T575	1		T565	1
all_values[11]	525	1			T693	1		T810	1		T837	2
all_values[12]	461	1			T564	1		T565	1		T567	3
all_values[13]	520	1			T693	1		T568	1		T567	1
all_values[14]	525	1			T575	2		T659	2		T802	8
all_values[15]	540	1			T693	1		T581	2		T575	1
all_values[16]	521	1			T99	1		T575	2		T567	1
all_values[17]	495	1			T693	1		T564	1		T575	2
all_values[18]	533	1			T575	2		T567	1		T810	3
all_values[19]	488	1			T575	1		T567	1		T810	1
all_values[20]	515	1			T564	1		T575	1		T568	1
all_values[21]	499	1			T575	2		T567	2		T810	7
all_values[22]	486	1			T564	1		T575	3		T567	1
all_values[23]	508	1			T564	1		T575	4		T565	1
all_values[24]	522	1			T575	2		T565	1		T810	3
all_values[25]	500	1			T810	6		T802	2		T660	7
all_values[26]	466	1			T810	1		T802	5		T660	2
all_values[27]	531	1			T693	2		T575	1		T810	3
all_values[28]	523	1			T564	1		T575	4		T810	3
all_values[29]	507	1			T564	2		T575	1		T810	4
all_values[30]	491	1			T564	1		T575	4		T810	6
all_values[31]	455	1			T564	1		T575	1		T567	1
all_values[32]	544	1			T564	1		T810	4		T802	1
all_values[33]	513	1			T575	2		T565	2		T810	4
all_values[34]	530	1			T575	2		T810	4		T497	2
all_values[35]	546	1			T575	1		T567	1		T821	1
all_values[36]	480	1			T581	1		T575	2		T810	4
all_values[37]	513	1			T575	3		T810	3		T802	3
all_values[38]	494	1			T575	2		T567	1		T810	2
all_values[39]	516	1			T575	1		T567	1		T810	4
all_values[40]	518	1			T693	1		T575	2		T568	1
all_values[41]	508	1			T810	1		T497	1		T659	1
all_values[42]	569	1			T575	3		T810	2		T497	1
all_values[43]	464	1			T575	2		T810	5		T497	1
all_values[44]	561	1			T565	1		T568	1		T810	3
all_values[45]	495	1			T810	4		T659	1		T802	4
all_values[46]	561	1			T99	1		T693	1		T581	1
all_values[47]	512	1			T564	2		T575	1		T810	2
all_values[48]	492	1			T693	1		T564	1		T575	1
all_values[49]	509	1			T575	2		T810	2		T659	1