Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3411	1			T480	2		T475	2		T581	3
all_values[1]	3580	1			T480	1		T475	1		T581	2
all_values[2]	3545	1			T480	3		T475	5		T581	2
all_values[3]	3689	1			T480	1		T475	4		T581	2
all_values[4]	3590	1			T480	1		T475	1		T581	1
all_values[5]	3597	1			T480	2		T475	1		T581	2
all_values[6]	3675	1			T480	2		T475	1		T581	4
all_values[7]	3678	1			T480	1		T475	3		T581	1
all_values[8]	3748	1			T480	1		T475	3		T581	2
all_values[9]	3516	1			T480	4		T581	7		T564	1
all_values[10]	3607	1			T480	2		T564	1		T575	15
all_values[11]	3575	1			T480	2		T581	5		T564	3
all_values[12]	3655	1			T475	1		T581	1		T575	15
all_values[13]	3705	1			T480	1		T581	3		T572	1
all_values[14]	3556	1			T475	1		T581	3		T564	1
all_values[15]	3579	1			T480	1		T475	2		T581	2
all_values[16]	3564	1			T475	1		T581	3		T572	1
all_values[17]	3528	1			T475	2		T581	1		T572	2
all_values[18]	3555	1			T480	3		T475	1		T581	2
all_values[19]	3695	1			T480	1		T475	2		T581	2
all_values[20]	3631	1			T480	3		T475	1		T581	2
all_values[21]	3690	1			T480	2		T581	5		T564	1
all_values[22]	3583	1			T480	1		T475	2		T581	2
all_values[23]	3561	1			T581	1		T572	1		T564	1
all_values[24]	3565	1			T480	2		T475	1		T581	2
all_values[25]	3611	1			T475	2		T581	2		T564	1
all_values[26]	3584	1			T581	4		T572	1		T575	10
all_values[27]	3617	1			T480	2		T475	3		T572	1
all_values[28]	3510	1			T480	1		T564	1		T575	18
all_values[29]	3573	1			T480	1		T581	4		T564	2
all_values[30]	3598	1			T475	1		T581	3		T564	1
all_values[31]	3514	1			T480	1		T475	1		T581	3
all_values[32]	3541	1			T480	2		T475	2		T581	2
all_values[33]	3548	1			T480	2		T581	6		T575	10
all_values[34]	3656	1			T480	4		T475	4		T581	2
all_values[35]	3609	1			T480	1		T475	1		T581	3
all_values[36]	3569	1			T480	2		T581	6		T572	2
all_values[37]	3588	1			T480	2		T581	1		T564	4
all_values[38]	3658	1			T480	1		T475	2		T581	5
all_values[39]	3678	1			T480	1		T475	1		T581	2
all_values[40]	3608	1			T480	4		T475	1		T581	5
all_values[41]	3661	1			T480	1		T475	2		T581	2
all_values[42]	3617	1			T480	1		T475	1		T581	4
all_values[43]	3576	1			T480	6		T475	3		T581	3
all_values[44]	3660	1			T480	1		T581	1		T564	2
all_values[45]	3707	1			T475	1		T581	1		T564	2
all_values[46]	3606	1			T480	2		T475	3		T581	2
all_values[47]	3617	1			T480	1		T475	1		T581	2
all_values[48]	3542	1			T480	1		T581	3		T564	1
all_values[49]	3613	1			T480	2		T475	4		T572	1
all_values[50]	3604	1			T480	3		T475	1		T581	1
all_values[51]	3691	1			T480	2		T475	2		T581	1
all_values[52]	3663	1			T480	1		T475	1		T564	2
all_values[53]	3575	1			T475	2		T572	1		T564	1
all_values[54]	3598	1			T480	1		T475	1		T581	4
all_values[55]	3611	1			T480	1		T581	3		T564	2
all_values[56]	3646	1			T475	2		T581	4		T575	12
all_values[57]	3654	1			T480	1		T475	2		T581	1
all_values[58]	3584	1			T480	2		T475	1		T581	3
all_values[59]	3417	1			T475	3		T581	4		T564	3
all_values[60]	3737	1			T480	1		T475	2		T581	3
all_values[61]	3599	1			T480	3		T581	2		T572	1
all_values[62]	3526	1			T480	1		T475	1		T564	3
all_values[63]	3623	1			T480	2		T581	4		T564	1