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759 // define mixed connection to port
760 1/1 assign edn0_edn_req[2] = ast_edn_req_i;
Tests: T1 T2 T3
761 1/1 assign ast_edn_rsp_o = edn0_edn_rsp[2];
Tests: T1 T2 T4
762 1/1 assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en;
Tests: T1 T2 T3
763 0/1 ==> assign ast_obs_ctrl = obs_ctrl_i;
764 0/1 ==> assign ast_ram_1p_cfg = ram_1p_cfg_i;
765 0/1 ==> assign ast_spi_ram_2p_cfg = spi_ram_2p_cfg_i;
766 0/1 ==> assign ast_usb_ram_1p_cfg = usb_ram_1p_cfg_i;
767 0/1 ==> assign ast_rom_cfg = rom_cfg_i;
768
769 // define partial inter-module tie-off
770 otp_ctrl_pkg::sram_otp_key_rsp_t unused_otp_ctrl_sram_otp_key_rsp3;
771 edn_pkg::edn_rsp_t unused_edn1_edn_rsp1;
772 edn_pkg::edn_rsp_t unused_edn1_edn_rsp2;
773 edn_pkg::edn_rsp_t unused_edn1_edn_rsp3;
774 edn_pkg::edn_rsp_t unused_edn1_edn_rsp4;
775 edn_pkg::edn_rsp_t unused_edn1_edn_rsp5;
776 edn_pkg::edn_rsp_t unused_edn1_edn_rsp6;
777 edn_pkg::edn_rsp_t unused_edn1_edn_rsp7;
778
779 // assign partial inter-module tie-off
780 1/1 assign unused_otp_ctrl_sram_otp_key_rsp3 = otp_ctrl_sram_otp_key_rsp[3];
Tests: T1 T2 T4
781 0/1 ==> assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1];
782 0/1 ==> assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2];
783 0/1 ==> assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3];
784 0/1 ==> assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4];
785 0/1 ==> assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5];
786 0/1 ==> assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6];
787 0/1 ==> assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7];
788 assign otp_ctrl_sram_otp_key_req[3] = '0;
789 assign edn1_edn_req[1] = '0;
790 assign edn1_edn_req[2] = '0;
791 assign edn1_edn_req[3] = '0;
792 assign edn1_edn_req[4] = '0;
793 assign edn1_edn_req[5] = '0;
794 assign edn1_edn_req[6] = '0;
795 assign edn1_edn_req[7] = '0;
796
797
798 // OTP HW_CFG* Broadcast signals.
799 // TODO(#6713): The actual struct breakout and mapping currently needs to
800 // be performed by hand.
801 1/1 assign csrng_otp_en_csrng_sw_app_read =
Tests: T1 T2 T3
802 otp_ctrl_otp_broadcast.hw_cfg1_data.en_csrng_sw_app_read;
803 1/1 assign sram_ctrl_main_otp_en_sram_ifetch =
Tests: T1 T2 T3
804 otp_ctrl_otp_broadcast.hw_cfg1_data.en_sram_ifetch;
805 1/1 assign rv_dm_otp_dis_rv_dm_late_debug =
Tests: T1 T2 T3
806 otp_ctrl_otp_broadcast.hw_cfg1_data.dis_rv_dm_late_debug;
807 1/1 assign lc_ctrl_otp_device_id =
Tests: T1 T2 T3
808 otp_ctrl_otp_broadcast.hw_cfg0_data.device_id;
809 1/1 assign lc_ctrl_otp_manuf_state =
Tests: T1 T2 T3
810 otp_ctrl_otp_broadcast.hw_cfg0_data.manuf_state;
811 1/1 assign keymgr_otp_device_id =
Tests: T1 T2 T3
812 otp_ctrl_otp_broadcast.hw_cfg0_data.device_id;
813
814 logic unused_otp_broadcast_bits;
815 1/1 assign unused_otp_broadcast_bits = ^{
Tests: T1 T2 T3
816 otp_ctrl_otp_broadcast.valid,
817 otp_ctrl_otp_broadcast.hw_cfg0_data.hw_cfg0_digest,
818 otp_ctrl_otp_broadcast.hw_cfg1_data.hw_cfg1_digest,
819 otp_ctrl_otp_broadcast.hw_cfg1_data.unallocated
820 };
821
822 // See #7978 This below is a hack.
823 // This is because ast is a comportable-like module that sits outside
824 // of top_earlgrey's boundary.
825 1/1 assign clks_ast_o = clkmgr_aon_clocks;
Tests: T1 T2 T3
826 1/1 assign rsts_ast_o = rstmgr_aon_resets;
Tests: T1 T2 T3
827
828 // ibex specific assignments
829 // TODO: This should be further automated in the future.
830 1/1 assign rv_core_ibex_irq_timer = intr_rv_timer_timer_expired_hart0_timer0;
Tests: T168 T169 T170
831 assign rv_core_ibex_hart_id = '0;
832
833 assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM_CTRL__ROM;
834
835
836 // Struct breakout module tool-inserted DFT TAP signals
837 pinmux_jtag_breakout u_dft_tap_breakout (
838 .req_i (pinmux_aon_dft_jtag_req),
839 .rsp_o (pinmux_aon_dft_jtag_rsp),
840 .tck_o (),
841 .trst_no (),
842 .tms_o (),
843 .tdi_o (),
844 .tdo_i (1'b0),
845 .tdo_oe_i (1'b0)
846 );
847
848 // Wire up alert handler LPGs
849 prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_cg_en;
850 prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_rst_en;
851
852
853 // peri_lc_io_div4_0
854 1/1 assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
855 1/1 assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
856 // peri_spi_device_0
857 1/1 assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
858 1/1 assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
859 // peri_i2c0_0
860 1/1 assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
861 1/1 assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
862 // peri_i2c1_0
863 1/1 assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
864 1/1 assign lpg_rst_en[3] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
865 // peri_i2c2_0
866 1/1 assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
867 1/1 assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
868 // timers_lc_io_div4_0
869 1/1 assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers;
Tests: T1 T2 T3
870 1/1 assign lpg_rst_en[5] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
871 // secure_lc_io_div4_0
872 1/1 assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_secure;
Tests: T1 T2 T3
873 1/1 assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
874 // peri_spi_host0_0
875 1/1 assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_peri;
Tests: T1 T2 T3
876 1/1 assign lpg_rst_en[7] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
877 // peri_spi_host1_0
878 1/1 assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div2_peri;
Tests: T1 T2 T3
879 1/1 assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
880 // peri_usb_0
881 1/1 assign lpg_cg_en[9] = clkmgr_aon_cg_en.usb_peri;
Tests: T1 T2 T3
882 1/1 assign lpg_rst_en[9] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
883 // powerup_por_io_div4_Aon
884 0/1 ==> assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup;
885 1/1 assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
886 // powerup_lc_io_div4_Aon
887 0/1 ==> assign lpg_cg_en[11] = clkmgr_aon_cg_en.io_div4_powerup;
888 1/1 assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
889 // secure_lc_io_div4_Aon
890 1/1 assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_secure;
Tests: T1 T2 T3
891 1/1 assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
892 // peri_lc_io_div4_Aon
893 1/1 assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
894 1/1 assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
895 // timers_lc_io_div4_Aon
896 1/1 assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_timers;
Tests: T1 T2 T3
897 1/1 assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
898 // infra_lc_io_div4_0
899 1/1 assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_infra;
Tests: T1 T2 T3
900 1/1 assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
901 // infra_lc_io_div4_Aon
902 1/1 assign lpg_cg_en[16] = clkmgr_aon_cg_en.io_div4_infra;
Tests: T1 T2 T3
903 1/1 assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
904 // infra_lc_0
905 1/1 assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_infra;
Tests: T1 T2 T3
906 1/1 assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
907 // infra_sys_0
908 1/1 assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_infra;
Tests: T1 T2 T3
909 1/1 assign lpg_rst_en[18] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
910 // secure_lc_0
911 1/1 assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure;
Tests: T1 T2 T3
912 1/1 assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
913 // aes_trans_lc_0
914 1/1 assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes;
Tests: T1 T2 T3
915 1/1 assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
916 // hmac_trans_lc_0
917 1/1 assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac;
Tests: T1 T2 T3
918 1/1 assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
919 // kmac_trans_lc_0
920 1/1 assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac;
Tests: T1 T2 T3
921 1/1 assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
922 // otbn_trans_lc_0
923 1/1 assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn;
Tests: T1 T2 T3
924 1/1 assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
925
926 // tie-off unused connections
927 //VCS coverage off
928 // pragma coverage off
929 prim_mubi_pkg::mubi4_t unused_cg_en_0;
930 unreachable assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup;
931 prim_mubi_pkg::mubi4_t unused_cg_en_1;
932 unreachable assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup;
933 prim_mubi_pkg::mubi4_t unused_cg_en_2;
934 unreachable assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup;
935 prim_mubi_pkg::mubi4_t unused_cg_en_3;
936 unreachable assign unused_cg_en_3 = clkmgr_aon_cg_en.usb_powerup;
937 prim_mubi_pkg::mubi4_t unused_cg_en_4;
938 unreachable assign unused_cg_en_4 = clkmgr_aon_cg_en.io_div2_powerup;
939 prim_mubi_pkg::mubi4_t unused_cg_en_5;
940 unreachable assign unused_cg_en_5 = clkmgr_aon_cg_en.aon_secure;
941 prim_mubi_pkg::mubi4_t unused_cg_en_6;
942 unreachable assign unused_cg_en_6 = clkmgr_aon_cg_en.aon_peri;
943 prim_mubi_pkg::mubi4_t unused_cg_en_7;
944 unreachable assign unused_cg_en_7 = clkmgr_aon_cg_en.aon_timers;
945 prim_mubi_pkg::mubi4_t unused_cg_en_8;
946 unreachable assign unused_cg_en_8 = clkmgr_aon_cg_en.usb_infra;
947 prim_mubi_pkg::mubi4_t unused_cg_en_9;
948 unreachable assign unused_cg_en_9 = clkmgr_aon_cg_en.io_infra;
949 prim_mubi_pkg::mubi4_t unused_cg_en_10;
950 unreachable assign unused_cg_en_10 = clkmgr_aon_cg_en.io_div2_infra;
951 prim_mubi_pkg::mubi4_t unused_rst_en_0;
952 unreachable assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel];
953 prim_mubi_pkg::mubi4_t unused_rst_en_1;
954 unreachable assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel];
955 prim_mubi_pkg::mubi4_t unused_rst_en_2;
956 unreachable assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel];
957 prim_mubi_pkg::mubi4_t unused_rst_en_3;
958 unreachable assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel];
959 prim_mubi_pkg::mubi4_t unused_rst_en_4;
960 unreachable assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel];
961 prim_mubi_pkg::mubi4_t unused_rst_en_5;
962 unreachable assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel];
963 prim_mubi_pkg::mubi4_t unused_rst_en_6;
964 unreachable assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel];
965 prim_mubi_pkg::mubi4_t unused_rst_en_7;
966 unreachable assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel];
967 prim_mubi_pkg::mubi4_t unused_rst_en_8;
968 unreachable assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel];
969 prim_mubi_pkg::mubi4_t unused_rst_en_9;
970 unreachable assign unused_rst_en_9 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::DomainAonSel];
971 prim_mubi_pkg::mubi4_t unused_rst_en_10;
972 unreachable assign unused_rst_en_10 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::Domain0Sel];
973 prim_mubi_pkg::mubi4_t unused_rst_en_11;
974 unreachable assign unused_rst_en_11 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel];
975 prim_mubi_pkg::mubi4_t unused_rst_en_12;
976 unreachable assign unused_rst_en_12 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel];
977 prim_mubi_pkg::mubi4_t unused_rst_en_13;
978 unreachable assign unused_rst_en_13 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel];
979 prim_mubi_pkg::mubi4_t unused_rst_en_14;
980 unreachable assign unused_rst_en_14 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel];
981 prim_mubi_pkg::mubi4_t unused_rst_en_15;
982 unreachable assign unused_rst_en_15 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel];
983 prim_mubi_pkg::mubi4_t unused_rst_en_16;
984 unreachable assign unused_rst_en_16 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel];
985 prim_mubi_pkg::mubi4_t unused_rst_en_17;
986 unreachable assign unused_rst_en_17 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel];
987 prim_mubi_pkg::mubi4_t unused_rst_en_18;
988 unreachable assign unused_rst_en_18 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel];
989 prim_mubi_pkg::mubi4_t unused_rst_en_19;
990 unreachable assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel];
991 prim_mubi_pkg::mubi4_t unused_rst_en_20;
992 unreachable assign unused_rst_en_20 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel];
993 prim_mubi_pkg::mubi4_t unused_rst_en_21;
994 unreachable assign unused_rst_en_21 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel];
995 prim_mubi_pkg::mubi4_t unused_rst_en_22;
996 unreachable assign unused_rst_en_22 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::DomainAonSel];
997 prim_mubi_pkg::mubi4_t unused_rst_en_23;
998 unreachable assign unused_rst_en_23 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::Domain0Sel];
999 prim_mubi_pkg::mubi4_t unused_rst_en_24;
1000 unreachable assign unused_rst_en_24 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel];
1001 prim_mubi_pkg::mubi4_t unused_rst_en_25;
1002 unreachable assign unused_rst_en_25 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel];
1003 prim_mubi_pkg::mubi4_t unused_rst_en_26;
1004 unreachable assign unused_rst_en_26 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
1005 prim_mubi_pkg::mubi4_t unused_rst_en_27;
1006 unreachable assign unused_rst_en_27 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel];
1007 prim_mubi_pkg::mubi4_t unused_rst_en_28;
1008 unreachable assign unused_rst_en_28 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel];
1009 prim_mubi_pkg::mubi4_t unused_rst_en_29;
1010 unreachable assign unused_rst_en_29 = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::DomainAonSel];
1011 prim_mubi_pkg::mubi4_t unused_rst_en_30;
1012 unreachable assign unused_rst_en_30 = rstmgr_aon_rst_en.usb[rstmgr_pkg::DomainAonSel];
1013 prim_mubi_pkg::mubi4_t unused_rst_en_31;
1014 unreachable assign unused_rst_en_31 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::DomainAonSel];
1015 prim_mubi_pkg::mubi4_t unused_rst_en_32;
1016 unreachable assign unused_rst_en_32 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::Domain0Sel];
1017 prim_mubi_pkg::mubi4_t unused_rst_en_33;
1018 unreachable assign unused_rst_en_33 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel];
1019 prim_mubi_pkg::mubi4_t unused_rst_en_34;
1020 unreachable assign unused_rst_en_34 = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::DomainAonSel];
1021 prim_mubi_pkg::mubi4_t unused_rst_en_35;
1022 unreachable assign unused_rst_en_35 = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::DomainAonSel];
1023 //VCS coverage on
1024 // pragma coverage on
1025
1026 // Peripheral Instantiation
1027
1028
1029 uart #(
1030 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
1031 ) u_uart0 (
1032
1033 // Input
1034 .cio_rx_i (cio_uart0_rx_p2d),
1035
1036 // Output
1037 .cio_tx_o (cio_uart0_tx_d2p),
1038 .cio_tx_en_o (cio_uart0_tx_en_d2p),
1039
1040 // Interrupt
1041 .intr_tx_watermark_o (intr_uart0_tx_watermark),
1042 .intr_rx_watermark_o (intr_uart0_rx_watermark),
1043 .intr_tx_done_o (intr_uart0_tx_done),
1044 .intr_rx_overflow_o (intr_uart0_rx_overflow),
1045 .intr_rx_frame_err_o (intr_uart0_rx_frame_err),
1046 .intr_rx_break_err_o (intr_uart0_rx_break_err),
1047 .intr_rx_timeout_o (intr_uart0_rx_timeout),
1048 .intr_rx_parity_err_o (intr_uart0_rx_parity_err),
1049 .intr_tx_empty_o (intr_uart0_tx_empty),
1050 // [0]: fatal_fault
1051 .alert_tx_o ( alert_tx[0:0] ),
1052 .alert_rx_i ( alert_rx[0:0] ),
1053
1054 // Inter-module signals
1055 .tl_i(uart0_tl_req),
1056 .tl_o(uart0_tl_rsp),
1057
1058 // Clock and reset connections
1059 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1060 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1061 );
1062 uart #(
1063 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
1064 ) u_uart1 (
1065
1066 // Input
1067 .cio_rx_i (cio_uart1_rx_p2d),
1068
1069 // Output
1070 .cio_tx_o (cio_uart1_tx_d2p),
1071 .cio_tx_en_o (cio_uart1_tx_en_d2p),
1072
1073 // Interrupt
1074 .intr_tx_watermark_o (intr_uart1_tx_watermark),
1075 .intr_rx_watermark_o (intr_uart1_rx_watermark),
1076 .intr_tx_done_o (intr_uart1_tx_done),
1077 .intr_rx_overflow_o (intr_uart1_rx_overflow),
1078 .intr_rx_frame_err_o (intr_uart1_rx_frame_err),
1079 .intr_rx_break_err_o (intr_uart1_rx_break_err),
1080 .intr_rx_timeout_o (intr_uart1_rx_timeout),
1081 .intr_rx_parity_err_o (intr_uart1_rx_parity_err),
1082 .intr_tx_empty_o (intr_uart1_tx_empty),
1083 // [1]: fatal_fault
1084 .alert_tx_o ( alert_tx[1:1] ),
1085 .alert_rx_i ( alert_rx[1:1] ),
1086
1087 // Inter-module signals
1088 .tl_i(uart1_tl_req),
1089 .tl_o(uart1_tl_rsp),
1090
1091 // Clock and reset connections
1092 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1093 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1094 );
1095 uart #(
1096 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
1097 ) u_uart2 (
1098
1099 // Input
1100 .cio_rx_i (cio_uart2_rx_p2d),
1101
1102 // Output
1103 .cio_tx_o (cio_uart2_tx_d2p),
1104 .cio_tx_en_o (cio_uart2_tx_en_d2p),
1105
1106 // Interrupt
1107 .intr_tx_watermark_o (intr_uart2_tx_watermark),
1108 .intr_rx_watermark_o (intr_uart2_rx_watermark),
1109 .intr_tx_done_o (intr_uart2_tx_done),
1110 .intr_rx_overflow_o (intr_uart2_rx_overflow),
1111 .intr_rx_frame_err_o (intr_uart2_rx_frame_err),
1112 .intr_rx_break_err_o (intr_uart2_rx_break_err),
1113 .intr_rx_timeout_o (intr_uart2_rx_timeout),
1114 .intr_rx_parity_err_o (intr_uart2_rx_parity_err),
1115 .intr_tx_empty_o (intr_uart2_tx_empty),
1116 // [2]: fatal_fault
1117 .alert_tx_o ( alert_tx[2:2] ),
1118 .alert_rx_i ( alert_rx[2:2] ),
1119
1120 // Inter-module signals
1121 .tl_i(uart2_tl_req),
1122 .tl_o(uart2_tl_rsp),
1123
1124 // Clock and reset connections
1125 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1126 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1127 );
1128 uart #(
1129 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3])
1130 ) u_uart3 (
1131
1132 // Input
1133 .cio_rx_i (cio_uart3_rx_p2d),
1134
1135 // Output
1136 .cio_tx_o (cio_uart3_tx_d2p),
1137 .cio_tx_en_o (cio_uart3_tx_en_d2p),
1138
1139 // Interrupt
1140 .intr_tx_watermark_o (intr_uart3_tx_watermark),
1141 .intr_rx_watermark_o (intr_uart3_rx_watermark),
1142 .intr_tx_done_o (intr_uart3_tx_done),
1143 .intr_rx_overflow_o (intr_uart3_rx_overflow),
1144 .intr_rx_frame_err_o (intr_uart3_rx_frame_err),
1145 .intr_rx_break_err_o (intr_uart3_rx_break_err),
1146 .intr_rx_timeout_o (intr_uart3_rx_timeout),
1147 .intr_rx_parity_err_o (intr_uart3_rx_parity_err),
1148 .intr_tx_empty_o (intr_uart3_tx_empty),
1149 // [3]: fatal_fault
1150 .alert_tx_o ( alert_tx[3:3] ),
1151 .alert_rx_i ( alert_rx[3:3] ),
1152
1153 // Inter-module signals
1154 .tl_i(uart3_tl_req),
1155 .tl_o(uart3_tl_rsp),
1156
1157 // Clock and reset connections
1158 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1159 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1160 );
1161 gpio #(
1162 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4]),
1163 .GpioAsyncOn(GpioGpioAsyncOn)
1164 ) u_gpio (
1165
1166 // Input
1167 .cio_gpio_i (cio_gpio_gpio_p2d),
1168
1169 // Output
1170 .cio_gpio_o (cio_gpio_gpio_d2p),
1171 .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
1172
1173 // Interrupt
1174 .intr_gpio_o (intr_gpio_gpio),
1175 // [4]: fatal_fault
1176 .alert_tx_o ( alert_tx[4:4] ),
1177 .alert_rx_i ( alert_rx[4:4] ),
1178
1179 // Inter-module signals
1180 .tl_i(gpio_tl_req),
1181 .tl_o(gpio_tl_rsp),
1182
1183 // Clock and reset connections
1184 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1185 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1186 );
1187 spi_device #(
1188 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:5]),
1189 .SramType(SpiDeviceSramType)
1190 ) u_spi_device (
1191
1192 // Input
1193 .cio_sck_i (cio_spi_device_sck_p2d),
1194 .cio_csb_i (cio_spi_device_csb_p2d),
1195 .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d),
1196 .cio_sd_i (cio_spi_device_sd_p2d),
1197
1198 // Output
1199 .cio_sd_o (cio_spi_device_sd_d2p),
1200 .cio_sd_en_o (cio_spi_device_sd_en_d2p),
1201
1202 // Interrupt
1203 .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty),
1204 .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty),
1205 .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow),
1206 .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark),
1207 .intr_readbuf_flip_o (intr_spi_device_readbuf_flip),
1208 .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty),
1209 .intr_tpm_rdfifo_cmd_end_o (intr_spi_device_tpm_rdfifo_cmd_end),
1210 .intr_tpm_rdfifo_drop_o (intr_spi_device_tpm_rdfifo_drop),
1211 // [5]: fatal_fault
1212 .alert_tx_o ( alert_tx[5:5] ),
1213 .alert_rx_i ( alert_rx[5:5] ),
1214
1215 // Inter-module signals
1216 .ram_cfg_i(ast_spi_ram_2p_cfg),
1217 .passthrough_o(spi_device_passthrough_req),
1218 .passthrough_i(spi_device_passthrough_rsp),
1219 .mbist_en_i('0),
1220 .sck_monitor_o(sck_monitor_o),
1221 .tl_i(spi_device_tl_req),
1222 .tl_o(spi_device_tl_rsp),
1223 .scanmode_i,
1224 .scan_rst_ni,
1225
1226 // Clock and reset connections
1227 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1228 .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
1229 .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
1230 );
1231 i2c #(
1232 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6]),
1233 .InputDelayCycles(I2c0InputDelayCycles)
1234 ) u_i2c0 (
1235
1236 // Input
1237 .cio_sda_i (cio_i2c0_sda_p2d),
1238 .cio_scl_i (cio_i2c0_scl_p2d),
1239
1240 // Output
1241 .cio_sda_o (cio_i2c0_sda_d2p),
1242 .cio_sda_en_o (cio_i2c0_sda_en_d2p),
1243 .cio_scl_o (cio_i2c0_scl_d2p),
1244 .cio_scl_en_o (cio_i2c0_scl_en_d2p),
1245
1246 // Interrupt
1247 .intr_fmt_threshold_o (intr_i2c0_fmt_threshold),
1248 .intr_rx_threshold_o (intr_i2c0_rx_threshold),
1249 .intr_acq_threshold_o (intr_i2c0_acq_threshold),
1250 .intr_rx_overflow_o (intr_i2c0_rx_overflow),
1251 .intr_controller_halt_o (intr_i2c0_controller_halt),
1252 .intr_scl_interference_o (intr_i2c0_scl_interference),
1253 .intr_sda_interference_o (intr_i2c0_sda_interference),
1254 .intr_stretch_timeout_o (intr_i2c0_stretch_timeout),
1255 .intr_sda_unstable_o (intr_i2c0_sda_unstable),
1256 .intr_cmd_complete_o (intr_i2c0_cmd_complete),
1257 .intr_tx_stretch_o (intr_i2c0_tx_stretch),
1258 .intr_tx_threshold_o (intr_i2c0_tx_threshold),
1259 .intr_acq_stretch_o (intr_i2c0_acq_stretch),
1260 .intr_unexp_stop_o (intr_i2c0_unexp_stop),
1261 .intr_host_timeout_o (intr_i2c0_host_timeout),
1262 // [6]: fatal_fault
1263 .alert_tx_o ( alert_tx[6:6] ),
1264 .alert_rx_i ( alert_rx[6:6] ),
1265
1266 // Inter-module signals
1267 .ram_cfg_i(ast_ram_1p_cfg),
1268 .tl_i(i2c0_tl_req),
1269 .tl_o(i2c0_tl_rsp),
1270
1271 // Clock and reset connections
1272 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1273 .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
1274 );
1275 i2c #(
1276 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7]),
1277 .InputDelayCycles(I2c1InputDelayCycles)
1278 ) u_i2c1 (
1279
1280 // Input
1281 .cio_sda_i (cio_i2c1_sda_p2d),
1282 .cio_scl_i (cio_i2c1_scl_p2d),
1283
1284 // Output
1285 .cio_sda_o (cio_i2c1_sda_d2p),
1286 .cio_sda_en_o (cio_i2c1_sda_en_d2p),
1287 .cio_scl_o (cio_i2c1_scl_d2p),
1288 .cio_scl_en_o (cio_i2c1_scl_en_d2p),
1289
1290 // Interrupt
1291 .intr_fmt_threshold_o (intr_i2c1_fmt_threshold),
1292 .intr_rx_threshold_o (intr_i2c1_rx_threshold),
1293 .intr_acq_threshold_o (intr_i2c1_acq_threshold),
1294 .intr_rx_overflow_o (intr_i2c1_rx_overflow),
1295 .intr_controller_halt_o (intr_i2c1_controller_halt),
1296 .intr_scl_interference_o (intr_i2c1_scl_interference),
1297 .intr_sda_interference_o (intr_i2c1_sda_interference),
1298 .intr_stretch_timeout_o (intr_i2c1_stretch_timeout),
1299 .intr_sda_unstable_o (intr_i2c1_sda_unstable),
1300 .intr_cmd_complete_o (intr_i2c1_cmd_complete),
1301 .intr_tx_stretch_o (intr_i2c1_tx_stretch),
1302 .intr_tx_threshold_o (intr_i2c1_tx_threshold),
1303 .intr_acq_stretch_o (intr_i2c1_acq_stretch),
1304 .intr_unexp_stop_o (intr_i2c1_unexp_stop),
1305 .intr_host_timeout_o (intr_i2c1_host_timeout),
1306 // [7]: fatal_fault
1307 .alert_tx_o ( alert_tx[7:7] ),
1308 .alert_rx_i ( alert_rx[7:7] ),
1309
1310 // Inter-module signals
1311 .ram_cfg_i(ast_ram_1p_cfg),
1312 .tl_i(i2c1_tl_req),
1313 .tl_o(i2c1_tl_rsp),
1314
1315 // Clock and reset connections
1316 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1317 .rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
1318 );
1319 i2c #(
1320 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8]),
1321 .InputDelayCycles(I2c2InputDelayCycles)
1322 ) u_i2c2 (
1323
1324 // Input
1325 .cio_sda_i (cio_i2c2_sda_p2d),
1326 .cio_scl_i (cio_i2c2_scl_p2d),
1327
1328 // Output
1329 .cio_sda_o (cio_i2c2_sda_d2p),
1330 .cio_sda_en_o (cio_i2c2_sda_en_d2p),
1331 .cio_scl_o (cio_i2c2_scl_d2p),
1332 .cio_scl_en_o (cio_i2c2_scl_en_d2p),
1333
1334 // Interrupt
1335 .intr_fmt_threshold_o (intr_i2c2_fmt_threshold),
1336 .intr_rx_threshold_o (intr_i2c2_rx_threshold),
1337 .intr_acq_threshold_o (intr_i2c2_acq_threshold),
1338 .intr_rx_overflow_o (intr_i2c2_rx_overflow),
1339 .intr_controller_halt_o (intr_i2c2_controller_halt),
1340 .intr_scl_interference_o (intr_i2c2_scl_interference),
1341 .intr_sda_interference_o (intr_i2c2_sda_interference),
1342 .intr_stretch_timeout_o (intr_i2c2_stretch_timeout),
1343 .intr_sda_unstable_o (intr_i2c2_sda_unstable),
1344 .intr_cmd_complete_o (intr_i2c2_cmd_complete),
1345 .intr_tx_stretch_o (intr_i2c2_tx_stretch),
1346 .intr_tx_threshold_o (intr_i2c2_tx_threshold),
1347 .intr_acq_stretch_o (intr_i2c2_acq_stretch),
1348 .intr_unexp_stop_o (intr_i2c2_unexp_stop),
1349 .intr_host_timeout_o (intr_i2c2_host_timeout),
1350 // [8]: fatal_fault
1351 .alert_tx_o ( alert_tx[8:8] ),
1352 .alert_rx_i ( alert_rx[8:8] ),
1353
1354 // Inter-module signals
1355 .ram_cfg_i(ast_ram_1p_cfg),
1356 .tl_i(i2c2_tl_req),
1357 .tl_o(i2c2_tl_rsp),
1358
1359 // Clock and reset connections
1360 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1361 .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
1362 );
1363 pattgen #(
1364 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
1365 ) u_pattgen (
1366
1367 // Output
1368 .cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p),
1369 .cio_pda0_tx_en_o (cio_pattgen_pda0_tx_en_d2p),
1370 .cio_pcl0_tx_o (cio_pattgen_pcl0_tx_d2p),
1371 .cio_pcl0_tx_en_o (cio_pattgen_pcl0_tx_en_d2p),
1372 .cio_pda1_tx_o (cio_pattgen_pda1_tx_d2p),
1373 .cio_pda1_tx_en_o (cio_pattgen_pda1_tx_en_d2p),
1374 .cio_pcl1_tx_o (cio_pattgen_pcl1_tx_d2p),
1375 .cio_pcl1_tx_en_o (cio_pattgen_pcl1_tx_en_d2p),
1376
1377 // Interrupt
1378 .intr_done_ch0_o (intr_pattgen_done_ch0),
1379 .intr_done_ch1_o (intr_pattgen_done_ch1),
1380 // [9]: fatal_fault
1381 .alert_tx_o ( alert_tx[9:9] ),
1382 .alert_rx_i ( alert_rx[9:9] ),
1383
1384 // Inter-module signals
1385 .tl_i(pattgen_tl_req),
1386 .tl_o(pattgen_tl_rsp),
1387
1388 // Clock and reset connections
1389 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1390 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1391 );
1392 rv_timer #(
1393 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
1394 ) u_rv_timer (
1395
1396 // Interrupt
1397 .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0),
1398 // [10]: fatal_fault
1399 .alert_tx_o ( alert_tx[10:10] ),
1400 .alert_rx_i ( alert_rx[10:10] ),
1401
1402 // Inter-module signals
1403 .tl_i(rv_timer_tl_req),
1404 .tl_o(rv_timer_tl_rsp),
1405
1406 // Clock and reset connections
1407 .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
1408 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1409 );
1410 otp_ctrl #(
1411 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:11]),
1412 .MemInitFile(OtpCtrlMemInitFile),
1413 .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
1414 .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm),
1415 .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit)
1416 ) u_otp_ctrl (
1417
1418 // Output
1419 .cio_test_o (cio_otp_ctrl_test_d2p),
1420 .cio_test_en_o (cio_otp_ctrl_test_en_d2p),
1421
1422 // Interrupt
1423 .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
1424 .intr_otp_error_o (intr_otp_ctrl_otp_error),
1425 // [11]: fatal_macro_error
1426 // [12]: fatal_check_error
1427 // [13]: fatal_bus_integ_error
1428 // [14]: fatal_prim_otp_alert
1429 // [15]: recov_prim_otp_alert
1430 .alert_tx_o ( alert_tx[15:11] ),
1431 .alert_rx_i ( alert_rx[15:11] ),
1432
1433 // Inter-module signals
1434 .otp_ext_voltage_h_io(otp_ext_voltage_h_io),
1435 .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
1436 .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
1437 .edn_o(edn0_edn_req[1]),
1438 .edn_i(edn0_edn_rsp[1]),
1439 .pwr_otp_i(pwrmgr_aon_pwr_otp_req),
1440 .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp),
1441 .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_req),
1442 .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_rsp),
1443 .lc_otp_program_i(lc_ctrl_lc_otp_program_req),
1444 .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp),
1445 .otp_lc_data_o(otp_ctrl_otp_lc_data),
1446 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
1447 .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
1448 .lc_owner_seed_sw_rw_en_i(lc_ctrl_pkg::Off),
1449 .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
1450 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1451 .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
1452 .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key),
1453 .flash_otp_key_i(flash_ctrl_otp_req),
1454 .flash_otp_key_o(flash_ctrl_otp_rsp),
1455 .sram_otp_key_i(otp_ctrl_sram_otp_key_req),
1456 .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp),
1457 .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req),
1458 .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp),
1459 .otp_broadcast_o(otp_ctrl_otp_broadcast),
1460 .obs_ctrl_i(ast_obs_ctrl),
1461 .otp_obs_o(otp_obs_o),
1462 .core_tl_i(otp_ctrl_core_tl_req),
1463 .core_tl_o(otp_ctrl_core_tl_rsp),
1464 .prim_tl_i(otp_ctrl_prim_tl_req),
1465 .prim_tl_o(otp_ctrl_prim_tl_rsp),
1466 .scanmode_i,
1467 .scan_rst_ni,
1468 .scan_en_i,
1469
1470 // Clock and reset connections
1471 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1472 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
1473 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1474 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1475 );
1476 lc_ctrl #(
1477 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]),
1478 .SecVolatileRawUnlockEn(SecLcCtrlVolatileRawUnlockEn),
1479 .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
1480 .RndCnstLcKeymgrDivTestUnlocked(RndCnstLcCtrlLcKeymgrDivTestUnlocked),
1481 .RndCnstLcKeymgrDivDev(RndCnstLcCtrlLcKeymgrDivDev),
1482 .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction),
1483 .RndCnstLcKeymgrDivRma(RndCnstLcCtrlLcKeymgrDivRma),
1484 .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens),
1485 .SiliconCreatorId(LcCtrlSiliconCreatorId),
1486 .ProductId(LcCtrlProductId),
1487 .RevisionId(LcCtrlRevisionId),
1488 .IdcodeValue(LcCtrlIdcodeValue)
1489 ) u_lc_ctrl (
1490 // [16]: fatal_prog_error
1491 // [17]: fatal_state_error
1492 // [18]: fatal_bus_integ_error
1493 .alert_tx_o ( alert_tx[18:16] ),
1494 .alert_rx_i ( alert_rx[18:16] ),
1495
1496 // Inter-module signals
1497 .jtag_i(pinmux_aon_lc_jtag_req),
1498 .jtag_o(pinmux_aon_lc_jtag_rsp),
1499 .esc_scrap_state0_tx_i(alert_handler_esc_tx[1]),
1500 .esc_scrap_state0_rx_o(alert_handler_esc_rx[1]),
1501 .esc_scrap_state1_tx_i(alert_handler_esc_tx[2]),
1502 .esc_scrap_state1_rx_o(alert_handler_esc_rx[2]),
1503 .pwr_lc_i(pwrmgr_aon_pwr_lc_req),
1504 .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp),
1505 .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req),
1506 .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp),
1507 .otp_lc_data_i(otp_ctrl_otp_lc_data),
1508 .lc_otp_program_o(lc_ctrl_lc_otp_program_req),
1509 .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp),
1510 .kmac_data_o(kmac_app_req[1]),
1511 .kmac_data_i(kmac_app_rsp[1]),
1512 .lc_dft_en_o(lc_ctrl_lc_dft_en),
1513 .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en),
1514 .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en),
1515 .lc_cpu_en_o(lc_ctrl_lc_cpu_en),
1516 .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en),
1517 .lc_escalate_en_o(lc_ctrl_lc_escalate_en),
1518 .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
1519 .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
1520 .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req),
1521 .lc_flash_rma_ack_i(lc_ctrl_lc_flash_rma_ack),
1522 .lc_flash_rma_seed_o(flash_ctrl_rma_seed),
1523 .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en),
1524 .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en),
1525 .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en),
1526 .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en),
1527 .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en),
1528 .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en),
1529 .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div),
1530 .otp_device_id_i(lc_ctrl_otp_device_id),
1531 .otp_manuf_state_i(lc_ctrl_otp_manuf_state),
1532 .hw_rev_o(),
1533 .strap_en_override_o(lc_ctrl_strap_en_override),
1534 .tl_i(lc_ctrl_tl_req),
1535 .tl_o(lc_ctrl_tl_rsp),
1536 .scanmode_i,
1537 .scan_rst_ni,
1538
1539 // Clock and reset connections
1540 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1541 .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure),
1542 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1543 .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1544 );
1545 alert_handler #(
1546 .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
1547 .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
1548 ) u_alert_handler (
1549
1550 // Interrupt
1551 .intr_classa_o (intr_alert_handler_classa),
1552 .intr_classb_o (intr_alert_handler_classb),
1553 .intr_classc_o (intr_alert_handler_classc),
1554 .intr_classd_o (intr_alert_handler_classd),
1555
1556 // Inter-module signals
1557 .crashdump_o(alert_handler_crashdump),
1558 .edn_o(edn0_edn_req[4]),
1559 .edn_i(edn0_edn_rsp[4]),
1560 .esc_rx_i(alert_handler_esc_rx),
1561 .esc_tx_o(alert_handler_esc_tx),
1562 .tl_i(alert_handler_tl_req),
1563 .tl_o(alert_handler_tl_rsp),
1564 // alert signals
1565 .alert_rx_o ( alert_rx ),
1566 .alert_tx_i ( alert_tx ),
1567 // synchronized clock gated / reset asserted
1568 // indications for each alert
1569 .lpg_cg_en_i ( lpg_cg_en ),
1570 .lpg_rst_en_i ( lpg_rst_en ),
1571
1572 // Clock and reset connections
1573 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1574 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
1575 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]),
1576 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1577 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1578 );
1579 spi_host #(
1580 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19])
1581 ) u_spi_host0 (
1582
1583 // Input
1584 .cio_sd_i (cio_spi_host0_sd_p2d),
1585
1586 // Output
1587 .cio_sck_o (cio_spi_host0_sck_d2p),
1588 .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
1589 .cio_csb_o (cio_spi_host0_csb_d2p),
1590 .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
1591 .cio_sd_o (cio_spi_host0_sd_d2p),
1592 .cio_sd_en_o (cio_spi_host0_sd_en_d2p),
1593
1594 // Interrupt
1595 .intr_error_o (intr_spi_host0_error),
1596 .intr_spi_event_o (intr_spi_host0_spi_event),
1597 // [19]: fatal_fault
1598 .alert_tx_o ( alert_tx[19:19] ),
1599 .alert_rx_i ( alert_rx[19:19] ),
1600
1601 // Inter-module signals
1602 .passthrough_i(spi_device_passthrough_req),
1603 .passthrough_o(spi_device_passthrough_rsp),
1604 .tl_i(spi_host0_tl_req),
1605 .tl_o(spi_host0_tl_rsp),
1606
1607 // Clock and reset connections
1608 .clk_i (clkmgr_aon_clocks.clk_io_peri),
1609 .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
1610 );
1611 spi_host #(
1612 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20])
1613 ) u_spi_host1 (
1614
1615 // Input
1616 .cio_sd_i (cio_spi_host1_sd_p2d),
1617
1618 // Output
1619 .cio_sck_o (cio_spi_host1_sck_d2p),
1620 .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
1621 .cio_csb_o (cio_spi_host1_csb_d2p),
1622 .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
1623 .cio_sd_o (cio_spi_host1_sd_d2p),
1624 .cio_sd_en_o (cio_spi_host1_sd_en_d2p),
1625
1626 // Interrupt
1627 .intr_error_o (intr_spi_host1_error),
1628 .intr_spi_event_o (intr_spi_host1_spi_event),
1629 // [20]: fatal_fault
1630 .alert_tx_o ( alert_tx[20:20] ),
1631 .alert_rx_i ( alert_rx[20:20] ),
1632
1633 // Inter-module signals
1634 .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
1635 .passthrough_o(),
1636 .tl_i(spi_host1_tl_req),
1637 .tl_o(spi_host1_tl_rsp),
1638
1639 // Clock and reset connections
1640 .clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
1641 .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
1642 );
1643 usbdev #(
1644 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]),
1645 .Stub(UsbdevStub),
1646 .RcvrWakeTimeUs(UsbdevRcvrWakeTimeUs)
1647 ) u_usbdev (
1648
1649 // Input
1650 .cio_sense_i (cio_usbdev_sense_p2d),
1651 .cio_usb_dp_i (cio_usbdev_usb_dp_p2d),
1652 .cio_usb_dn_i (cio_usbdev_usb_dn_p2d),
1653
1654 // Output
1655 .cio_usb_dp_o (cio_usbdev_usb_dp_d2p),
1656 .cio_usb_dp_en_o (cio_usbdev_usb_dp_en_d2p),
1657 .cio_usb_dn_o (cio_usbdev_usb_dn_d2p),
1658 .cio_usb_dn_en_o (cio_usbdev_usb_dn_en_d2p),
1659
1660 // Interrupt
1661 .intr_pkt_received_o (intr_usbdev_pkt_received),
1662 .intr_pkt_sent_o (intr_usbdev_pkt_sent),
1663 .intr_disconnected_o (intr_usbdev_disconnected),
1664 .intr_host_lost_o (intr_usbdev_host_lost),
1665 .intr_link_reset_o (intr_usbdev_link_reset),
1666 .intr_link_suspend_o (intr_usbdev_link_suspend),
1667 .intr_link_resume_o (intr_usbdev_link_resume),
1668 .intr_av_out_empty_o (intr_usbdev_av_out_empty),
1669 .intr_rx_full_o (intr_usbdev_rx_full),
1670 .intr_av_overflow_o (intr_usbdev_av_overflow),
1671 .intr_link_in_err_o (intr_usbdev_link_in_err),
1672 .intr_rx_crc_err_o (intr_usbdev_rx_crc_err),
1673 .intr_rx_pid_err_o (intr_usbdev_rx_pid_err),
1674 .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err),
1675 .intr_frame_o (intr_usbdev_frame),
1676 .intr_powered_o (intr_usbdev_powered),
1677 .intr_link_out_err_o (intr_usbdev_link_out_err),
1678 .intr_av_setup_empty_o (intr_usbdev_av_setup_empty),
1679 // [21]: fatal_fault
1680 .alert_tx_o ( alert_tx[21:21] ),
1681 .alert_rx_i ( alert_rx[21:21] ),
1682
1683 // Inter-module signals
1684 .usb_rx_d_i(usbdev_usb_rx_d_i),
1685 .usb_tx_d_o(usbdev_usb_tx_d_o),
1686 .usb_tx_se0_o(usbdev_usb_tx_se0_o),
1687 .usb_tx_use_d_se0_o(usbdev_usb_tx_use_d_se0_o),
1688 .usb_dp_pullup_o(usbdev_usb_dp_pullup),
1689 .usb_dn_pullup_o(usbdev_usb_dn_pullup),
1690 .usb_rx_enable_o(usbdev_usb_rx_enable_o),
1691 .usb_ref_val_o(usbdev_usb_ref_val_o),
1692 .usb_ref_pulse_o(usbdev_usb_ref_pulse_o),
1693 .usb_aon_suspend_req_o(usbdev_usb_aon_suspend_req),
1694 .usb_aon_wake_ack_o(usbdev_usb_aon_wake_ack),
1695 .usb_aon_bus_reset_i(usbdev_usb_aon_bus_reset),
1696 .usb_aon_sense_lost_i(usbdev_usb_aon_sense_lost),
1697 .usb_aon_bus_not_idle_i(usbdev_usb_aon_bus_not_idle),
1698 .usb_aon_wake_detect_active_i(pinmux_aon_usbdev_wake_detect_active),
1699 .ram_cfg_i(ast_usb_ram_1p_cfg),
1700 .tl_i(usbdev_tl_req),
1701 .tl_o(usbdev_tl_rsp),
1702
1703 // Clock and reset connections
1704 .clk_i (clkmgr_aon_clocks.clk_usb_peri),
1705 .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
1706 .rst_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
1707 .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel])
1708 );
1709 pwrmgr #(
1710 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22])
1711 ) u_pwrmgr_aon (
1712
1713 // Interrupt
1714 .intr_wakeup_o (intr_pwrmgr_aon_wakeup),
1715 // [22]: fatal_fault
1716 .alert_tx_o ( alert_tx[22:22] ),
1717 .alert_rx_i ( alert_rx[22:22] ),
1718
1719 // Inter-module signals
1720 .pwr_ast_o(pwrmgr_ast_req_o),
1721 .pwr_ast_i(pwrmgr_ast_rsp_i),
1722 .pwr_rst_o(pwrmgr_aon_pwr_rst_req),
1723 .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp),
1724 .pwr_clk_o(pwrmgr_aon_pwr_clk_req),
1725 .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp),
1726 .pwr_otp_o(pwrmgr_aon_pwr_otp_req),
1727 .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp),
1728 .pwr_lc_o(pwrmgr_aon_pwr_lc_req),
1729 .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp),
1730 .pwr_flash_i(pwrmgr_aon_pwr_flash),
1731 .esc_rst_tx_i(alert_handler_esc_tx[3]),
1732 .esc_rst_rx_o(alert_handler_esc_rx[3]),
1733 .pwr_cpu_i(rv_core_ibex_pwrmgr),
1734 .wakeups_i(pwrmgr_aon_wakeups),
1735 .rstreqs_i(pwrmgr_aon_rstreqs),
1736 .ndmreset_req_i(rv_dm_ndmreset_req),
1737 .strap_o(pwrmgr_aon_strap),
1738 .low_power_o(pwrmgr_aon_low_power),
1739 .rom_ctrl_i(rom_ctrl_pwrmgr_data),
1740 .fetch_en_o(pwrmgr_aon_fetch_en),
1741 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1742 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1743 .sw_rst_req_i(rstmgr_aon_sw_rst_req),
1744 .tl_i(pwrmgr_aon_tl_req),
1745 .tl_o(pwrmgr_aon_tl_rsp),
1746
1747 // Clock and reset connections
1748 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1749 .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup),
1750 .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1751 .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
1752 .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1753 .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]),
1754 .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1755 .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1756 .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel])
1757 );
1758 rstmgr #(
1759 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]),
1760 .SecCheck(SecRstmgrAonCheck),
1761 .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay)
1762 ) u_rstmgr_aon (
1763 // [23]: fatal_fault
1764 // [24]: fatal_cnsty_fault
1765 .alert_tx_o ( alert_tx[24:23] ),
1766 .alert_rx_i ( alert_rx[24:23] ),
1767
1768 // Inter-module signals
1769 .por_n_i(por_n_i),
1770 .pwr_i(pwrmgr_aon_pwr_rst_req),
1771 .pwr_o(pwrmgr_aon_pwr_rst_rsp),
1772 .resets_o(rstmgr_aon_resets),
1773 .rst_en_o(rstmgr_aon_rst_en),
1774 .alert_dump_i(alert_handler_crashdump),
1775 .cpu_dump_i(rv_core_ibex_crash_dump),
1776 .sw_rst_req_o(rstmgr_aon_sw_rst_req),
1777 .tl_i(rstmgr_aon_tl_req),
1778 .tl_o(rstmgr_aon_tl_rsp),
1779 .scanmode_i,
1780 .scan_rst_ni,
1781
1782 // Clock and reset connections
1783 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1784 .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1785 .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
1786 .clk_main_i (clkmgr_aon_clocks.clk_main_powerup),
1787 .clk_io_i (clkmgr_aon_clocks.clk_io_powerup),
1788 .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup),
1789 .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup),
1790 .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1791 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1792 .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
1793 );
1794 clkmgr #(
1795 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25])
1796 ) u_clkmgr_aon (
1797 // [25]: recov_fault
1798 // [26]: fatal_fault
1799 .alert_tx_o ( alert_tx[26:25] ),
1800 .alert_rx_i ( alert_rx[26:25] ),
1801
1802 // Inter-module signals
1803 .clocks_o(clkmgr_aon_clocks),
1804 .cg_en_o(clkmgr_aon_cg_en),
1805 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1806 .io_clk_byp_req_o(io_clk_byp_req_o),
1807 .io_clk_byp_ack_i(io_clk_byp_ack_i),
1808 .all_clk_byp_req_o(all_clk_byp_req_o),
1809 .all_clk_byp_ack_i(all_clk_byp_ack_i),
1810 .hi_speed_sel_o(hi_speed_sel_o),
1811 .div_step_down_req_i(div_step_down_req_i),
1812 .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req),
1813 .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack),
1814 .jitter_en_o(clk_main_jitter_en_o),
1815 .pwr_i(pwrmgr_aon_pwr_clk_req),
1816 .pwr_o(pwrmgr_aon_pwr_clk_rsp),
1817 .idle_i(clkmgr_aon_idle),
1818 .calib_rdy_i(calib_rdy_i),
1819 .tl_i(clkmgr_aon_tl_req),
1820 .tl_o(clkmgr_aon_tl_rsp),
1821 .scanmode_i,
1822
1823 // Clock and reset connections
1824 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1825 .clk_main_i (clk_main_i),
1826 .clk_io_i (clk_io_i),
1827 .clk_usb_i (clk_usb_i),
1828 .clk_aon_i (clk_aon_i),
1829 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]),
1830 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1831 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
1832 .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]),
1833 .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]),
1834 .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1835 .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]),
1836 .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::DomainAonSel]),
1837 .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1838 .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]),
1839 .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]),
1840 .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1841 .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
1842 .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel])
1843 );
1844 sysrst_ctrl #(
1845 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27])
1846 ) u_sysrst_ctrl_aon (
1847
1848 // Input
1849 .cio_ac_present_i (cio_sysrst_ctrl_aon_ac_present_p2d),
1850 .cio_key0_in_i (cio_sysrst_ctrl_aon_key0_in_p2d),
1851 .cio_key1_in_i (cio_sysrst_ctrl_aon_key1_in_p2d),
1852 .cio_key2_in_i (cio_sysrst_ctrl_aon_key2_in_p2d),
1853 .cio_pwrb_in_i (cio_sysrst_ctrl_aon_pwrb_in_p2d),
1854 .cio_lid_open_i (cio_sysrst_ctrl_aon_lid_open_p2d),
1855 .cio_ec_rst_l_i (cio_sysrst_ctrl_aon_ec_rst_l_p2d),
1856 .cio_flash_wp_l_i (cio_sysrst_ctrl_aon_flash_wp_l_p2d),
1857
1858 // Output
1859 .cio_bat_disable_o (cio_sysrst_ctrl_aon_bat_disable_d2p),
1860 .cio_bat_disable_en_o (cio_sysrst_ctrl_aon_bat_disable_en_d2p),
1861 .cio_key0_out_o (cio_sysrst_ctrl_aon_key0_out_d2p),
1862 .cio_key0_out_en_o (cio_sysrst_ctrl_aon_key0_out_en_d2p),
1863 .cio_key1_out_o (cio_sysrst_ctrl_aon_key1_out_d2p),
1864 .cio_key1_out_en_o (cio_sysrst_ctrl_aon_key1_out_en_d2p),
1865 .cio_key2_out_o (cio_sysrst_ctrl_aon_key2_out_d2p),
1866 .cio_key2_out_en_o (cio_sysrst_ctrl_aon_key2_out_en_d2p),
1867 .cio_pwrb_out_o (cio_sysrst_ctrl_aon_pwrb_out_d2p),
1868 .cio_pwrb_out_en_o (cio_sysrst_ctrl_aon_pwrb_out_en_d2p),
1869 .cio_z3_wakeup_o (cio_sysrst_ctrl_aon_z3_wakeup_d2p),
1870 .cio_z3_wakeup_en_o (cio_sysrst_ctrl_aon_z3_wakeup_en_d2p),
1871 .cio_ec_rst_l_o (cio_sysrst_ctrl_aon_ec_rst_l_d2p),
1872 .cio_ec_rst_l_en_o (cio_sysrst_ctrl_aon_ec_rst_l_en_d2p),
1873 .cio_flash_wp_l_o (cio_sysrst_ctrl_aon_flash_wp_l_d2p),
1874 .cio_flash_wp_l_en_o (cio_sysrst_ctrl_aon_flash_wp_l_en_d2p),
1875
1876 // Interrupt
1877 .intr_event_detected_o (intr_sysrst_ctrl_aon_event_detected),
1878 // [27]: fatal_fault
1879 .alert_tx_o ( alert_tx[27:27] ),
1880 .alert_rx_i ( alert_rx[27:27] ),
1881
1882 // Inter-module signals
1883 .wkup_req_o(pwrmgr_aon_wakeups[0]),
1884 .rst_req_o(pwrmgr_aon_rstreqs[0]),
1885 .tl_i(sysrst_ctrl_aon_tl_req),
1886 .tl_o(sysrst_ctrl_aon_tl_rsp),
1887
1888 // Clock and reset connections
1889 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1890 .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
1891 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1892 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1893 );
1894 adc_ctrl #(
1895 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28])
1896 ) u_adc_ctrl_aon (
1897
1898 // Interrupt
1899 .intr_match_pending_o (intr_adc_ctrl_aon_match_pending),
1900 // [28]: fatal_fault
1901 .alert_tx_o ( alert_tx[28:28] ),
1902 .alert_rx_i ( alert_rx[28:28] ),
1903
1904 // Inter-module signals
1905 .adc_o(adc_req_o),
1906 .adc_i(adc_rsp_i),
1907 .wkup_req_o(pwrmgr_aon_wakeups[1]),
1908 .tl_i(adc_ctrl_aon_tl_req),
1909 .tl_o(adc_ctrl_aon_tl_rsp),
1910
1911 // Clock and reset connections
1912 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1913 .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
1914 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1915 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1916 );
1917 pwm #(
1918 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29])
1919 ) u_pwm_aon (
1920
1921 // Output
1922 .cio_pwm_o (cio_pwm_aon_pwm_d2p),
1923 .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p),
1924 // [29]: fatal_fault
1925 .alert_tx_o ( alert_tx[29:29] ),
1926 .alert_rx_i ( alert_rx[29:29] ),
1927
1928 // Inter-module signals
1929 .tl_i(pwm_aon_tl_req),
1930 .tl_o(pwm_aon_tl_rsp),
1931
1932 // Clock and reset connections
1933 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1934 .clk_core_i (clkmgr_aon_clocks.clk_aon_peri),
1935 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1936 .rst_core_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1937 );
1938 pinmux #(
1939 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
1940 .SecVolatileRawUnlockEn(SecPinmuxAonVolatileRawUnlockEn),
1941 .TargetCfg(PinmuxAonTargetCfg)
1942 ) u_pinmux_aon (
1943 // [30]: fatal_fault
1944 .alert_tx_o ( alert_tx[30:30] ),
1945 .alert_rx_i ( alert_rx[30:30] ),
1946
1947 // Inter-module signals
1948 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1949 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1950 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
1951 .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
1952 .pinmux_hw_debug_en_o(pinmux_aon_pinmux_hw_debug_en),
1953 .lc_jtag_o(pinmux_aon_lc_jtag_req),
1954 .lc_jtag_i(pinmux_aon_lc_jtag_rsp),
1955 .rv_jtag_o(pinmux_aon_rv_jtag_req),
1956 .rv_jtag_i(pinmux_aon_rv_jtag_rsp),
1957 .dft_jtag_o(pinmux_aon_dft_jtag_req),
1958 .dft_jtag_i(pinmux_aon_dft_jtag_rsp),
1959 .dft_strap_test_o(dft_strap_test_o),
1960 .dft_hold_tap_sel_i(dft_hold_tap_sel_i),
1961 .sleep_en_i(pwrmgr_aon_low_power),
1962 .strap_en_i(pwrmgr_aon_strap),
1963 .strap_en_override_i(lc_ctrl_strap_en_override),
1964 .pin_wkup_req_o(pwrmgr_aon_wakeups[2]),
1965 .usbdev_dppullup_en_i(usbdev_usb_dp_pullup),
1966 .usbdev_dnpullup_en_i(usbdev_usb_dn_pullup),
1967 .usb_dppullup_en_o(usb_dp_pullup_en_o),
1968 .usb_dnpullup_en_o(usb_dn_pullup_en_o),
1969 .usb_wkup_req_o(pwrmgr_aon_wakeups[3]),
1970 .usbdev_suspend_req_i(usbdev_usb_aon_suspend_req),
1971 .usbdev_wake_ack_i(usbdev_usb_aon_wake_ack),
1972 .usbdev_bus_not_idle_o(usbdev_usb_aon_bus_not_idle),
1973 .usbdev_bus_reset_o(usbdev_usb_aon_bus_reset),
1974 .usbdev_sense_lost_o(usbdev_usb_aon_sense_lost),
1975 .usbdev_wake_detect_active_o(pinmux_aon_usbdev_wake_detect_active),
1976 .tl_i(pinmux_aon_tl_req),
1977 .tl_o(pinmux_aon_tl_rsp),
1978
1979 .periph_to_mio_i (mio_d2p ),
1980 .periph_to_mio_oe_i (mio_en_d2p ),
1981 .mio_to_periph_o (mio_p2d ),
1982
1983 .mio_attr_o,
1984 .mio_out_o,
1985 .mio_oe_o,
1986 .mio_in_i,
1987
1988 .periph_to_dio_i (dio_d2p ),
1989 .periph_to_dio_oe_i (dio_en_d2p ),
1990 .dio_to_periph_o (dio_p2d ),
1991
1992 .dio_attr_o,
1993 .dio_out_o,
1994 .dio_oe_o,
1995 .dio_in_i,
1996
1997 .scanmode_i,
1998
1999 // Clock and reset connections
2000 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
2001 .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
2002 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2003 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
2004 .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
2005 );
2006 aon_timer #(
2007 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31])
2008 ) u_aon_timer_aon (
2009
2010 // Interrupt
2011 .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired),
2012 .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark),
2013 // [31]: fatal_fault
2014 .alert_tx_o ( alert_tx[31:31] ),
2015 .alert_rx_i ( alert_rx[31:31] ),
2016
2017 // Inter-module signals
2018 .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark),
2019 .wkup_req_o(pwrmgr_aon_wakeups[4]),
2020 .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[1]),
2021 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2022 .sleep_mode_i(pwrmgr_aon_low_power),
2023 .tl_i(aon_timer_aon_tl_req),
2024 .tl_o(aon_timer_aon_tl_rsp),
2025
2026 // Clock and reset connections
2027 .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
2028 .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers),
2029 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2030 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
2031 );
2032 sensor_ctrl #(
2033 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32])
2034 ) u_sensor_ctrl_aon (
2035
2036 // Output
2037 .cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p),
2038 .cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
2039
2040 // Interrupt
2041 .intr_io_status_change_o (intr_sensor_ctrl_aon_io_status_change),
2042 .intr_init_status_change_o (intr_sensor_ctrl_aon_init_status_change),
2043 // [32]: recov_alert
2044 // [33]: fatal_alert
2045 .alert_tx_o ( alert_tx[33:32] ),
2046 .alert_rx_i ( alert_rx[33:32] ),
2047
2048 // Inter-module signals
2049 .ast_alert_i(sensor_ctrl_ast_alert_req_i),
2050 .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
2051 .ast_status_i(sensor_ctrl_ast_status_i),
2052 .ast_init_done_i(ast_init_done_i),
2053 .ast2pinmux_i(ast2pinmux_i),
2054 .wkup_req_o(pwrmgr_aon_wakeups[5]),
2055 .manual_pad_attr_o(sensor_ctrl_manual_pad_attr_o),
2056 .tl_i(sensor_ctrl_aon_tl_req),
2057 .tl_o(sensor_ctrl_aon_tl_rsp),
2058
2059 // Clock and reset connections
2060 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
2061 .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
2062 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2063 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
2064 );
2065 sram_ctrl #(
2066 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
2067 .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
2068 .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
2069 .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed),
2070 .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm),
2071 .MemSizeRam(4096),
2072 .InstrExec(SramCtrlRetAonInstrExec),
2073 .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf)
2074 ) u_sram_ctrl_ret_aon (
2075 // [34]: fatal_error
2076 .alert_tx_o ( alert_tx[34:34] ),
2077 .alert_rx_i ( alert_rx[34:34] ),
2078
2079 // Inter-module signals
2080 .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
2081 .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]),
2082 .cfg_i(ast_ram_1p_cfg),
2083 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2084 .lc_hw_debug_en_i(lc_ctrl_pkg::Off),
2085 .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False),
2086 .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req),
2087 .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp),
2088 .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req),
2089 .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp),
2090
2091 // Clock and reset connections
2092 .clk_i (clkmgr_aon_clocks.clk_io_div4_infra),
2093 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2094 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2095 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
2096 );
2097 flash_ctrl #(
2098 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]),
2099 .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
2100 .RndCnstDataKey(RndCnstFlashCtrlDataKey),
2101 .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds),
2102 .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
2103 .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm),
2104 .SecScrambleEn(SecFlashCtrlScrambleEn),
2105 .ProgFifoDepth(FlashCtrlProgFifoDepth),
2106 .RdFifoDepth(FlashCtrlRdFifoDepth)
2107 ) u_flash_ctrl (
2108
2109 // Input
2110 .cio_tck_i (cio_flash_ctrl_tck_p2d),
2111 .cio_tms_i (cio_flash_ctrl_tms_p2d),
2112 .cio_tdi_i (cio_flash_ctrl_tdi_p2d),
2113
2114 // Output
2115 .cio_tdo_o (cio_flash_ctrl_tdo_d2p),
2116 .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p),
2117
2118 // Interrupt
2119 .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
2120 .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
2121 .intr_rd_full_o (intr_flash_ctrl_rd_full),
2122 .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
2123 .intr_op_done_o (intr_flash_ctrl_op_done),
2124 .intr_corr_err_o (intr_flash_ctrl_corr_err),
2125 // [35]: recov_err
2126 // [36]: fatal_std_err
2127 // [37]: fatal_err
2128 // [38]: fatal_prim_flash_alert
2129 // [39]: recov_prim_flash_alert
2130 .alert_tx_o ( alert_tx[39:35] ),
2131 .alert_rx_i ( alert_rx[39:35] ),
2132
2133 // Inter-module signals
2134 .otp_o(flash_ctrl_otp_req),
2135 .otp_i(flash_ctrl_otp_rsp),
2136 .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en),
2137 .flash_bist_enable_i(flash_bist_enable_i),
2138 .flash_power_down_h_i(flash_power_down_h_i),
2139 .flash_power_ready_h_i(flash_power_ready_h_i),
2140 .flash_test_mode_a_io(flash_test_mode_a_io),
2141 .flash_test_voltage_h_io(flash_test_voltage_h_io),
2142 .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
2143 .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en),
2144 .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en),
2145 .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en),
2146 .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
2147 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2148 .rma_req_i(lc_ctrl_lc_flash_rma_req),
2149 .rma_ack_o(lc_ctrl_lc_flash_rma_ack[0]),
2150 .rma_seed_i(flash_ctrl_rma_seed),
2151 .pwrmgr_o(pwrmgr_aon_pwr_flash),
2152 .keymgr_o(flash_ctrl_keymgr),
2153 .obs_ctrl_i(ast_obs_ctrl),
2154 .fla_obs_o(flash_obs_o),
2155 .core_tl_i(flash_ctrl_core_tl_req),
2156 .core_tl_o(flash_ctrl_core_tl_rsp),
2157 .prim_tl_i(flash_ctrl_prim_tl_req),
2158 .prim_tl_o(flash_ctrl_prim_tl_rsp),
2159 .mem_tl_i(flash_ctrl_mem_tl_req),
2160 .mem_tl_o(flash_ctrl_mem_tl_rsp),
2161 .scanmode_i,
2162 .scan_rst_ni,
2163 .scan_en_i,
2164
2165 // Clock and reset connections
2166 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2167 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2168 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2169 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2170 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2171 );
2172 rv_dm #(
2173 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]),
2174 .IdcodeValue(RvDmIdcodeValue)
2175 ) u_rv_dm (
2176 // [40]: fatal_fault
2177 .alert_tx_o ( alert_tx[40:40] ),
2178 .alert_rx_i ( alert_rx[40:40] ),
2179
2180 // Inter-module signals
2181 .next_dm_addr_i('0),
2182 .jtag_i(pinmux_aon_rv_jtag_req),
2183 .jtag_o(pinmux_aon_rv_jtag_rsp),
2184 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2185 .lc_dft_en_i(lc_ctrl_lc_dft_en),
2186 .pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en),
2187 .otp_dis_rv_dm_late_debug_i(rv_dm_otp_dis_rv_dm_late_debug),
2188 .unavailable_i(1'b0),
2189 .ndmreset_req_o(rv_dm_ndmreset_req),
2190 .dmactive_o(),
2191 .debug_req_o(rv_dm_debug_req),
2192 .sba_tl_h_o(main_tl_rv_dm__sba_req),
2193 .sba_tl_h_i(main_tl_rv_dm__sba_rsp),
2194 .regs_tl_d_i(rv_dm_regs_tl_d_req),
2195 .regs_tl_d_o(rv_dm_regs_tl_d_rsp),
2196 .mem_tl_d_i(rv_dm_mem_tl_d_req),
2197 .mem_tl_d_o(rv_dm_mem_tl_d_rsp),
2198 .scanmode_i,
2199 .scan_rst_ni,
2200
2201 // Clock and reset connections
2202 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2203 .clk_lc_i (clkmgr_aon_clocks.clk_main_infra),
2204 .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
2205 .rst_lc_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2206 );
2207 rv_plic #(
2208 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
2209 ) u_rv_plic (
2210 // [41]: fatal_fault
2211 .alert_tx_o ( alert_tx[41:41] ),
2212 .alert_rx_i ( alert_rx[41:41] ),
2213
2214 // Inter-module signals
2215 .irq_o(rv_plic_irq),
2216 .irq_id_o(),
2217 .msip_o(rv_plic_msip),
2218 .tl_i(rv_plic_tl_req),
2219 .tl_o(rv_plic_tl_rsp),
2220 .intr_src_i (intr_vector),
2221
2222 // Clock and reset connections
2223 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2224 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2225 );
2226 aes #(
2227 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
2228 .AES192Enable(1'b1),
2229 .SecMasking(SecAesMasking),
2230 .SecSBoxImpl(SecAesSBoxImpl),
2231 .SecStartTriggerDelay(SecAesStartTriggerDelay),
2232 .SecAllowForcingMasks(SecAesAllowForcingMasks),
2233 .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding),
2234 .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed),
2235 .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm),
2236 .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm),
2237 .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
2238 .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm)
2239 ) u_aes (
2240 // [42]: recov_ctrl_update_err
2241 // [43]: fatal_fault
2242 .alert_tx_o ( alert_tx[43:42] ),
2243 .alert_rx_i ( alert_rx[43:42] ),
2244
2245 // Inter-module signals
2246 .idle_o(clkmgr_aon_idle[0]),
2247 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2248 .edn_o(edn0_edn_req[5]),
2249 .edn_i(edn0_edn_rsp[5]),
2250 .keymgr_key_i(keymgr_aes_key),
2251 .tl_i(aes_tl_req),
2252 .tl_o(aes_tl_rsp),
2253
2254 // Clock and reset connections
2255 .clk_i (clkmgr_aon_clocks.clk_main_aes),
2256 .clk_edn_i (clkmgr_aon_clocks.clk_main_aes),
2257 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2258 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2259 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2260 );
2261 hmac #(
2262 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44])
2263 ) u_hmac (
2264
2265 // Interrupt
2266 .intr_hmac_done_o (intr_hmac_hmac_done),
2267 .intr_fifo_empty_o (intr_hmac_fifo_empty),
2268 .intr_hmac_err_o (intr_hmac_hmac_err),
2269 // [44]: fatal_fault
2270 .alert_tx_o ( alert_tx[44:44] ),
2271 .alert_rx_i ( alert_rx[44:44] ),
2272
2273 // Inter-module signals
2274 .idle_o(clkmgr_aon_idle[1]),
2275 .tl_i(hmac_tl_req),
2276 .tl_o(hmac_tl_rsp),
2277
2278 // Clock and reset connections
2279 .clk_i (clkmgr_aon_clocks.clk_main_hmac),
2280 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2281 );
2282 kmac #(
2283 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
2284 .EnMasking(KmacEnMasking),
2285 .SwKeyMasked(KmacSwKeyMasked),
2286 .SecCmdDelay(SecKmacCmdDelay),
2287 .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg),
2288 .RndCnstLfsrSeed(RndCnstKmacLfsrSeed),
2289 .RndCnstLfsrPerm(RndCnstKmacLfsrPerm),
2290 .RndCnstBufferLfsrSeed(RndCnstKmacBufferLfsrSeed),
2291 .RndCnstMsgPerm(RndCnstKmacMsgPerm)
2292 ) u_kmac (
2293
2294 // Interrupt
2295 .intr_kmac_done_o (intr_kmac_kmac_done),
2296 .intr_fifo_empty_o (intr_kmac_fifo_empty),
2297 .intr_kmac_err_o (intr_kmac_kmac_err),
2298 // [45]: recov_operation_err
2299 // [46]: fatal_fault_err
2300 .alert_tx_o ( alert_tx[46:45] ),
2301 .alert_rx_i ( alert_rx[46:45] ),
2302
2303 // Inter-module signals
2304 .keymgr_key_i(keymgr_kmac_key),
2305 .app_i(kmac_app_req),
2306 .app_o(kmac_app_rsp),
2307 .entropy_o(edn0_edn_req[3]),
2308 .entropy_i(edn0_edn_rsp[3]),
2309 .idle_o(clkmgr_aon_idle[2]),
2310 .en_masking_o(kmac_en_masking),
2311 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2312 .tl_i(kmac_tl_req),
2313 .tl_o(kmac_tl_rsp),
2314
2315 // Clock and reset connections
2316 .clk_i (clkmgr_aon_clocks.clk_main_kmac),
2317 .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac),
2318 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2319 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2320 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2321 );
2322 otbn #(
2323 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
2324 .Stub(OtbnStub),
2325 .RegFile(OtbnRegFile),
2326 .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
2327 .SecMuteUrnd(SecOtbnMuteUrnd),
2328 .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart),
2329 .RndCnstOtbnKey(RndCnstOtbnOtbnKey),
2330 .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce)
2331 ) u_otbn (
2332
2333 // Interrupt
2334 .intr_done_o (intr_otbn_done),
2335 // [47]: fatal
2336 // [48]: recov
2337 .alert_tx_o ( alert_tx[48:47] ),
2338 .alert_rx_i ( alert_rx[48:47] ),
2339
2340 // Inter-module signals
2341 .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
2342 .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp),
2343 .edn_rnd_o(edn1_edn_req[0]),
2344 .edn_rnd_i(edn1_edn_rsp[0]),
2345 .edn_urnd_o(edn0_edn_req[6]),
2346 .edn_urnd_i(edn0_edn_rsp[6]),
2347 .idle_o(clkmgr_aon_idle[3]),
2348 .ram_cfg_i(ast_ram_1p_cfg),
2349 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2350 .lc_rma_req_i(lc_ctrl_lc_flash_rma_req),
2351 .lc_rma_ack_o(lc_ctrl_lc_flash_rma_ack[1]),
2352 .keymgr_key_i(keymgr_otbn_key),
2353 .tl_i(otbn_tl_req),
2354 .tl_o(otbn_tl_rsp),
2355
2356 // Clock and reset connections
2357 .clk_i (clkmgr_aon_clocks.clk_main_otbn),
2358 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
2359 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
2360 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2361 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2362 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2363 );
2364 keymgr #(
2365 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
2366 .UseOtpSeedsInsteadOfFlash(KeymgrUseOtpSeedsInsteadOfFlash),
2367 .KmacEnMasking(KeymgrKmacEnMasking),
2368 .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
2369 .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
2370 .RndCnstRandPerm(RndCnstKeymgrRandPerm),
2371 .RndCnstRevisionSeed(RndCnstKeymgrRevisionSeed),
2372 .RndCnstCreatorIdentitySeed(RndCnstKeymgrCreatorIdentitySeed),
2373 .RndCnstOwnerIntIdentitySeed(RndCnstKeymgrOwnerIntIdentitySeed),
2374 .RndCnstOwnerIdentitySeed(RndCnstKeymgrOwnerIdentitySeed),
2375 .RndCnstSoftOutputSeed(RndCnstKeymgrSoftOutputSeed),
2376 .RndCnstHardOutputSeed(RndCnstKeymgrHardOutputSeed),
2377 .RndCnstAesSeed(RndCnstKeymgrAesSeed),
2378 .RndCnstKmacSeed(RndCnstKeymgrKmacSeed),
2379 .RndCnstOtbnSeed(RndCnstKeymgrOtbnSeed),
2380 .RndCnstCdi(RndCnstKeymgrCdi),
2381 .RndCnstNoneSeed(RndCnstKeymgrNoneSeed)
2382 ) u_keymgr (
2383
2384 // Interrupt
2385 .intr_op_done_o (intr_keymgr_op_done),
2386 // [49]: recov_operation_err
2387 // [50]: fatal_fault_err
2388 .alert_tx_o ( alert_tx[50:49] ),
2389 .alert_rx_i ( alert_rx[50:49] ),
2390
2391 // Inter-module signals
2392 .edn_o(edn0_edn_req[0]),
2393 .edn_i(edn0_edn_rsp[0]),
2394 .aes_key_o(keymgr_aes_key),
2395 .kmac_key_o(keymgr_kmac_key),
2396 .otbn_key_o(keymgr_otbn_key),
2397 .kmac_data_o(kmac_app_req[0]),
2398 .kmac_data_i(kmac_app_rsp[0]),
2399 .otp_key_i(otp_ctrl_otp_keymgr_key),
2400 .otp_device_id_i(keymgr_otp_device_id),
2401 .flash_i(flash_ctrl_keymgr),
2402 .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en),
2403 .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div),
2404 .rom_digest_i(rom_ctrl_keymgr_data),
2405 .kmac_en_masking_i(kmac_en_masking),
2406 .tl_i(keymgr_tl_req),
2407 .tl_o(keymgr_tl_rsp),
2408
2409 // Clock and reset connections
2410 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2411 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
2412 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2413 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2414 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2415 );
2416 csrng #(
2417 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
2418 .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
2419 .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
2420 .SBoxImpl(CsrngSBoxImpl)
2421 ) u_csrng (
2422
2423 // Interrupt
2424 .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done),
2425 .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
2426 .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
2427 .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
2428 // [51]: recov_alert
2429 // [52]: fatal_alert
2430 .alert_tx_o ( alert_tx[52:51] ),
2431 .alert_rx_i ( alert_rx[52:51] ),
2432
2433 // Inter-module signals
2434 .csrng_cmd_i(csrng_csrng_cmd_req),
2435 .csrng_cmd_o(csrng_csrng_cmd_rsp),
2436 .entropy_src_hw_if_o(csrng_entropy_src_hw_if_req),
2437 .entropy_src_hw_if_i(csrng_entropy_src_hw_if_rsp),
2438 .cs_aes_halt_i(csrng_cs_aes_halt_req),
2439 .cs_aes_halt_o(csrng_cs_aes_halt_rsp),
2440 .otp_en_csrng_sw_app_read_i(csrng_otp_en_csrng_sw_app_read),
2441 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2442 .tl_i(csrng_tl_req),
2443 .tl_o(csrng_tl_rsp),
2444
2445 // Clock and reset connections
2446 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2447 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2448 );
2449 entropy_src #(
2450 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]),
2451 .EsFifoDepth(EntropySrcEsFifoDepth),
2452 .DistrFifoDepth(EntropySrcDistrFifoDepth),
2453 .Stub(EntropySrcStub)
2454 ) u_entropy_src (
2455
2456 // Interrupt
2457 .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid),
2458 .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
2459 .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
2460 .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
2461 // [53]: recov_alert
2462 // [54]: fatal_alert
2463 .alert_tx_o ( alert_tx[54:53] ),
2464 .alert_rx_i ( alert_rx[54:53] ),
2465
2466 // Inter-module signals
2467 .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
2468 .entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp),
2469 .cs_aes_halt_o(csrng_cs_aes_halt_req),
2470 .cs_aes_halt_i(csrng_cs_aes_halt_rsp),
2471 .entropy_src_rng_o(es_rng_req_o),
2472 .entropy_src_rng_i(es_rng_rsp_i),
2473 .entropy_src_xht_o(),
2474 .entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT),
2475 .otp_en_entropy_src_fw_read_i(prim_mubi_pkg::MuBi8True),
2476 .otp_en_entropy_src_fw_over_i(prim_mubi_pkg::MuBi8True),
2477 .rng_fips_o(es_rng_fips_o),
2478 .tl_i(entropy_src_tl_req),
2479 .tl_o(entropy_src_tl_rsp),
2480
2481 // Clock and reset connections
2482 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2483 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2484 );
2485 edn #(
2486 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55])
2487 ) u_edn0 (
2488
2489 // Interrupt
2490 .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
2491 .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
2492 // [55]: recov_alert
2493 // [56]: fatal_alert
2494 .alert_tx_o ( alert_tx[56:55] ),
2495 .alert_rx_i ( alert_rx[56:55] ),
2496
2497 // Inter-module signals
2498 .csrng_cmd_o(csrng_csrng_cmd_req[0]),
2499 .csrng_cmd_i(csrng_csrng_cmd_rsp[0]),
2500 .edn_i(edn0_edn_req),
2501 .edn_o(edn0_edn_rsp),
2502 .tl_i(edn0_tl_req),
2503 .tl_o(edn0_tl_rsp),
2504
2505 // Clock and reset connections
2506 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2507 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2508 );
2509 edn #(
2510 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57])
2511 ) u_edn1 (
2512
2513 // Interrupt
2514 .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
2515 .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
2516 // [57]: recov_alert
2517 // [58]: fatal_alert
2518 .alert_tx_o ( alert_tx[58:57] ),
2519 .alert_rx_i ( alert_rx[58:57] ),
2520
2521 // Inter-module signals
2522 .csrng_cmd_o(csrng_csrng_cmd_req[1]),
2523 .csrng_cmd_i(csrng_csrng_cmd_rsp[1]),
2524 .edn_i(edn1_edn_req),
2525 .edn_o(edn1_edn_rsp),
2526 .tl_i(edn1_tl_req),
2527 .tl_o(edn1_tl_rsp),
2528
2529 // Clock and reset connections
2530 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2531 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2532 );
2533 sram_ctrl #(
2534 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]),
2535 .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
2536 .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
2537 .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
2538 .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm),
2539 .MemSizeRam(131072),
2540 .InstrExec(SramCtrlMainInstrExec),
2541 .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf)
2542 ) u_sram_ctrl_main (
2543 // [59]: fatal_error
2544 .alert_tx_o ( alert_tx[59:59] ),
2545 .alert_rx_i ( alert_rx[59:59] ),
2546
2547 // Inter-module signals
2548 .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
2549 .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]),
2550 .cfg_i(ast_ram_1p_cfg),
2551 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2552 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2553 .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch),
2554 .regs_tl_i(sram_ctrl_main_regs_tl_req),
2555 .regs_tl_o(sram_ctrl_main_regs_tl_rsp),
2556 .ram_tl_i(sram_ctrl_main_ram_tl_req),
2557 .ram_tl_o(sram_ctrl_main_ram_tl_rsp),
2558
2559 // Clock and reset connections
2560 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2561 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2562 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2563 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2564 );
2565 rom_ctrl #(
2566 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]),
2567 .BootRomInitFile(RomCtrlBootRomInitFile),
2568 .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
2569 .RndCnstScrKey(RndCnstRomCtrlScrKey),
2570 .SecDisableScrambling(SecRomCtrlDisableScrambling),
2571 .MemSizeRom(32768)
2572 ) u_rom_ctrl (
2573 // [60]: fatal
2574 .alert_tx_o ( alert_tx[60:60] ),
2575 .alert_rx_i ( alert_rx[60:60] ),
2576
2577 // Inter-module signals
2578 .rom_cfg_i(ast_rom_cfg),
2579 .pwrmgr_data_o(rom_ctrl_pwrmgr_data),
2580 .keymgr_data_o(rom_ctrl_keymgr_data),
2581 .kmac_data_o(kmac_app_req[2]),
2582 .kmac_data_i(kmac_app_rsp[2]),
2583 .regs_tl_i(rom_ctrl_regs_tl_req),
2584 .regs_tl_o(rom_ctrl_regs_tl_rsp),
2585 .rom_tl_i(rom_ctrl_rom_tl_req),
2586 .rom_tl_o(rom_ctrl_rom_tl_rsp),
2587
2588 // Clock and reset connections
2589 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2590 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2591 );
2592 rv_core_ibex #(
2593 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]),
2594 .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
2595 .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
2596 .RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault),
2597 .RndCnstIbexNonceDefault(RndCnstRvCoreIbexIbexNonceDefault),
2598 .PMPEnable(RvCoreIbexPMPEnable),
2599 .PMPGranularity(RvCoreIbexPMPGranularity),
2600 .PMPNumRegions(RvCoreIbexPMPNumRegions),
2601 .MHPMCounterNum(RvCoreIbexMHPMCounterNum),
2602 .MHPMCounterWidth(RvCoreIbexMHPMCounterWidth),
2603 .RV32E(RvCoreIbexRV32E),
2604 .RV32M(RvCoreIbexRV32M),
2605 .RV32B(RvCoreIbexRV32B),
2606 .RegFile(RvCoreIbexRegFile),
2607 .BranchTargetALU(RvCoreIbexBranchTargetALU),
2608 .WritebackStage(RvCoreIbexWritebackStage),
2609 .ICache(RvCoreIbexICache),
2610 .ICacheECC(RvCoreIbexICacheECC),
2611 .ICacheScramble(RvCoreIbexICacheScramble),
2612 .BranchPredictor(RvCoreIbexBranchPredictor),
2613 .DbgTriggerEn(RvCoreIbexDbgTriggerEn),
2614 .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum),
2615 .SecureIbex(RvCoreIbexSecureIbex),
2616 .DmHaltAddr(RvCoreIbexDmHaltAddr),
2617 .DmExceptionAddr(RvCoreIbexDmExceptionAddr),
2618 .PipeLine(RvCoreIbexPipeLine)
2619 ) u_rv_core_ibex (
2620 // [61]: fatal_sw_err
2621 // [62]: recov_sw_err
2622 // [63]: fatal_hw_err
2623 // [64]: recov_hw_err
2624 .alert_tx_o ( alert_tx[64:61] ),
2625 .alert_rx_i ( alert_rx[64:61] ),
2626
2627 // Inter-module signals
2628 .rst_cpu_n_o(),
2629 .ram_cfg_i(ast_ram_1p_cfg),
2630 .hart_id_i(rv_core_ibex_hart_id),
2631 .boot_addr_i(rv_core_ibex_boot_addr),
2632 .irq_software_i(rv_plic_msip),
2633 .irq_timer_i(rv_core_ibex_irq_timer),
2634 .irq_external_i(rv_plic_irq),
2635 .esc_tx_i(alert_handler_esc_tx[0]),
2636 .esc_rx_o(alert_handler_esc_rx[0]),
2637 .debug_req_i(rv_dm_debug_req),
2638 .crash_dump_o(rv_core_ibex_crash_dump),
2639 .lc_cpu_en_i(lc_ctrl_lc_cpu_en),
2640 .pwrmgr_cpu_en_i(pwrmgr_aon_fetch_en),
2641 .pwrmgr_o(rv_core_ibex_pwrmgr),
2642 .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark),
2643 .edn_o(edn0_edn_req[7]),
2644 .edn_i(edn0_edn_rsp[7]),
2645 .icache_otp_key_o(otp_ctrl_sram_otp_key_req[2]),
2646 .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]),
2647 .fpga_info_i(fpga_info_i),
2648 .corei_tl_h_o(main_tl_rv_core_ibex__corei_req),
2649 .corei_tl_h_i(main_tl_rv_core_ibex__corei_rsp),
2650 .cored_tl_h_o(main_tl_rv_core_ibex__cored_req),
2651 .cored_tl_h_i(main_tl_rv_core_ibex__cored_rsp),
2652 .cfg_tl_d_i(rv_core_ibex_cfg_tl_d_req),
2653 .cfg_tl_d_o(rv_core_ibex_cfg_tl_d_rsp),
2654 .scanmode_i,
2655 .scan_rst_ni,
2656
2657 // Clock and reset connections
2658 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2659 .clk_edn_i (clkmgr_aon_clocks.clk_main_infra),
2660 .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
2661 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
2662 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2663 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2664 .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2665 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2666 );
2667 // interrupt assignments
2668 1/1 assign intr_vector = {
Tests: T1 T5 T6
2669 intr_edn1_edn_fatal_err, // IDs [185 +: 1]
2670 intr_edn1_edn_cmd_req_done, // IDs [184 +: 1]
2671 intr_edn0_edn_fatal_err, // IDs [183 +: 1]
2672 intr_edn0_edn_cmd_req_done, // IDs [182 +: 1]
2673 intr_entropy_src_es_fatal_err, // IDs [181 +: 1]
2674 intr_entropy_src_es_observe_fifo_ready, // IDs [180 +: 1]
2675 intr_entropy_src_es_health_test_failed, // IDs [179 +: 1]
2676 intr_entropy_src_es_entropy_valid, // IDs [178 +: 1]
2677 intr_csrng_cs_fatal_err, // IDs [177 +: 1]
2678 intr_csrng_cs_hw_inst_exc, // IDs [176 +: 1]
2679 intr_csrng_cs_entropy_req, // IDs [175 +: 1]
2680 intr_csrng_cs_cmd_req_done, // IDs [174 +: 1]
2681 intr_keymgr_op_done, // IDs [173 +: 1]
2682 intr_otbn_done, // IDs [172 +: 1]
2683 intr_kmac_kmac_err, // IDs [171 +: 1]
2684 intr_kmac_fifo_empty, // IDs [170 +: 1]
2685 intr_kmac_kmac_done, // IDs [169 +: 1]
2686 intr_hmac_hmac_err, // IDs [168 +: 1]
2687 intr_hmac_fifo_empty, // IDs [167 +: 1]
2688 intr_hmac_hmac_done, // IDs [166 +: 1]
2689 intr_flash_ctrl_corr_err, // IDs [165 +: 1]
2690 intr_flash_ctrl_op_done, // IDs [164 +: 1]
2691 intr_flash_ctrl_rd_lvl, // IDs [163 +: 1]
2692 intr_flash_ctrl_rd_full, // IDs [162 +: 1]
2693 intr_flash_ctrl_prog_lvl, // IDs [161 +: 1]
2694 intr_flash_ctrl_prog_empty, // IDs [160 +: 1]
2695 intr_sensor_ctrl_aon_init_status_change, // IDs [159 +: 1]
2696 intr_sensor_ctrl_aon_io_status_change, // IDs [158 +: 1]
2697 intr_aon_timer_aon_wdog_timer_bark, // IDs [157 +: 1]
2698 intr_aon_timer_aon_wkup_timer_expired, // IDs [156 +: 1]
2699 intr_adc_ctrl_aon_match_pending, // IDs [155 +: 1]
2700 intr_sysrst_ctrl_aon_event_detected, // IDs [154 +: 1]
2701 intr_pwrmgr_aon_wakeup, // IDs [153 +: 1]
2702 intr_usbdev_av_setup_empty, // IDs [152 +: 1]
2703 intr_usbdev_link_out_err, // IDs [151 +: 1]
2704 intr_usbdev_powered, // IDs [150 +: 1]
2705 intr_usbdev_frame, // IDs [149 +: 1]
2706 intr_usbdev_rx_bitstuff_err, // IDs [148 +: 1]
2707 intr_usbdev_rx_pid_err, // IDs [147 +: 1]
2708 intr_usbdev_rx_crc_err, // IDs [146 +: 1]
2709 intr_usbdev_link_in_err, // IDs [145 +: 1]
2710 intr_usbdev_av_overflow, // IDs [144 +: 1]
2711 intr_usbdev_rx_full, // IDs [143 +: 1]
2712 intr_usbdev_av_out_empty, // IDs [142 +: 1]
2713 intr_usbdev_link_resume, // IDs [141 +: 1]
2714 intr_usbdev_link_suspend, // IDs [140 +: 1]
2715 intr_usbdev_link_reset, // IDs [139 +: 1]
2716 intr_usbdev_host_lost, // IDs [138 +: 1]
2717 intr_usbdev_disconnected, // IDs [137 +: 1]
2718 intr_usbdev_pkt_sent, // IDs [136 +: 1]
2719 intr_usbdev_pkt_received, // IDs [135 +: 1]
2720 intr_spi_host1_spi_event, // IDs [134 +: 1]
2721 intr_spi_host1_error, // IDs [133 +: 1]
2722 intr_spi_host0_spi_event, // IDs [132 +: 1]
2723 intr_spi_host0_error, // IDs [131 +: 1]
2724 intr_alert_handler_classd, // IDs [130 +: 1]
2725 intr_alert_handler_classc, // IDs [129 +: 1]
2726 intr_alert_handler_classb, // IDs [128 +: 1]
2727 intr_alert_handler_classa, // IDs [127 +: 1]
2728 intr_otp_ctrl_otp_error, // IDs [126 +: 1]
2729 intr_otp_ctrl_otp_operation_done, // IDs [125 +: 1]
2730 intr_rv_timer_timer_expired_hart0_timer0, // IDs [124 +: 1]
2731 intr_pattgen_done_ch1, // IDs [123 +: 1]
2732 intr_pattgen_done_ch0, // IDs [122 +: 1]
2733 intr_i2c2_host_timeout, // IDs [121 +: 1]
2734 intr_i2c2_unexp_stop, // IDs [120 +: 1]
2735 intr_i2c2_acq_stretch, // IDs [119 +: 1]
2736 intr_i2c2_tx_threshold, // IDs [118 +: 1]
2737 intr_i2c2_tx_stretch, // IDs [117 +: 1]
2738 intr_i2c2_cmd_complete, // IDs [116 +: 1]
2739 intr_i2c2_sda_unstable, // IDs [115 +: 1]
2740 intr_i2c2_stretch_timeout, // IDs [114 +: 1]
2741 intr_i2c2_sda_interference, // IDs [113 +: 1]
2742 intr_i2c2_scl_interference, // IDs [112 +: 1]
2743 intr_i2c2_controller_halt, // IDs [111 +: 1]
2744 intr_i2c2_rx_overflow, // IDs [110 +: 1]
2745 intr_i2c2_acq_threshold, // IDs [109 +: 1]
2746 intr_i2c2_rx_threshold, // IDs [108 +: 1]
2747 intr_i2c2_fmt_threshold, // IDs [107 +: 1]
2748 intr_i2c1_host_timeout, // IDs [106 +: 1]
2749 intr_i2c1_unexp_stop, // IDs [105 +: 1]
2750 intr_i2c1_acq_stretch, // IDs [104 +: 1]
2751 intr_i2c1_tx_threshold, // IDs [103 +: 1]
2752 intr_i2c1_tx_stretch, // IDs [102 +: 1]
2753 intr_i2c1_cmd_complete, // IDs [101 +: 1]
2754 intr_i2c1_sda_unstable, // IDs [100 +: 1]
2755 intr_i2c1_stretch_timeout, // IDs [99 +: 1]
2756 intr_i2c1_sda_interference, // IDs [98 +: 1]
2757 intr_i2c1_scl_interference, // IDs [97 +: 1]
2758 intr_i2c1_controller_halt, // IDs [96 +: 1]
2759 intr_i2c1_rx_overflow, // IDs [95 +: 1]
2760 intr_i2c1_acq_threshold, // IDs [94 +: 1]
2761 intr_i2c1_rx_threshold, // IDs [93 +: 1]
2762 intr_i2c1_fmt_threshold, // IDs [92 +: 1]
2763 intr_i2c0_host_timeout, // IDs [91 +: 1]
2764 intr_i2c0_unexp_stop, // IDs [90 +: 1]
2765 intr_i2c0_acq_stretch, // IDs [89 +: 1]
2766 intr_i2c0_tx_threshold, // IDs [88 +: 1]
2767 intr_i2c0_tx_stretch, // IDs [87 +: 1]
2768 intr_i2c0_cmd_complete, // IDs [86 +: 1]
2769 intr_i2c0_sda_unstable, // IDs [85 +: 1]
2770 intr_i2c0_stretch_timeout, // IDs [84 +: 1]
2771 intr_i2c0_sda_interference, // IDs [83 +: 1]
2772 intr_i2c0_scl_interference, // IDs [82 +: 1]
2773 intr_i2c0_controller_halt, // IDs [81 +: 1]
2774 intr_i2c0_rx_overflow, // IDs [80 +: 1]
2775 intr_i2c0_acq_threshold, // IDs [79 +: 1]
2776 intr_i2c0_rx_threshold, // IDs [78 +: 1]
2777 intr_i2c0_fmt_threshold, // IDs [77 +: 1]
2778 intr_spi_device_tpm_rdfifo_drop, // IDs [76 +: 1]
2779 intr_spi_device_tpm_rdfifo_cmd_end, // IDs [75 +: 1]
2780 intr_spi_device_tpm_header_not_empty, // IDs [74 +: 1]
2781 intr_spi_device_readbuf_flip, // IDs [73 +: 1]
2782 intr_spi_device_readbuf_watermark, // IDs [72 +: 1]
2783 intr_spi_device_upload_payload_overflow, // IDs [71 +: 1]
2784 intr_spi_device_upload_payload_not_empty, // IDs [70 +: 1]
2785 intr_spi_device_upload_cmdfifo_not_empty, // IDs [69 +: 1]
2786 intr_gpio_gpio, // IDs [37 +: 32]
2787 intr_uart3_tx_empty, // IDs [36 +: 1]
2788 intr_uart3_rx_parity_err, // IDs [35 +: 1]
2789 intr_uart3_rx_timeout, // IDs [34 +: 1]
2790 intr_uart3_rx_break_err, // IDs [33 +: 1]
2791 intr_uart3_rx_frame_err, // IDs [32 +: 1]
2792 intr_uart3_rx_overflow, // IDs [31 +: 1]
2793 intr_uart3_tx_done, // IDs [30 +: 1]
2794 intr_uart3_rx_watermark, // IDs [29 +: 1]
2795 intr_uart3_tx_watermark, // IDs [28 +: 1]
2796 intr_uart2_tx_empty, // IDs [27 +: 1]
2797 intr_uart2_rx_parity_err, // IDs [26 +: 1]
2798 intr_uart2_rx_timeout, // IDs [25 +: 1]
2799 intr_uart2_rx_break_err, // IDs [24 +: 1]
2800 intr_uart2_rx_frame_err, // IDs [23 +: 1]
2801 intr_uart2_rx_overflow, // IDs [22 +: 1]
2802 intr_uart2_tx_done, // IDs [21 +: 1]
2803 intr_uart2_rx_watermark, // IDs [20 +: 1]
2804 intr_uart2_tx_watermark, // IDs [19 +: 1]
2805 intr_uart1_tx_empty, // IDs [18 +: 1]
2806 intr_uart1_rx_parity_err, // IDs [17 +: 1]
2807 intr_uart1_rx_timeout, // IDs [16 +: 1]
2808 intr_uart1_rx_break_err, // IDs [15 +: 1]
2809 intr_uart1_rx_frame_err, // IDs [14 +: 1]
2810 intr_uart1_rx_overflow, // IDs [13 +: 1]
2811 intr_uart1_tx_done, // IDs [12 +: 1]
2812 intr_uart1_rx_watermark, // IDs [11 +: 1]
2813 intr_uart1_tx_watermark, // IDs [10 +: 1]
2814 intr_uart0_tx_empty, // IDs [9 +: 1]
2815 intr_uart0_rx_parity_err, // IDs [8 +: 1]
2816 intr_uart0_rx_timeout, // IDs [7 +: 1]
2817 intr_uart0_rx_break_err, // IDs [6 +: 1]
2818 intr_uart0_rx_frame_err, // IDs [5 +: 1]
2819 intr_uart0_rx_overflow, // IDs [4 +: 1]
2820 intr_uart0_tx_done, // IDs [3 +: 1]
2821 intr_uart0_rx_watermark, // IDs [2 +: 1]
2822 intr_uart0_tx_watermark, // IDs [1 +: 1]
2823 1'b 0 // ID [0 +: 1] is a special case and tied to zero.
2824 };
2825
2826 // TL-UL Crossbar
2827 xbar_main u_xbar_main (
2828 .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
2829 .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra),
2830 .clk_usb_i (clkmgr_aon_clocks.clk_usb_infra),
2831 .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra),
2832 .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_div2_infra),
2833 .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2834 .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2835 .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::Domain0Sel]),
2836 .rst_spi_host0_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
2837 .rst_spi_host1_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::Domain0Sel]),
2838
2839 // port: tl_rv_core_ibex__corei
2840 .tl_rv_core_ibex__corei_i(main_tl_rv_core_ibex__corei_req),
2841 .tl_rv_core_ibex__corei_o(main_tl_rv_core_ibex__corei_rsp),
2842
2843 // port: tl_rv_core_ibex__cored
2844 .tl_rv_core_ibex__cored_i(main_tl_rv_core_ibex__cored_req),
2845 .tl_rv_core_ibex__cored_o(main_tl_rv_core_ibex__cored_rsp),
2846
2847 // port: tl_rv_dm__sba
2848 .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req),
2849 .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp),
2850
2851 // port: tl_rv_dm__regs
2852 .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req),
2853 .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp),
2854
2855 // port: tl_rv_dm__mem
2856 .tl_rv_dm__mem_o(rv_dm_mem_tl_d_req),
2857 .tl_rv_dm__mem_i(rv_dm_mem_tl_d_rsp),
2858
2859 // port: tl_rom_ctrl__rom
2860 .tl_rom_ctrl__rom_o(rom_ctrl_rom_tl_req),
2861 .tl_rom_ctrl__rom_i(rom_ctrl_rom_tl_rsp),
2862
2863 // port: tl_rom_ctrl__regs
2864 .tl_rom_ctrl__regs_o(rom_ctrl_regs_tl_req),
2865 .tl_rom_ctrl__regs_i(rom_ctrl_regs_tl_rsp),
2866
2867 // port: tl_peri
2868 .tl_peri_o(main_tl_peri_req),
2869 .tl_peri_i(main_tl_peri_rsp),
2870
2871 // port: tl_spi_host0
2872 .tl_spi_host0_o(spi_host0_tl_req),
2873 .tl_spi_host0_i(spi_host0_tl_rsp),
2874
2875 // port: tl_spi_host1
2876 .tl_spi_host1_o(spi_host1_tl_req),
2877 .tl_spi_host1_i(spi_host1_tl_rsp),
2878
2879 // port: tl_usbdev
2880 .tl_usbdev_o(usbdev_tl_req),
2881 .tl_usbdev_i(usbdev_tl_rsp),
2882
2883 // port: tl_flash_ctrl__core
2884 .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req),
2885 .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp),
2886
2887 // port: tl_flash_ctrl__prim
2888 .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req),
2889 .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp),
2890
2891 // port: tl_flash_ctrl__mem
2892 .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req),
2893 .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp),
2894
2895 // port: tl_hmac
2896 .tl_hmac_o(hmac_tl_req),
2897 .tl_hmac_i(hmac_tl_rsp),
2898
2899 // port: tl_kmac
2900 .tl_kmac_o(kmac_tl_req),
2901 .tl_kmac_i(kmac_tl_rsp),
2902
2903 // port: tl_aes
2904 .tl_aes_o(aes_tl_req),
2905 .tl_aes_i(aes_tl_rsp),
2906
2907 // port: tl_entropy_src
2908 .tl_entropy_src_o(entropy_src_tl_req),
2909 .tl_entropy_src_i(entropy_src_tl_rsp),
2910
2911 // port: tl_csrng
2912 .tl_csrng_o(csrng_tl_req),
2913 .tl_csrng_i(csrng_tl_rsp),
2914
2915 // port: tl_edn0
2916 .tl_edn0_o(edn0_tl_req),
2917 .tl_edn0_i(edn0_tl_rsp),
2918
2919 // port: tl_edn1
2920 .tl_edn1_o(edn1_tl_req),
2921 .tl_edn1_i(edn1_tl_rsp),
2922
2923 // port: tl_rv_plic
2924 .tl_rv_plic_o(rv_plic_tl_req),
2925 .tl_rv_plic_i(rv_plic_tl_rsp),
2926
2927 // port: tl_otbn
2928 .tl_otbn_o(otbn_tl_req),
2929 .tl_otbn_i(otbn_tl_rsp),
2930
2931 // port: tl_keymgr
2932 .tl_keymgr_o(keymgr_tl_req),
2933 .tl_keymgr_i(keymgr_tl_rsp),
2934
2935 // port: tl_rv_core_ibex__cfg
2936 .tl_rv_core_ibex__cfg_o(rv_core_ibex_cfg_tl_d_req),
2937 .tl_rv_core_ibex__cfg_i(rv_core_ibex_cfg_tl_d_rsp),
2938
2939 // port: tl_sram_ctrl_main__regs
2940 .tl_sram_ctrl_main__regs_o(sram_ctrl_main_regs_tl_req),
2941 .tl_sram_ctrl_main__regs_i(sram_ctrl_main_regs_tl_rsp),
2942
2943 // port: tl_sram_ctrl_main__ram
2944 .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req),
2945 .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp),
2946
2947
2948 .scanmode_i
2949 );
2950 xbar_peri u_xbar_peri (
2951 .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
2952 .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2953
2954 // port: tl_main
2955 .tl_main_i(main_tl_peri_req),
2956 .tl_main_o(main_tl_peri_rsp),
2957
2958 // port: tl_uart0
2959 .tl_uart0_o(uart0_tl_req),
2960 .tl_uart0_i(uart0_tl_rsp),
2961
2962 // port: tl_uart1
2963 .tl_uart1_o(uart1_tl_req),
2964 .tl_uart1_i(uart1_tl_rsp),
2965
2966 // port: tl_uart2
2967 .tl_uart2_o(uart2_tl_req),
2968 .tl_uart2_i(uart2_tl_rsp),
2969
2970 // port: tl_uart3
2971 .tl_uart3_o(uart3_tl_req),
2972 .tl_uart3_i(uart3_tl_rsp),
2973
2974 // port: tl_i2c0
2975 .tl_i2c0_o(i2c0_tl_req),
2976 .tl_i2c0_i(i2c0_tl_rsp),
2977
2978 // port: tl_i2c1
2979 .tl_i2c1_o(i2c1_tl_req),
2980 .tl_i2c1_i(i2c1_tl_rsp),
2981
2982 // port: tl_i2c2
2983 .tl_i2c2_o(i2c2_tl_req),
2984 .tl_i2c2_i(i2c2_tl_rsp),
2985
2986 // port: tl_pattgen
2987 .tl_pattgen_o(pattgen_tl_req),
2988 .tl_pattgen_i(pattgen_tl_rsp),
2989
2990 // port: tl_pwm_aon
2991 .tl_pwm_aon_o(pwm_aon_tl_req),
2992 .tl_pwm_aon_i(pwm_aon_tl_rsp),
2993
2994 // port: tl_gpio
2995 .tl_gpio_o(gpio_tl_req),
2996 .tl_gpio_i(gpio_tl_rsp),
2997
2998 // port: tl_spi_device
2999 .tl_spi_device_o(spi_device_tl_req),
3000 .tl_spi_device_i(spi_device_tl_rsp),
3001
3002 // port: tl_rv_timer
3003 .tl_rv_timer_o(rv_timer_tl_req),
3004 .tl_rv_timer_i(rv_timer_tl_rsp),
3005
3006 // port: tl_pwrmgr_aon
3007 .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req),
3008 .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp),
3009
3010 // port: tl_rstmgr_aon
3011 .tl_rstmgr_aon_o(rstmgr_aon_tl_req),
3012 .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp),
3013
3014 // port: tl_clkmgr_aon
3015 .tl_clkmgr_aon_o(clkmgr_aon_tl_req),
3016 .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp),
3017
3018 // port: tl_pinmux_aon
3019 .tl_pinmux_aon_o(pinmux_aon_tl_req),
3020 .tl_pinmux_aon_i(pinmux_aon_tl_rsp),
3021
3022 // port: tl_otp_ctrl__core
3023 .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req),
3024 .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp),
3025
3026 // port: tl_otp_ctrl__prim
3027 .tl_otp_ctrl__prim_o(otp_ctrl_prim_tl_req),
3028 .tl_otp_ctrl__prim_i(otp_ctrl_prim_tl_rsp),
3029
3030 // port: tl_lc_ctrl
3031 .tl_lc_ctrl_o(lc_ctrl_tl_req),
3032 .tl_lc_ctrl_i(lc_ctrl_tl_rsp),
3033
3034 // port: tl_sensor_ctrl_aon
3035 .tl_sensor_ctrl_aon_o(sensor_ctrl_aon_tl_req),
3036 .tl_sensor_ctrl_aon_i(sensor_ctrl_aon_tl_rsp),
3037
3038 // port: tl_alert_handler
3039 .tl_alert_handler_o(alert_handler_tl_req),
3040 .tl_alert_handler_i(alert_handler_tl_rsp),
3041
3042 // port: tl_sram_ctrl_ret_aon__regs
3043 .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req),
3044 .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp),
3045
3046 // port: tl_sram_ctrl_ret_aon__ram
3047 .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req),
3048 .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp),
3049
3050 // port: tl_aon_timer_aon
3051 .tl_aon_timer_aon_o(aon_timer_aon_tl_req),
3052 .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp),
3053
3054 // port: tl_sysrst_ctrl_aon
3055 .tl_sysrst_ctrl_aon_o(sysrst_ctrl_aon_tl_req),
3056 .tl_sysrst_ctrl_aon_i(sysrst_ctrl_aon_tl_rsp),
3057
3058 // port: tl_adc_ctrl_aon
3059 .tl_adc_ctrl_aon_o(adc_ctrl_aon_tl_req),
3060 .tl_adc_ctrl_aon_i(adc_ctrl_aon_tl_rsp),
3061
3062 // port: tl_ast
3063 .tl_ast_o(ast_tl_req_o),
3064 .tl_ast_i(ast_tl_rsp_i),
3065
3066
3067 .scanmode_i
3068 );
3069
3070 // Pinmux connections
3071 // All muxed inputs
3072 1/1 assign cio_gpio_gpio_p2d[0] = mio_p2d[MioInGpioGpio0];
Tests: T6 T31 T43
3073 1/1 assign cio_gpio_gpio_p2d[1] = mio_p2d[MioInGpioGpio1];
Tests: T29 T31 T43
3074 1/1 assign cio_gpio_gpio_p2d[2] = mio_p2d[MioInGpioGpio2];
Tests: T29 T31 T43
3075 1/1 assign cio_gpio_gpio_p2d[3] = mio_p2d[MioInGpioGpio3];
Tests: T29 T31 T43
3076 1/1 assign cio_gpio_gpio_p2d[4] = mio_p2d[MioInGpioGpio4];
Tests: T29 T31 T43
3077 1/1 assign cio_gpio_gpio_p2d[5] = mio_p2d[MioInGpioGpio5];
Tests: T29 T31 T43
3078 1/1 assign cio_gpio_gpio_p2d[6] = mio_p2d[MioInGpioGpio6];
Tests: T29 T31 T43
3079 1/1 assign cio_gpio_gpio_p2d[7] = mio_p2d[MioInGpioGpio7];
Tests: T29 T31 T43
3080 1/1 assign cio_gpio_gpio_p2d[8] = mio_p2d[MioInGpioGpio8];
Tests: T29 T31 T43
3081 1/1 assign cio_gpio_gpio_p2d[9] = mio_p2d[MioInGpioGpio9];
Tests: T31 T43 T44
3082 1/1 assign cio_gpio_gpio_p2d[10] = mio_p2d[MioInGpioGpio10];
Tests: T31 T43 T44
3083 1/1 assign cio_gpio_gpio_p2d[11] = mio_p2d[MioInGpioGpio11];
Tests: T31 T43 T44
3084 1/1 assign cio_gpio_gpio_p2d[12] = mio_p2d[MioInGpioGpio12];
Tests: T31 T43 T44
3085 1/1 assign cio_gpio_gpio_p2d[13] = mio_p2d[MioInGpioGpio13];
Tests: T31 T43 T44
3086 1/1 assign cio_gpio_gpio_p2d[14] = mio_p2d[MioInGpioGpio14];
Tests: T31 T43 T44
3087 1/1 assign cio_gpio_gpio_p2d[15] = mio_p2d[MioInGpioGpio15];
Tests: T31 T43 T44
3088 1/1 assign cio_gpio_gpio_p2d[16] = mio_p2d[MioInGpioGpio16];
Tests: T31 T43 T44
3089 1/1 assign cio_gpio_gpio_p2d[17] = mio_p2d[MioInGpioGpio17];
Tests: T31 T43 T44
3090 1/1 assign cio_gpio_gpio_p2d[18] = mio_p2d[MioInGpioGpio18];
Tests: T31 T43 T44
3091 1/1 assign cio_gpio_gpio_p2d[19] = mio_p2d[MioInGpioGpio19];
Tests: T31 T43 T44
3092 1/1 assign cio_gpio_gpio_p2d[20] = mio_p2d[MioInGpioGpio20];
Tests: T31 T43 T44
3093 1/1 assign cio_gpio_gpio_p2d[21] = mio_p2d[MioInGpioGpio21];
Tests: T31 T43 T44
3094 1/1 assign cio_gpio_gpio_p2d[22] = mio_p2d[MioInGpioGpio22];
Tests: T1 T2 T3
3095 1/1 assign cio_gpio_gpio_p2d[23] = mio_p2d[MioInGpioGpio23];
Tests: T1 T2 T3
3096 1/1 assign cio_gpio_gpio_p2d[24] = mio_p2d[MioInGpioGpio24];
Tests: T1 T2 T3
3097 1/1 assign cio_gpio_gpio_p2d[25] = mio_p2d[MioInGpioGpio25];
Tests: T31 T43 T44
3098 1/1 assign cio_gpio_gpio_p2d[26] = mio_p2d[MioInGpioGpio26];
Tests: T31 T43 T44
3099 1/1 assign cio_gpio_gpio_p2d[27] = mio_p2d[MioInGpioGpio27];
Tests: T31 T43 T44
3100 1/1 assign cio_gpio_gpio_p2d[28] = mio_p2d[MioInGpioGpio28];
Tests: T31 T43 T44
3101 1/1 assign cio_gpio_gpio_p2d[29] = mio_p2d[MioInGpioGpio29];
Tests: T31 T43 T44
3102 1/1 assign cio_gpio_gpio_p2d[30] = mio_p2d[MioInGpioGpio30];
Tests: T31 T43 T44
3103 1/1 assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31];
Tests: T31 T43 T44
3104 1/1 assign cio_i2c0_sda_p2d = mio_p2d[MioInI2c0Sda];
Tests: T61 T12 T62
3105 1/1 assign cio_i2c0_scl_p2d = mio_p2d[MioInI2c0Scl];
Tests: T61 T12 T62
3106 1/1 assign cio_i2c1_sda_p2d = mio_p2d[MioInI2c1Sda];
Tests: T33 T63 T12
3107 1/1 assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl];
Tests: T33 T63 T12
3108 1/1 assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda];
Tests: T64 T12 T65
3109 1/1 assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl];
Tests: T64 T12 T65
3110 1/1 assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0];
Tests: T28 T12 T50
3111 1/1 assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1];
Tests: T28 T12 T50
3112 1/1 assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2];
Tests: T28 T12 T50
3113 1/1 assign cio_spi_host1_sd_p2d[3] = mio_p2d[MioInSpiHost1Sd3];
Tests: T28 T10 T11
3114 1/1 assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx];
Tests: T1 T2 T3
3115 1/1 assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx];
Tests: T1 T2 T3
3116 1/1 assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx];
Tests: T32 T66 T67
3117 1/1 assign cio_uart3_rx_p2d = mio_p2d[MioInUart3Rx];
Tests: T30 T68 T12
3118 1/1 assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb];
Tests: T13 T52 T53
3119 1/1 assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck];
Tests: T22 T23 T24
3120 1/1 assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms];
Tests: T22 T23 T24
3121 1/1 assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi];
Tests: T22 T23 T24
3122 1/1 assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent];
Tests: T70 T71 T15
3123 1/1 assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In];
Tests: T72 T14 T70
3124 1/1 assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In];
Tests: T14 T70 T71
3125 1/1 assign cio_sysrst_ctrl_aon_key2_in_p2d = mio_p2d[MioInSysrstCtrlAonKey2In];
Tests: T14 T70 T71
3126 1/1 assign cio_sysrst_ctrl_aon_pwrb_in_p2d = mio_p2d[MioInSysrstCtrlAonPwrbIn];
Tests: T14 T70 T71
3127 1/1 assign cio_sysrst_ctrl_aon_lid_open_p2d = mio_p2d[MioInSysrstCtrlAonLidOpen];
Tests: T70 T17 T15
3128 1/1 assign cio_usbdev_sense_p2d = mio_p2d[MioInUsbdevSense];
Tests: T4 T35 T8
3129
3130 // All muxed outputs
3131 1/1 assign mio_d2p[MioOutGpioGpio0] = cio_gpio_gpio_d2p[0];
Tests: T29 T31 T96
3132 1/1 assign mio_d2p[MioOutGpioGpio1] = cio_gpio_gpio_d2p[1];
Tests: T29 T31 T96
3133 1/1 assign mio_d2p[MioOutGpioGpio2] = cio_gpio_gpio_d2p[2];
Tests: T29 T31 T75
3134 1/1 assign mio_d2p[MioOutGpioGpio3] = cio_gpio_gpio_d2p[3];
Tests: T29 T31 T43
3135 1/1 assign mio_d2p[MioOutGpioGpio4] = cio_gpio_gpio_d2p[4];
Tests: T29 T31 T96
3136 1/1 assign mio_d2p[MioOutGpioGpio5] = cio_gpio_gpio_d2p[5];
Tests: T29 T31 T43
3137 1/1 assign mio_d2p[MioOutGpioGpio6] = cio_gpio_gpio_d2p[6];
Tests: T29 T31 T96
3138 1/1 assign mio_d2p[MioOutGpioGpio7] = cio_gpio_gpio_d2p[7];
Tests: T29 T31 T96
3139 1/1 assign mio_d2p[MioOutGpioGpio8] = cio_gpio_gpio_d2p[8];
Tests: T31 T96 T43
3140 1/1 assign mio_d2p[MioOutGpioGpio9] = cio_gpio_gpio_d2p[9];
Tests: T31 T96 T43
3141 1/1 assign mio_d2p[MioOutGpioGpio10] = cio_gpio_gpio_d2p[10];
Tests: T31 T43 T44
3142 1/1 assign mio_d2p[MioOutGpioGpio11] = cio_gpio_gpio_d2p[11];
Tests: T31 T43 T44
3143 1/1 assign mio_d2p[MioOutGpioGpio12] = cio_gpio_gpio_d2p[12];
Tests: T31 T43 T44
3144 1/1 assign mio_d2p[MioOutGpioGpio13] = cio_gpio_gpio_d2p[13];
Tests: T31 T96 T43
3145 1/1 assign mio_d2p[MioOutGpioGpio14] = cio_gpio_gpio_d2p[14];
Tests: T31 T96 T43
3146 1/1 assign mio_d2p[MioOutGpioGpio15] = cio_gpio_gpio_d2p[15];
Tests: T31 T43 T44
3147 1/1 assign mio_d2p[MioOutGpioGpio16] = cio_gpio_gpio_d2p[16];
Tests: T31 T96 T43
3148 1/1 assign mio_d2p[MioOutGpioGpio17] = cio_gpio_gpio_d2p[17];
Tests: T31 T96 T43
3149 1/1 assign mio_d2p[MioOutGpioGpio18] = cio_gpio_gpio_d2p[18];
Tests: T31 T96 T43
3150 1/1 assign mio_d2p[MioOutGpioGpio19] = cio_gpio_gpio_d2p[19];
Tests: T31 T43 T44
3151 1/1 assign mio_d2p[MioOutGpioGpio20] = cio_gpio_gpio_d2p[20];
Tests: T31 T43 T44
3152 1/1 assign mio_d2p[MioOutGpioGpio21] = cio_gpio_gpio_d2p[21];
Tests: T31 T43 T44
3153 1/1 assign mio_d2p[MioOutGpioGpio22] = cio_gpio_gpio_d2p[22];
Tests: T31 T43 T44
3154 1/1 assign mio_d2p[MioOutGpioGpio23] = cio_gpio_gpio_d2p[23];
Tests: T31 T96 T43
3155 1/1 assign mio_d2p[MioOutGpioGpio24] = cio_gpio_gpio_d2p[24];
Tests: T31 T96 T43
3156 1/1 assign mio_d2p[MioOutGpioGpio25] = cio_gpio_gpio_d2p[25];
Tests: T31 T43 T44
3157 1/1 assign mio_d2p[MioOutGpioGpio26] = cio_gpio_gpio_d2p[26];
Tests: T31 T43 T44
3158 1/1 assign mio_d2p[MioOutGpioGpio27] = cio_gpio_gpio_d2p[27];
Tests: T31 T96 T43
3159 1/1 assign mio_d2p[MioOutGpioGpio28] = cio_gpio_gpio_d2p[28];
Tests: T31 T96 T43
3160 1/1 assign mio_d2p[MioOutGpioGpio29] = cio_gpio_gpio_d2p[29];
Tests: T31 T96 T43
3161 1/1 assign mio_d2p[MioOutGpioGpio30] = cio_gpio_gpio_d2p[30];
Tests: T31 T96 T43
3162 1/1 assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31];
Tests: T31 T96 T43
3163 unreachable assign mio_d2p[MioOutI2c0Sda] = cio_i2c0_sda_d2p;
3164 unreachable assign mio_d2p[MioOutI2c0Scl] = cio_i2c0_scl_d2p;
3165 unreachable assign mio_d2p[MioOutI2c1Sda] = cio_i2c1_sda_d2p;
3166 unreachable assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p;
3167 unreachable assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p;
3168 unreachable assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p;
3169 1/1 assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0];
Tests: T28 T50 T51
3170 1/1 assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1];
Tests: T12 T171 T172
3171 0/1 ==> assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2];
3172 1/1 assign mio_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_d2p[3];
Tests: T12 T171 T172
3173 1/1 assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p;
Tests: T173 T57 T58
3174 1/1 assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p;
Tests: T73 T174 T175
3175 1/1 assign mio_d2p[MioOutUart2Tx] = cio_uart2_tx_d2p;
Tests: T32 T66 T67
3176 1/1 assign mio_d2p[MioOutUart3Tx] = cio_uart3_tx_d2p;
Tests: T30 T68 T96
3177 1/1 assign mio_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_d2p;
Tests: T12 T176 T177
3178 1/1 assign mio_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_d2p;
Tests: T12 T176 T177
3179 1/1 assign mio_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_d2p;
Tests: T5 T12 T171
3180 1/1 assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p;
Tests: T5 T12 T171
3181 1/1 assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p;
Tests: T28 T12 T50
3182 1/1 assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p;
Tests: T28 T12 T50
3183 0/1 ==> assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p;
3184 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_d2p[0];
3185 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_d2p[1];
3186 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_d2p[2];
3187 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_d2p[3];
3188 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_d2p[4];
3189 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_d2p[5];
3190 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_d2p[6];
3191 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_d2p[7];
3192 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_d2p[8];
3193 1/1 assign mio_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_d2p[0];
Tests: T39 T75 T178
3194 1/1 assign mio_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_d2p[1];
Tests: T39 T75 T178
3195 1/1 assign mio_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_d2p[2];
Tests: T39 T75 T178
3196 1/1 assign mio_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_d2p[3];
Tests: T39 T75 T178
3197 1/1 assign mio_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_d2p[4];
Tests: T39 T75 T178
3198 1/1 assign mio_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_d2p[5];
Tests: T39 T75 T178
3199 0/1 ==> assign mio_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_d2p[0];
3200 1/1 assign mio_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_d2p;
Tests: T72 T14 T179
3201 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_d2p;
Tests: T72 T14 T70
3202 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_d2p;
Tests: T14 T70 T71
3203 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_d2p;
Tests: T14 T70 T71
3204 1/1 assign mio_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_d2p;
Tests: T14 T70 T71
3205 1/1 assign mio_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_d2p;
Tests: T14 T17 T15
3206
3207 // All muxed output enables
3208 1/1 assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0];
Tests: T6 T29 T31
3209 1/1 assign mio_en_d2p[MioOutGpioGpio1] = cio_gpio_gpio_en_d2p[1];
Tests: T29 T31 T43
3210 1/1 assign mio_en_d2p[MioOutGpioGpio2] = cio_gpio_gpio_en_d2p[2];
Tests: T29 T31 T75
3211 1/1 assign mio_en_d2p[MioOutGpioGpio3] = cio_gpio_gpio_en_d2p[3];
Tests: T29 T31 T43
3212 1/1 assign mio_en_d2p[MioOutGpioGpio4] = cio_gpio_gpio_en_d2p[4];
Tests: T29 T31 T96
3213 1/1 assign mio_en_d2p[MioOutGpioGpio5] = cio_gpio_gpio_en_d2p[5];
Tests: T29 T31 T96
3214 1/1 assign mio_en_d2p[MioOutGpioGpio6] = cio_gpio_gpio_en_d2p[6];
Tests: T29 T31 T96
3215 1/1 assign mio_en_d2p[MioOutGpioGpio7] = cio_gpio_gpio_en_d2p[7];
Tests: T29 T31 T96
3216 1/1 assign mio_en_d2p[MioOutGpioGpio8] = cio_gpio_gpio_en_d2p[8];
Tests: T31 T43 T44
3217 1/1 assign mio_en_d2p[MioOutGpioGpio9] = cio_gpio_gpio_en_d2p[9];
Tests: T31 T43 T44
3218 1/1 assign mio_en_d2p[MioOutGpioGpio10] = cio_gpio_gpio_en_d2p[10];
Tests: T31 T96 T43
3219 1/1 assign mio_en_d2p[MioOutGpioGpio11] = cio_gpio_gpio_en_d2p[11];
Tests: T31 T43 T44
3220 1/1 assign mio_en_d2p[MioOutGpioGpio12] = cio_gpio_gpio_en_d2p[12];
Tests: T31 T96 T43
3221 1/1 assign mio_en_d2p[MioOutGpioGpio13] = cio_gpio_gpio_en_d2p[13];
Tests: T31 T96 T43
3222 1/1 assign mio_en_d2p[MioOutGpioGpio14] = cio_gpio_gpio_en_d2p[14];
Tests: T31 T96 T43
3223 1/1 assign mio_en_d2p[MioOutGpioGpio15] = cio_gpio_gpio_en_d2p[15];
Tests: T31 T96 T43
3224 1/1 assign mio_en_d2p[MioOutGpioGpio16] = cio_gpio_gpio_en_d2p[16];
Tests: T31 T43 T44
3225 1/1 assign mio_en_d2p[MioOutGpioGpio17] = cio_gpio_gpio_en_d2p[17];
Tests: T31 T96 T43
3226 1/1 assign mio_en_d2p[MioOutGpioGpio18] = cio_gpio_gpio_en_d2p[18];
Tests: T31 T43 T44
3227 1/1 assign mio_en_d2p[MioOutGpioGpio19] = cio_gpio_gpio_en_d2p[19];
Tests: T31 T96 T43
3228 1/1 assign mio_en_d2p[MioOutGpioGpio20] = cio_gpio_gpio_en_d2p[20];
Tests: T31 T43 T44
3229 1/1 assign mio_en_d2p[MioOutGpioGpio21] = cio_gpio_gpio_en_d2p[21];
Tests: T31 T43 T44
3230 1/1 assign mio_en_d2p[MioOutGpioGpio22] = cio_gpio_gpio_en_d2p[22];
Tests: T31 T43 T44
3231 1/1 assign mio_en_d2p[MioOutGpioGpio23] = cio_gpio_gpio_en_d2p[23];
Tests: T31 T43 T44
3232 1/1 assign mio_en_d2p[MioOutGpioGpio24] = cio_gpio_gpio_en_d2p[24];
Tests: T31 T96 T43
3233 1/1 assign mio_en_d2p[MioOutGpioGpio25] = cio_gpio_gpio_en_d2p[25];
Tests: T31 T96 T43
3234 1/1 assign mio_en_d2p[MioOutGpioGpio26] = cio_gpio_gpio_en_d2p[26];
Tests: T31 T96 T43
3235 1/1 assign mio_en_d2p[MioOutGpioGpio27] = cio_gpio_gpio_en_d2p[27];
Tests: T31 T43 T44
3236 1/1 assign mio_en_d2p[MioOutGpioGpio28] = cio_gpio_gpio_en_d2p[28];
Tests: T31 T96 T43
3237 1/1 assign mio_en_d2p[MioOutGpioGpio29] = cio_gpio_gpio_en_d2p[29];
Tests: T31 T96 T43
3238 1/1 assign mio_en_d2p[MioOutGpioGpio30] = cio_gpio_gpio_en_d2p[30];
Tests: T31 T43 T44
3239 1/1 assign mio_en_d2p[MioOutGpioGpio31] = cio_gpio_gpio_en_d2p[31];
Tests: T31 T96 T43
3240 1/1 assign mio_en_d2p[MioOutI2c0Sda] = cio_i2c0_sda_en_d2p;
Tests: T61 T12 T62
3241 1/1 assign mio_en_d2p[MioOutI2c0Scl] = cio_i2c0_scl_en_d2p;
Tests: T61 T12 T62
3242 1/1 assign mio_en_d2p[MioOutI2c1Sda] = cio_i2c1_sda_en_d2p;
Tests: T33 T63 T96
3243 1/1 assign mio_en_d2p[MioOutI2c1Scl] = cio_i2c1_scl_en_d2p;
Tests: T63 T96 T12
3244 1/1 assign mio_en_d2p[MioOutI2c2Sda] = cio_i2c2_sda_en_d2p;
Tests: T64 T96 T12
3245 1/1 assign mio_en_d2p[MioOutI2c2Scl] = cio_i2c2_scl_en_d2p;
Tests: T64 T96 T12
3246 1/1 assign mio_en_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_en_d2p[0];
Tests: T28 T12 T50
3247 1/1 assign mio_en_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_en_d2p[1];
Tests: T12 T171 T172
3248 1/1 assign mio_en_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_en_d2p[2];
Tests: T12 T171 T172
3249 1/1 assign mio_en_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_en_d2p[3];
Tests: T12 T171 T172
3250 unreachable assign mio_en_d2p[MioOutUart0Tx] = cio_uart0_tx_en_d2p;
3251 unreachable assign mio_en_d2p[MioOutUart1Tx] = cio_uart1_tx_en_d2p;
3252 unreachable assign mio_en_d2p[MioOutUart2Tx] = cio_uart2_tx_en_d2p;
3253 unreachable assign mio_en_d2p[MioOutUart3Tx] = cio_uart3_tx_en_d2p;
3254 unreachable assign mio_en_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_en_d2p;
3255 unreachable assign mio_en_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_en_d2p;
3256 unreachable assign mio_en_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_en_d2p;
3257 unreachable assign mio_en_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_en_d2p;
3258 1/1 assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p;
Tests: T28 T12 T50
3259 1/1 assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p;
Tests: T28 T12 T50
3260 0/1 ==> assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p;
3261 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[0];
3262 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[1];
3263 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[2];
3264 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[3];
3265 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[4];
3266 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[5];
3267 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[6];
3268 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[7];
3269 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[8];
3270 unreachable assign mio_en_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_en_d2p[0];
3271 unreachable assign mio_en_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_en_d2p[1];
3272 unreachable assign mio_en_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_en_d2p[2];
3273 unreachable assign mio_en_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_en_d2p[3];
3274 unreachable assign mio_en_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_en_d2p[4];
3275 unreachable assign mio_en_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_en_d2p[5];
3276 1/1 assign mio_en_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_en_d2p[0];
Tests: T1 T2 T3
3277 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_en_d2p;
3278 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_en_d2p;
3279 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_en_d2p;
3280 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_en_d2p;
3281 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
3282 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_en_d2p;
3283
3284 // All dedicated inputs
3285 logic [15:0] unused_dio_p2d;
3286 1/1 assign unused_dio_p2d = dio_p2d;
Tests: T4 T7 T28
3287 1/1 assign cio_usbdev_usb_dp_p2d = dio_p2d[DioUsbdevUsbDp];
Tests: T4 T7 T35
3288 1/1 assign cio_usbdev_usb_dn_p2d = dio_p2d[DioUsbdevUsbDn];
Tests: T4 T8 T9
3289 1/1 assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0];
Tests: T7 T28 T10
3290 1/1 assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1];
Tests: T7 T28 T10
3291 1/1 assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2];
Tests: T7 T28 T10
3292 1/1 assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3];
Tests: T7 T28 T10
3293 1/1 assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0];
Tests: T7 T6 T13
3294 1/1 assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1];
Tests: T7 T6 T13
3295 1/1 assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2];
Tests: T7 T6 T13
3296 1/1 assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3];
Tests: T7 T6 T13
3297 1/1 assign cio_sysrst_ctrl_aon_ec_rst_l_p2d = dio_p2d[DioSysrstCtrlAonEcRstL];
Tests: T25 T14 T70
3298 1/1 assign cio_sysrst_ctrl_aon_flash_wp_l_p2d = dio_p2d[DioSysrstCtrlAonFlashWpL];
Tests: T25 T14 T70
3299 1/1 assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck];
Tests: T7 T6 T13
3300 1/1 assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb];
Tests: T7 T6 T25
3301
3302 // All dedicated outputs
3303 1/1 assign dio_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_d2p;
Tests: T4 T8 T9
3304 1/1 assign dio_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_d2p;
Tests: T4 T8 T9
3305 1/1 assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0];
Tests: T10 T11 T12
3306 1/1 assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1];
Tests: T10 T11 T12
3307 1/1 assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2];
Tests: T10 T11 T12
3308 1/1 assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3];
Tests: T10 T11 T12
3309 1/1 assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0];
Tests: T10 T11 T12
3310 1/1 assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1];
Tests: T13 T10 T11
3311 1/1 assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2];
Tests: T10 T11 T12
3312 1/1 assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3];
Tests: T10 T11 T12
3313 1/1 assign dio_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_d2p;
Tests: T14 T15 T16
3314 1/1 assign dio_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_d2p;
Tests: T14 T17 T15
3315 assign dio_d2p[DioSpiDeviceSck] = 1'b0;
3316 assign dio_d2p[DioSpiDeviceCsb] = 1'b0;
3317 1/1 assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p;
Tests: T10 T11 T12
3318 1/1 assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p;
Tests: T10 T11 T12
3319
3320 // All dedicated output enables
3321 1/1 assign dio_en_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_en_d2p;
Tests: T9 T18 T19
3322 1/1 assign dio_en_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_en_d2p;
Tests: T9 T18 T19
3323 1/1 assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0];
Tests: T10 T11 T12
3324 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1];
3325 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2];
3326 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3];
3327 1/1 assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0];
Tests: T7 T10 T12
3328 1/1 assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1];
Tests: T7 T13 T10
3329 1/1 assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2];
Tests: T7 T10 T12
3330 1/1 assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3];
Tests: T7 T10 T12
3331 unreachable assign dio_en_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_en_d2p;
3332 unreachable assign dio_en_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_en_d2p;
3333 assign dio_en_d2p[DioSpiDeviceSck] = 1'b0;
3334 assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0;
3335 1/1 assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p;
Tests: T10 T11 T12
3336 1/1 assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p;
Tests: T10 T11 T12