Unified Coverage Report :: Cond split page

Go back

 LINE       35152
 EXPRESSION (addr_hit[288] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T417,T418,T580
1	1	1	Covered	T534,T535,T536

 LINE       35173
 EXPRESSION (addr_hit[289] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Not Covered
1	1	1	Covered	T104,T622,T484

 LINE       35174
 EXPRESSION (addr_hit[289] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T570,T589,T494
1	1	1	Covered	T494,T496,T525

 LINE       35195
 EXPRESSION (addr_hit[290] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Not Covered
1	1	1	Covered	T632,T518,T633

 LINE       35196
 EXPRESSION (addr_hit[290] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T418,T588,T591
1	1	1	Covered	T537,T538,T539

 LINE       35217
 EXPRESSION (addr_hit[291] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T634
1	1	1	Covered	T497,T599,T635

 LINE       35218
 EXPRESSION (addr_hit[291] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T417,T418,T588
1	1	1	Covered	T540,T485,T539

 LINE       35239
 EXPRESSION (addr_hit[292] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Not Covered
1	1	1	Covered	T603,T490,T517

 LINE       35240
 EXPRESSION (addr_hit[292] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T589,T502,T595
1	1	1	Covered	T541,T489,T542

 LINE       35261
 EXPRESSION (addr_hit[293] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Not Covered
1	1	1	Covered	T509,T492,T518

 LINE       35262
 EXPRESSION (addr_hit[293] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T263,T107,T470
1	1	0	Covered	T418,T588,T589
1	1	1	Covered	T484,T528,T543

 LINE       35283
 EXPRESSION (addr_hit[294] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Not Covered
1	1	1	Covered	T490,T485,T514

 LINE       35284
 EXPRESSION (addr_hit[294] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T580,T484,T592
1	1	1	Covered	T504,T495,T544

 LINE       35305
 EXPRESSION (addr_hit[295] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Not Covered
1	1	1	Covered	T569,T497,T509

 LINE       35306
 EXPRESSION (addr_hit[295] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T480,T580,T589
1	1	1	Covered	T508,T485,T518

 LINE       35327
 EXPRESSION (addr_hit[296] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T471,T472,T473
1	1	0	Not Covered
1	1	1	Covered	T512,T636,T627

 LINE       35328
 EXPRESSION (addr_hit[296] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T471,T472,T473
1	1	0	Covered	T588,T589,T597
1	1	1	Covered	T545,T546,T518

 LINE       35349
 EXPRESSION (addr_hit[297] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T471,T474,T472
1	1	0	Not Covered
1	1	1	Covered	T509,T598,T637

 LINE       35350
 EXPRESSION (addr_hit[297] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T471,T474,T472
1	1	0	Covered	T484,T494,T595
1	1	1	Covered	T513,T484,T547

 LINE       35371
 EXPRESSION (addr_hit[298] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T309,T475,T476
1	1	0	Not Covered
1	1	1	Covered	T475,T497,T484

 LINE       35372
 EXPRESSION (addr_hit[298] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T309,T475,T476
1	1	0	Covered	T417,T418,T580
1	1	1	Covered	T490,T541,T548

 LINE       35393
 EXPRESSION (addr_hit[299] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Not Covered
1	1	1	Covered	T497,T597,T484

 LINE       35394
 EXPRESSION (addr_hit[299] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T417,T580,T638
1	1	1	Covered	T497,T513,T549

 LINE       35415
 EXPRESSION (addr_hit[300] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Not Covered
1	1	1	Covered	T458,T497,T504

 LINE       35416
 EXPRESSION (addr_hit[300] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T580,T592,T594
1	1	1	Covered	T484,T493,T550

 LINE       35437
 EXPRESSION (addr_hit[301] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Not Covered
1	1	1	Covered	T456,T639,T536

 LINE       35438
 EXPRESSION (addr_hit[301] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T458,T418,T640
1	1	1	Covered	T551,T485,T528

 LINE       35459
 EXPRESSION (addr_hit[302] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T641
1	1	1	Covered	T494,T528,T552

 LINE       35460
 EXPRESSION (addr_hit[302] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T80,T262
1	1	0	Covered	T523,T588,T490
1	1	1	Covered	T490,T520,T552

 LINE       35481
 EXPRESSION (addr_hit[303] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T417,T588,T589
1	1	1	Covered	T69,T515,T407

 LINE       35484
 EXPRESSION (addr_hit[304] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T418,T589,T592
1	1	1	Covered	T69,T407,T158

 LINE       35487
 EXPRESSION (addr_hit[305] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T47
1	1	0	Covered	T417,T589,T592
1	1	1	Covered	T69,T407,T158

 LINE       35490
 EXPRESSION (addr_hit[306] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T418,T580,T588
1	1	1	Covered	T69,T407,T158

 LINE       35493
 EXPRESSION (addr_hit[307] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T47
1	1	0	Covered	T417,T588,T589
1	1	1	Covered	T69,T407,T158

 LINE       35496
 EXPRESSION (addr_hit[308] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T418,T595,T606
1	1	1	Covered	T69,T458,T407

 LINE       35499
 EXPRESSION (addr_hit[309] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T191
1	1	0	Covered	T418,T580,T588
1	1	1	Covered	T69,T407,T158

 LINE       35502
 EXPRESSION (addr_hit[310] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Covered	T612,T588,T490
1	1	1	Covered	T69,T456,T407

 LINE       35505
 EXPRESSION (addr_hit[311] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Covered	T588,T484,T592
1	1	1	Covered	T69,T564,T407

 LINE       35508
 EXPRESSION (addr_hit[312] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Covered	T497,T591,T589
1	1	1	Covered	T69,T407,T158

 LINE       35511
 EXPRESSION (addr_hit[313] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T191,T17,T80
1	1	0	Covered	T588,T642,T592
1	1	1	Covered	T69,T407,T158

 LINE       35514
 EXPRESSION (addr_hit[314] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T191,T17,T80
1	1	0	Covered	T588,T589,T490
1	1	1	Covered	T69,T407,T158

 LINE       35517
 EXPRESSION (addr_hit[315] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T191,T80,T263
1	1	0	Covered	T417,T588,T589
1	1	1	Covered	T69,T407,T158

 LINE       35520
 EXPRESSION (addr_hit[316] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T191,T80,T263
1	1	0	Covered	T485,T595,T606
1	1	1	Covered	T69,T407,T158

 LINE       35523
 EXPRESSION (addr_hit[317] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T534,T484,T592
1	1	1	Covered	T69,T569,T407

 LINE       35526
 EXPRESSION (addr_hit[318] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T588,T497,T603
1	1	1	Covered	T69,T564,T575

 LINE       35529
 EXPRESSION (addr_hit[319] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       35530
 EXPRESSION (addr_hit[319] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T564,T418,T580
1	1	1	Covered	T1,T2,T3

 LINE       35551
 EXPRESSION (addr_hit[320] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       35552
 EXPRESSION (addr_hit[320] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T417,T588,T497
1	1	1	Covered	T1,T2,T3

 LINE       35573
 EXPRESSION (addr_hit[321] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T643
1	1	1	Covered	T28,T10,T11

 LINE       35574
 EXPRESSION (addr_hit[321] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T580,T588,T592
1	1	1	Covered	T28,T10,T11

 LINE       35595
 EXPRESSION (addr_hit[322] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T28,T10,T11

 LINE       35596
 EXPRESSION (addr_hit[322] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T417,T588,T497
1	1	1	Covered	T28,T10,T11

 LINE       35617
 EXPRESSION (addr_hit[323] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T28,T10,T11

 LINE       35618
 EXPRESSION (addr_hit[323] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T596,T588,T592
1	1	1	Covered	T28,T10,T11

 LINE       35639
 EXPRESSION (addr_hit[324] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T28,T10,T11

 LINE       35640
 EXPRESSION (addr_hit[324] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T588,T589,T494
1	1	1	Covered	T28,T10,T11

 LINE       35661
 EXPRESSION (addr_hit[325] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       35662
 EXPRESSION (addr_hit[325] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Covered	T588,T591,T589
1	1	1	Covered	T10,T11,T12

 LINE       35683
 EXPRESSION (addr_hit[326] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       35684
 EXPRESSION (addr_hit[326] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T12
1	1	0	Covered	T580,T592,T594
1	1	1	Covered	T10,T11,T12

 LINE       35705
 EXPRESSION (addr_hit[327] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T192
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       35706
 EXPRESSION (addr_hit[327] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T192
1	1	0	Covered	T588,T589,T592
1	1	1	Covered	T10,T11,T12

 LINE       35727
 EXPRESSION (addr_hit[328] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T192
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       35728
 EXPRESSION (addr_hit[328] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T192
1	1	0	Covered	T566,T580,T588
1	1	1	Covered	T10,T11,T12

 LINE       35749
 EXPRESSION (addr_hit[329] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T192,T265
1	1	0	Not Covered
1	1	1	Covered	T17,T48,T49

 LINE       35750
 EXPRESSION (addr_hit[329] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T192,T265
1	1	0	Covered	T418,T588,T497
1	1	1	Covered	T17,T48,T49

 LINE       35771
 EXPRESSION (addr_hit[330] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T192,T57
1	1	0	Not Covered
1	1	1	Covered	T17,T48,T49

 LINE       35772
 EXPRESSION (addr_hit[330] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T192,T57
1	1	0	Covered	T418,T580,T497
1	1	1	Covered	T17,T48,T49

 LINE       35793
 EXPRESSION (addr_hit[331] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T192,T57,T477
1	1	0	Not Covered
1	1	1	Covered	T158,T160,T408

 LINE       35794
 EXPRESSION (addr_hit[331] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T192,T57,T477
1	1	0	Covered	T417,T588,T591
1	1	1	Covered	T553,T554,T555

 LINE       35815
 EXPRESSION (addr_hit[332] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T57,T477,T478
1	1	0	Not Covered
1	1	1	Covered	T613,T158,T160

 LINE       35816
 EXPRESSION (addr_hit[332] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T57,T477,T478
1	1	0	Covered	T589,T592,T587
1	1	1	Covered	T502,T509,T495

 LINE       35837
 EXPRESSION (addr_hit[333] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T28,T10,T11

 LINE       35838
 EXPRESSION (addr_hit[333] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T580,T588,T497
1	1	1	Covered	T28,T10,T11

 LINE       35859
 EXPRESSION (addr_hit[334] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T28,T10,T11

 LINE       35860
 EXPRESSION (addr_hit[334] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T10,T11
1	1	0	Covered	T612,T588,T589
1	1	1	Covered	T28,T10,T11

 LINE       35881
 EXPRESSION (addr_hit[335] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T29,T76
1	1	0	Covered	T577,T588,T497
1	1	1	Covered	T6,T29,T76

 LINE       35946
 EXPRESSION (addr_hit[336] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T87,T192
1	1	0	Covered	T580,T588,T589
1	1	1	Covered	T69,T407,T158

 LINE       35977
 EXPRESSION (addr_hit[337] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T46,T29
1	1	0	Covered	T580,T588,T490
1	1	1	Covered	T69,T407,T158