Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T173 T246 T253 | T173 T246 T253 | T173 T246 T254 | T173 T246 T254 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T173 T246 T253 | T73 T246 T174 | T73 T246 T174 | T73 T246 T174 | T73 T246 T174 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T73 T246 T174 | T32 T66 T246 | T32 T66 T246 | T32 T66 T246 | T32 T66 T246 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T32 T66 T246 | T30 T68 T246 | T30 T68 T246 | T30 T68 T246 | T30 T68 T246 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T30 T68 T246 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T169 T232 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T13 T169 T52 | T169 T189 T190 | T169 T189 T190 | T61 T257 T62 | T61 T257 T62 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T61 T257 T62 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T63 T257 T260 | T63 T257 T260 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T33 T63 T257 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T64 T257 T261 | T64 T257 T261 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T64 T257 T65 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T169 T176 T189 | T5 T169 T189 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T47 T262 T357 | T191 T264 T192 | T257 T265 T266 | T46 T87 T192 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T71 T246 T239 | T140 T257 T267 | T268 T269 T358 | T247 T269 T357 | T131 T169 T271 | T169 T189 T190 | T1 T248 T134 | T1 T248 T134 | T248 T134 T257 | T248 T134 T257 | T1 T248 T134 | T257 T258 T259 | T249 T250 T257 | T257 T258 T259 | T257 T258 T259 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T251 T169 T181 | T169 T189 T190 | T257 T258 T259 | T272 T257 T273 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T272 T257 T273 | T257 T258 T259 | T272 T257 T273 | T257 T258 T259
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T243 T244 T245 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T13 T10 T31 | T13 T243 T169 | T13 T243 T169 | T13 T10 T11 | T13 T10 T11 | T13 T243 T169 | T243 T169 T246 | T243 T169 T246 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T61 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T243 T169 T246 | T33 T63 T243 | T33 T243 T169 | T243 T169 T246 | T33 T243 T169 | T33 T243 T169 | T33 T243 T169 | T64 T243 T169 | T64 T243 T169 | T243 T169 T246 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T243 T169 T246 | T64 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T5 T243 T169 | T5 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T46 T47 T87 | T46 T47 T87 | T46 T47 T87 | T46 T47 T87 | T10 T11 T243 | T10 T11 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T6 T25 T29 | T71 T243 T169 | T140 T243 T169 | T46 T47 T87 | T46 T247 T47 | T131 T243 T169 | T243 T169 T246 | T1 T248 T134 | T1 T248 T134 | T1 T248 T134 | T1 T248 T134 | T1 T248 T134 | T243 T169 T246 | T249 T250 T243 | T249 T250 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T1 T5 T6 | T5 T13 T73 | T73 T32 T30 | T5 T13 T33 | T1 T6 T46 | T73 T32 T30 | T30 T31 T68 | T13 T10 T31 | T5 T33 T47 | T6 T46 T25 | T1 T248 T134 | T73 T173 T243 | T73 T32 T30 | T30 T31 T68 | T31 T243 T169 | T13 T10 T31 | T63 T61 T243 | T33 T64 T63 | T5 T47 T64 | T46 T47 T87 | T6 T25 T29 | T1 T248 T134 | T243 T169 T246 | T173 T243 T169 | T73 T173 T243 | T73 T32 T66 | T32 T30 T68 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T10 T31 T243 | T13 T10 T11 | T61 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T64 T243 | T64 T243 T169 | T5 T47 T262 | T46 T10 T47 | T243 T169 T246 | T243 T169 T246 | T6 T46 T25 | T1 T248 T134 | T251 T243 T169 | T243 T169 T246 | T173 T243 T169 | T173 T243 T169 | T73 T173 T243 | T73 T243 T169 | T73 T32 T66 | T32 T66 T243 | T32 T66 T243 | T30 T68 T243 | T30 T68 T243 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T13 T10 T31 | T13 T10 T11 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T64 T243 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T5 T243 T169 | T47 T262 T357 | T46 T47 T87 | T10 T11 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T6 T25 T29 | T46 T247 T47 | T1 T248 T134 | T1 T248 T134 | T243 T169 T246 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T32 T66 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T13 T10 T31 | T13 T243 T169 | T13 T10 T11 | T13 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T243 T169 | T33 T243 T169 | T33 T64 T243 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T243 T169 T246 | T243 T169 T246 | T5 T243 T169 | T243 T169 T246 | T46 T47 T87 | T46 T47 T87 | T46 T10 T47 | T10 T11 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T6 T25 T29 | T71 T140 T243 | T46 T247 T47 | T131 T243 T169 | T1 T248 T134 | T1 T248 T134 | T1 T248 T134 | T249 T250 T243 | T243 T169 T246 | T243 T169 T246 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T1 T5 T6 | T5 T13 T73 | T1 T6 T46 | T73 T32 T30 | T5 T13 T33 | T1 T6 T46 | T73 T32 T30 | T30 T31 T68 | T13 T10 T31 | T5 T33 T47 | T6 T46 T25 | T1 T248 T134 | T73 T173 T246 | T73 T32 T30 | T30 T31 T68 | T31 T257 T44 | T13 T10 T31 | T63 T61 T257 | T33 T64 T63 | T5 T47 T64 | T46 T87 T191 | T6 T25 T29 | T1 T248 T134 | T272 T257 T273 | T173 T246 T254 | T73 T173 T246 | T73 T32 T66 | T32 T30 T68 | T30 T31 T68 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T31 T169 | T13 T61 T169 | T61 T257 T62 | T63 T257 T260 | T33 T63 T257 | T64 T257 T261 | T64 T257 T65 | T5 T47 T262 | T46 T87 T191 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T1 T248 T134 | T251 T169 T272 | T272 T257 T273 | T272 T257 T273 | T173 T246 T254 | T173 T246 T254 | T73 T173 T246 | T73 T246 T174 | T73 T32 T66 | T32 T66 T246 | T32 T66 T246 | T30 T68 T246 | T246 T255 T256 | T30 T31 T68 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T31 T169 | T13 T169 T52 | T61 T169 T257 | T257 T258 T259 | T61 T257 T62 | T257 T258 T259 | T63 T257 T260 | T257 T258 T259 | T33 T63 T257 | T64 T257 T261 | T64 T257 T261 | T257 T258 T259 | T64 T257 T65 | T5 T169 T257 | T47 T262 T357 | T46 T87 T191 | T169 T246 T189 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T247 T268 T269 | T1 T248 T134 | T1 T248 T134 | T169 T257 T189 | T251 T169 T272 | T257 T258 T259 | T272 T257 T273 | T272 T257 T273 | T173 T246 T253 | T173 T246 T254 | T173 T246 T254 | T246 T255 T256 | T173 T246 T253 | T73 T246 T174 | T73 T246 T174 | T246 T255 T256 | T246 T255 T256 | T73 T32 T66 | T32 T66 T246 | T32 T66 T246 | T246 T255 T256 | T32 T66 T246 | T30 T68 T246 | T30 T68 T246 | T246 T255 T256 | T246 T255 T256 | T30 T31 T68 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T31 T169 | T169 T189 T190 | T169 T189 T190 | T13 T169 T52 | T61 T169 T257 | T61 T257 T62 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T61 T257 T62 | T257 T258 T259 | T257 T258 T259 | T63 T257 T260 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T33 T63 T257 | T257 T258 T259 | T257 T258 T259 | T64 T257 T261 | T64 T257 T261 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T64 T257 T65 | T257 T258 T259 | T257 T258 T259 | T5 T169 T176 | T169 T189 T190 | T47 T262 T357 | T191 T264 T192 | T46 T87 T192 | T169 T189 T190 | T169 T246 T189 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T71 T140 T246 | T247 T268 T269 | T131 T169 T271 | T1 T248 T134 | T248 T134 T257 | T1 T248 T134 | T249 T250 T257 | T169 T257 T189 | T169 T189 T190 | T251 T169 T181 | T272 T257 T273 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T272 T257 T273 | T272 T257 T273
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T1 T5 T6 | T5 T13 T73 | T1 T6 T46 | T73 T32 T30 | T5 T13 T33 | T1 T6 T46 | T73 T32 T30 | T30 T31 T68 | T13 T10 T31 | T5 T33 T47 | T6 T46 T25 | T1 T248 T134 | T73 T173 T246 | T73 T32 T30 | T30 T31 T68 | T31 T257 T44 | T13 T10 T31 | T63 T61 T257 | T33 T64 T63 | T5 T47 T64 | T46 T87 T192 | T6 T25 T29 | T1 T248 T134 | T272 T257 T273 | T173 T246 T254 | T73 T173 T246 | T73 T32 T66 | T32 T30 T68 | T30 T31 T68 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T31 T169 | T13 T61 T169 | T61 T257 T62 | T63 T257 T260 | T33 T63 T257 | T64 T257 T261 | T64 T257 T65 | T5 T47 T262 | T46 T87 T192 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T1 T248 T134 | T251 T169 T272 | T272 T257 T273 | T257 T258 T259 | T173 T246 T254 | T246 T255 T256 | T73 T173 T246 | T73 T246 T174 | T73 T32 T66 | T32 T66 T246 | T32 T66 T246 | T30 T68 T246 | T246 T255 T256 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T169 T232 | T13 T169 T52 | T61 T257 T62 | T257 T258 T259 | T61 T257 T62 | T257 T258 T259 | T63 T257 T260 | T257 T258 T259 | T33 T63 T257 | T64 T257 T261 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T5 T169 T257 | T47 T262 T357 | T46 T87 T192 | T169 T246 T189 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T247 T269 T357 | T1 T248 T134 | T249 T250 T257 | T169 T189 T190 | T169 T272 T257 | T257 T258 T259 | T272 T257 T273 | T257 T258 T259 | T173 T246 T253 | T173 T246 T254 | T246 T255 T256 | T246 T255 T256 | T173 T246 T253 | T73 T246 T174 | T73 T246 T174 | T246 T255 T256 | T246 T255 T256 | T32 T66 T246 | T32 T66 T246 | T246 T255 T256 | T246 T255 T256 | T32 T66 T246 | T30 T68 T246 | T30 T68 T246 | T246 T255 T256 | T246 T255 T256 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T31 T257 T44 | T10 T169 T232 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T61 T257 T62 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T63 T257 T260 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T33 T63 T257 | T257 T258 T259 | T257 T258 T259 | T64 T257 T261 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T5 T169 T189 | T169 T189 T190 | T47 T262 T357 | T257 T265 T266 | T169 T189 T190 | T169 T189 T190 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T246 T255 T256 | T6 T25 T29 | T140 T257 T267 | T247 T269 T357 | T169 T189 T190 | T1 T248 T134 | T248 T134 T257 | T257 T258 T259 | T257 T258 T259 | T169 T189 T190 | T169 T189 T190 | T169 T189 T190 | T272 T257 T273 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259 | T257 T258 T259
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T1 T5 T6 | T5 T13 T73 | T1 T6 T46 | T73 T32 T30 | T5 T13 T33 | T1 T6 T46 | T73 T32 T30 | T30 T31 T68 | T13 T10 T31 | T5 T33 T47 | T6 T46 T25 | T1 T248 T134 | T73 T173 T243 | T73 T32 T30 | T30 T31 T68 | T31 T243 T169 | T13 T10 T31 | T63 T61 T243 | T33 T64 T63 | T5 T47 T64 | T46 T47 T87 | T6 T25 T29 | T1 T248 T134 | T243 T169 T246 | T173 T243 T169 | T73 T173 T243 | T73 T32 T66 | T32 T30 T68 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T10 T31 T243 | T13 T10 T11 | T61 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T64 T243 | T64 T243 T169 | T5 T47 T262 | T46 T10 T47 | T243 T169 T246 | T243 T169 T246 | T6 T46 T25 | T1 T248 T134 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T173 T243 T169 | T173 T243 T169 | T73 T173 T243 | T73 T243 T169 | T73 T32 T66 | T32 T66 T243 | T32 T66 T243 | T30 T68 T243 | T30 T68 T243 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T13 T10 T31 | T13 T10 T11 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T64 T243 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T5 T243 T169 | T47 T262 T357 | T46 T47 T87 | T10 T11 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T6 T25 T29 | T46 T247 T47 | T1 T248 T134 | T1 T248 T134 | T243 T169 T246 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T173 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T243 T169 | T73 T32 T66 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T32 T66 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T68 T243 | T30 T31 T68 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T31 T243 T169 | T13 T10 T31 | T13 T243 T169 | T13 T10 T11 | T13 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T61 T243 T169 | T243 T169 T246 | T243 T169 T246 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T63 T243 T169 | T33 T63 T243 | T33 T243 T169 | T33 T243 T169 | T33 T64 T243 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T64 T243 T169 | T243 T169 T246 | T243 T169 T246 | T5 T243 T169 | T243 T169 T246 | T46 T47 T87 | T46 T47 T87 | T46 T10 T47 | T10 T11 T243 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T6 T25 T29 | T71 T140 T243 | T46 T247 T47 | T131 T243 T169 | T1 T248 T134 | T1 T248 T134 | T1 T248 T134 | T249 T250 T243 | T243 T169 T246 | T243 T169 T246 | T251 T243 T169 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246 | T243 T169 T246
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T1 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T1 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T1 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);