Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	463	1			T568	1		T555	1		T463	1
all_values[1]	541	1			T555	1		T463	1		T453	2
all_values[2]	463	1			T555	2		T547	1		T882	1
all_values[3]	480	1			T555	1		T453	1		T547	1
all_values[4]	476	1			T555	1		T453	1		T547	1
all_values[5]	492	1			T555	1		T453	2		T547	1
all_values[6]	448	1			T463	1		T547	1		T439	1
all_values[7]	470	1			T569	1		T463	1		T439	1
all_values[8]	464	1			T86	1		T555	2		T463	1
all_values[9]	467	1			T555	1		T453	3		T882	1
all_values[10]	480	1			T453	1		T547	1		T474	1
all_values[11]	458	1			T555	1		T463	1		T453	2
all_values[12]	455	1			T555	2		T474	1		T810	1
all_values[13]	464	1			T453	2		T439	2		T810	1
all_values[14]	489	1			T569	1		T555	1		T463	1
all_values[15]	492	1			T555	2		T463	1		T453	1
all_values[16]	489	1			T453	1		T547	1		T882	1
all_values[17]	490	1			T563	1		T439	2		T474	1
all_values[18]	463	1			T463	1		T453	2		T474	3
all_values[19]	470	1			T555	2		T453	1		T547	1
all_values[20]	479	1			T555	2		T547	1		T658	1
all_values[21]	499	1			T555	3		T453	1		T547	1
all_values[22]	484	1			T555	1		T463	1		T453	2
all_values[23]	521	1			T555	3		T453	1		T439	1
all_values[24]	521	1			T555	1		T463	1		T439	3
all_values[25]	468	1			T568	1		T555	1		T463	1
all_values[26]	467	1			T568	1		T547	1		T658	1
all_values[27]	474	1			T568	1		T453	1		T547	2
all_values[28]	489	1			T555	1		T463	2		T563	2
all_values[29]	485	1			T555	1		T463	1		T453	2
all_values[30]	455	1			T463	1		T453	1		T439	2
all_values[31]	461	1			T555	1		T547	1		T439	1
all_values[32]	485	1			T555	1		T463	1		T453	1
all_values[33]	470	1			T555	1		T453	1		T547	1
all_values[34]	511	1			T569	1		T568	1		T555	1
all_values[35]	484	1			T555	2		T439	1		T474	1
all_values[36]	474	1			T555	1		T439	1		T882	1
all_values[37]	465	1			T86	1		T474	1		T573	5
all_values[38]	505	1			T463	1		T474	2		T573	2
all_values[39]	506	1			T555	1		T463	1		T453	1
all_values[40]	499	1			T555	2		T463	1		T547	1
all_values[41]	499	1			T555	2		T463	1		T474	1
all_values[42]	486	1			T555	1		T453	1		T439	2
all_values[43]	525	1			T555	1		T453	2		T563	1
all_values[44]	484	1			T568	1		T555	2		T453	1
all_values[45]	497	1			T555	1		T453	4		T547	2
all_values[46]	506	1			T453	1		T547	1		T439	3
all_values[47]	478	1			T555	1		T563	1		T547	1
all_values[48]	505	1			T568	1		T547	2		T439	2
all_values[49]	488	1			T568	1		T547	1		T439	1