Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.81 95.32 93.12 95.43 93.85 97.57 99.57


Total tests in report: 2913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.86 40.86 49.59 49.59 49.39 49.39 22.69 22.69 64.11 64.11 59.28 59.28 0.13 0.13 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1014747965
47.82 6.96 53.71 4.12 57.45 8.07 22.95 0.26 70.07 5.96 81.96 22.68 0.78 0.65 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2800588655
53.14 5.32 64.92 11.21 65.05 7.60 26.04 3.09 80.07 10.00 81.96 0.00 0.78 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.367323709
57.05 3.92 72.72 7.81 66.60 1.54 32.58 6.54 80.31 0.24 81.96 0.00 8.15 7.38 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1676184677
60.12 3.07 77.62 4.90 70.41 3.81 36.13 3.55 82.00 1.70 86.43 4.47 8.15 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2088239172
63.07 2.95 77.62 0.00 70.41 0.00 53.56 17.42 82.00 0.00 86.60 0.17 8.26 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2856674397
65.55 2.48 77.62 0.00 70.95 0.54 53.56 0.00 82.04 0.03 86.60 0.00 22.55 14.29 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3649995367
67.97 2.42 79.17 1.55 73.69 2.74 58.90 5.34 83.89 1.86 86.94 0.34 25.21 2.67 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.624965865
69.97 2.00 79.17 0.00 73.94 0.25 58.90 0.00 83.93 0.03 86.94 0.00 36.93 11.71 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2384748338
71.74 1.77 81.08 1.91 75.27 1.34 62.76 3.87 85.03 1.10 89.35 2.41 36.93 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1766272641
73.35 1.61 84.31 3.23 76.60 1.33 66.24 3.47 85.96 0.93 90.03 0.69 36.93 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3928046298
74.94 1.60 84.31 0.00 76.60 0.00 66.24 0.00 85.96 0.00 90.03 0.00 46.50 9.58 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4139143364
76.39 1.45 84.31 0.00 77.59 0.99 66.24 0.00 86.06 0.10 90.03 0.00 54.13 7.63 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.733539209
77.83 1.44 84.42 0.11 77.70 0.10 74.30 8.07 86.23 0.17 90.21 0.17 54.13 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.4053602310
79.10 1.27 86.76 2.34 79.65 1.95 74.96 0.65 88.92 2.69 90.21 0.00 54.13 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.2115067892
80.25 1.15 86.76 0.00 79.65 0.00 74.96 0.00 88.92 0.00 90.21 0.00 61.03 6.90 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2759154251
81.35 1.10 86.76 0.00 79.65 0.00 74.96 0.00 88.92 0.00 90.21 0.00 67.62 6.59 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.167313167
82.34 0.99 87.88 1.12 80.37 0.72 77.65 2.69 89.98 1.05 90.55 0.34 67.62 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1981276026
83.31 0.97 88.71 0.83 84.23 3.86 78.05 0.40 90.63 0.65 90.55 0.00 67.70 0.08 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.29730427
84.18 0.87 88.71 0.00 84.31 0.08 78.05 0.00 90.63 0.00 90.55 0.00 72.84 5.13 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2356588414
85.05 0.87 89.61 0.90 85.21 0.90 78.36 0.31 91.64 1.01 92.61 2.06 72.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2840699429
85.88 0.83 89.61 0.00 85.21 0.00 83.34 4.98 91.64 0.00 92.61 0.00 72.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1604297652
86.70 0.82 90.34 0.73 85.39 0.18 83.35 0.01 91.86 0.22 96.39 3.78 72.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1112119593
87.35 0.65 90.34 0.00 85.39 0.00 83.35 0.00 91.86 0.00 96.39 0.00 76.75 3.91 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2960675817
87.97 0.62 91.39 1.05 85.82 0.43 85.35 2.00 92.11 0.24 96.39 0.00 76.75 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2608467906
88.55 0.58 91.39 0.00 86.17 0.35 85.36 0.01 92.11 0.00 96.39 0.00 79.88 3.14 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2481866788
89.11 0.56 91.39 0.00 86.17 0.00 85.36 0.00 92.11 0.00 96.39 0.00 83.22 3.34 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2812210651
89.62 0.52 91.39 0.00 86.23 0.07 85.36 0.00 92.12 0.02 96.39 0.00 86.24 3.02 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.3016354406
90.03 0.40 91.39 0.00 86.30 0.06 85.36 0.00 92.14 0.02 96.39 0.00 88.59 2.35 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.962833144
90.39 0.36 91.40 0.01 86.30 0.01 87.32 1.96 92.14 0.00 96.56 0.17 88.59 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1367588960
90.74 0.36 91.41 0.01 88.01 1.71 87.32 0.00 92.14 0.00 96.56 0.00 89.01 0.42 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.636579521
91.09 0.35 91.41 0.00 88.01 0.00 87.32 0.00 92.14 0.00 96.56 0.00 91.11 2.09 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.348151241
91.41 0.32 92.37 0.96 88.24 0.24 87.85 0.53 92.32 0.18 96.56 0.00 91.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1860735384
91.71 0.31 92.37 0.00 88.24 0.00 87.85 0.00 92.32 0.00 96.56 0.00 92.94 1.83 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3854726073
92.00 0.29 92.79 0.42 88.74 0.49 88.16 0.31 92.80 0.49 96.56 0.00 92.94 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.349991354
92.25 0.25 93.38 0.59 89.01 0.27 88.49 0.32 93.10 0.30 96.56 0.00 92.94 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.2304405702
92.48 0.23 93.38 0.00 89.04 0.03 88.49 0.00 93.10 0.00 96.56 0.00 94.30 1.36 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2149244971
92.70 0.22 93.38 0.00 89.04 0.00 89.81 1.32 93.10 0.00 96.56 0.00 94.30 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2455754983
92.87 0.17 93.40 0.02 89.07 0.03 90.75 0.94 93.13 0.02 96.56 0.00 94.30 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.1831516269
93.04 0.17 93.59 0.19 89.77 0.70 90.75 0.01 93.23 0.11 96.56 0.00 94.30 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.2906256594
93.20 0.16 93.59 0.00 89.77 0.00 90.75 0.00 93.23 0.00 96.56 0.00 95.26 0.96 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.2786315633
93.34 0.14 93.73 0.14 89.81 0.04 91.42 0.66 93.23 0.00 96.56 0.00 95.28 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3732981089
93.48 0.14 93.84 0.10 89.85 0.04 92.08 0.66 93.26 0.02 96.56 0.00 95.28 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2594991148
93.61 0.13 93.84 0.00 89.90 0.05 92.08 0.00 93.26 0.00 96.56 0.00 96.02 0.74 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.269020905
93.73 0.13 94.04 0.21 90.22 0.32 92.31 0.23 93.26 0.00 96.56 0.00 96.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2920374202
93.86 0.12 94.05 0.01 90.46 0.24 92.31 0.01 93.27 0.01 96.56 0.00 96.51 0.49 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3501716583
93.98 0.12 94.05 0.00 90.46 0.00 93.02 0.70 93.27 0.00 96.56 0.00 96.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.235391717
94.07 0.10 94.14 0.09 90.53 0.07 93.39 0.38 93.31 0.05 96.56 0.00 96.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2239076611
94.17 0.09 94.14 0.00 90.68 0.16 93.39 0.00 93.33 0.02 96.56 0.00 96.90 0.39 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.862387277
94.26 0.09 94.30 0.17 90.79 0.11 93.55 0.16 93.45 0.12 96.56 0.00 96.90 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2602784682
94.34 0.08 94.30 0.00 91.28 0.49 93.55 0.00 93.45 0.00 96.56 0.00 96.90 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.160709026
94.42 0.08 94.30 0.00 91.32 0.03 93.55 0.00 93.45 0.00 96.56 0.00 97.36 0.46 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.4060403605
94.48 0.06 94.30 0.00 91.37 0.05 93.55 0.00 93.47 0.02 96.56 0.00 97.64 0.28 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.77944670
94.54 0.06 94.30 0.00 91.37 0.00 93.89 0.34 93.47 0.00 96.56 0.00 97.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.980665719
94.59 0.05 94.33 0.03 91.39 0.02 93.96 0.07 93.49 0.02 96.74 0.17 97.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3104483871
94.64 0.05 94.34 0.01 91.50 0.11 94.05 0.09 93.61 0.11 96.74 0.00 97.64 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2814200302
94.68 0.04 94.35 0.01 91.51 0.02 94.05 0.00 93.63 0.02 96.91 0.17 97.65 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3317517045
94.72 0.04 94.35 0.01 91.52 0.01 94.06 0.01 93.64 0.01 97.08 0.17 97.66 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3342169950
94.75 0.04 94.35 0.01 91.54 0.01 94.06 0.01 93.65 0.01 97.25 0.17 97.67 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2565081639
94.79 0.04 94.36 0.01 91.55 0.01 94.06 0.00 93.66 0.01 97.42 0.17 97.69 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2761095514
94.82 0.03 94.36 0.00 91.55 0.01 94.06 0.00 93.66 0.00 97.42 0.00 97.89 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2098182069
94.86 0.03 94.36 0.00 91.55 0.00 94.06 0.00 93.66 0.00 97.42 0.00 98.08 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4285583180
94.89 0.03 94.40 0.04 91.58 0.03 94.14 0.08 93.68 0.02 97.42 0.00 98.10 0.01 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1819407530
94.92 0.03 94.40 0.00 91.77 0.19 94.14 0.00 93.68 0.00 97.42 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.3609559182
94.95 0.03 94.40 0.00 91.77 0.00 94.15 0.01 93.68 0.00 97.59 0.17 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.108986665
94.98 0.03 94.47 0.07 91.77 0.00 94.25 0.10 93.69 0.01 97.59 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.3137002635
95.01 0.03 94.54 0.07 91.82 0.05 94.27 0.02 93.72 0.03 97.59 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2399912598
95.03 0.03 94.54 0.00 91.85 0.03 94.40 0.13 93.72 0.00 97.59 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3991316311
95.06 0.03 94.61 0.07 91.87 0.03 94.41 0.01 93.77 0.05 97.59 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3042980342
95.08 0.02 94.63 0.02 91.96 0.09 94.45 0.04 93.77 0.00 97.59 0.00 98.10 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1504643548
95.11 0.02 94.63 0.00 91.96 0.00 94.45 0.00 93.77 0.00 97.59 0.00 98.24 0.14 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2944360841
95.13 0.02 94.63 0.00 92.10 0.13 94.45 0.00 93.77 0.00 97.59 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3206104463
95.15 0.02 94.63 0.00 92.10 0.00 94.57 0.12 93.77 0.00 97.59 0.00 98.24 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.1766230727
95.17 0.02 94.63 0.00 92.12 0.02 94.57 0.00 93.77 0.00 97.59 0.00 98.33 0.09 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3814087317
95.19 0.02 94.63 0.01 92.15 0.03 94.65 0.08 93.77 0.00 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3051856053
95.20 0.02 94.63 0.00 92.23 0.08 94.65 0.00 93.77 0.00 97.59 0.00 98.36 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.1978056987
95.22 0.02 94.63 0.00 92.23 0.00 94.75 0.10 93.77 0.00 97.59 0.00 98.36 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3821666452
95.24 0.02 94.63 0.00 92.24 0.01 94.75 0.00 93.77 0.00 97.59 0.00 98.44 0.08 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2732291427
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95.71 0.01 94.71 0.00 93.09 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.44636091
95.71 0.01 94.71 0.00 93.10 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.415973516
95.71 0.01 94.71 0.00 93.10 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.804051412
95.71 0.01 94.71 0.00 93.10 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.2127910968
95.71 0.01 94.71 0.00 93.11 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.993286752
95.71 0.01 94.71 0.00 93.11 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1558350456
95.71 0.01 94.71 0.00 93.11 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.4261753848
95.71 0.01 94.71 0.00 93.12 0.01 95.42 0.00 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.3490886083
95.71 0.01 94.71 0.00 93.12 0.00 95.42 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3857410941
95.71 0.01 94.71 0.00 93.12 0.00 95.43 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.1461129112
95.71 0.01 94.71 0.00 93.12 0.00 95.43 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.4108019018
95.71 0.01 94.71 0.00 93.12 0.00 95.43 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.614509377
95.71 0.01 94.71 0.00 93.12 0.00 95.43 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2722517590
95.71 0.01 94.71 0.00 93.12 0.00 95.43 0.01 93.85 0.00 97.59 0.00 99.57 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1432654949

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2541939830
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3408943422
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3911668545
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.4001661476
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.720999571
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1775170308
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.582137426
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1819319608
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1925659176
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3763352871
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.4207068843
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3597132820
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2733142776
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.962800246
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.314582231
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.3984490432
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1485287399
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.23443452
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3217860305
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3625447535
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3600271373
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4114044338
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.647868197
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3049037474
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.4145023718
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.4163486078
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.3564239081
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1359227084
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1952700749
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.4234279787
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3072467058
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1268565103
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.293280978
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2501947037
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.4117997423
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.2345462208
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.551747015
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1760825332
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2138543012
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2111228644
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.1714604429
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.2878828983
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1465371240
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.340837351
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.206199739
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.3471105597
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.797544010
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2642152984
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.473038945
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1590366849
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4186482659
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1401200065
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2205662304
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.684494536
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2416047124
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2638784533
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1964351844
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.943877251
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1357332740
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.67787506
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1861108128
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1502236209
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.4121646381
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.902771168
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.745255274
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.703794507
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.1714496435
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3726291325
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2711942796
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.194188745
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.2838739753
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.913313460
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1498585203
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1372887103
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2191723264
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.609145573
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.3920850182
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2628964733
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.469081701
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1901884125
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1161113212
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.508575699
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.856166380
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.4046762531
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1194768389
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.128494441
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.4224011953
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1070597935
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1547168244
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2069744483
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1964213090
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3716295980
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.742336619
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3190612760
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3913955552
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1131233081
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1676107650
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1940491334
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3959489953
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3188099698
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3611500045
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.696270894
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3916448694
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.935267016
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2530875724
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.987971087
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3749009947
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2655496635
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/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.4214375856
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2413204850
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3519175313
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1377118853
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2793859896
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.652929140
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/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1256383544
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.869635241
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1812987135



Total test records in report: 2913
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.3453761309 Oct 12 07:45:25 PM UTC 24 Oct 12 07:48:32 PM UTC 24 3160920460 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2239076611 Oct 12 07:45:29 PM UTC 24 Oct 12 07:48:43 PM UTC 24 3001179692 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.1744265087 Oct 12 07:46:44 PM UTC 24 Oct 12 07:49:12 PM UTC 24 3111886680 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1014747965 Oct 12 07:46:08 PM UTC 24 Oct 12 07:49:29 PM UTC 24 3171996751 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3343052839 Oct 12 07:46:53 PM UTC 24 Oct 12 07:50:15 PM UTC 24 3027552164 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.1282885611 Oct 12 07:47:31 PM UTC 24 Oct 12 07:50:23 PM UTC 24 3049333168 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.1732488876 Oct 12 07:49:25 PM UTC 24 Oct 12 07:51:28 PM UTC 24 2303762260 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3106200272 Oct 12 07:48:37 PM UTC 24 Oct 12 07:51:30 PM UTC 24 2730150242 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.2399912598 Oct 12 07:48:19 PM UTC 24 Oct 12 07:51:54 PM UTC 24 3205636792 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.1831919827 Oct 12 07:47:57 PM UTC 24 Oct 12 07:52:15 PM UTC 24 3494308248 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.263102061 Oct 12 07:48:26 PM UTC 24 Oct 12 07:52:23 PM UTC 24 2690447050 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1766272641 Oct 12 07:47:10 PM UTC 24 Oct 12 07:53:01 PM UTC 24 4615308580 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2814200302 Oct 12 07:48:18 PM UTC 24 Oct 12 07:53:15 PM UTC 24 3313624728 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.1648702096 Oct 12 07:49:24 PM UTC 24 Oct 12 07:53:29 PM UTC 24 3065172306 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3603499215 Oct 12 07:48:37 PM UTC 24 Oct 12 07:53:31 PM UTC 24 2980362404 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.777043962 Oct 12 07:50:29 PM UTC 24 Oct 12 07:54:14 PM UTC 24 4271862204 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2885026929 Oct 12 07:51:01 PM UTC 24 Oct 12 07:54:19 PM UTC 24 3916282582 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1860735384 Oct 12 07:48:09 PM UTC 24 Oct 12 07:54:45 PM UTC 24 4040404461 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1793282983 Oct 12 07:51:01 PM UTC 24 Oct 12 07:54:50 PM UTC 24 3636612056 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.380277608 Oct 12 07:52:57 PM UTC 24 Oct 12 07:54:52 PM UTC 24 2367224541 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.1981276026 Oct 12 07:46:23 PM UTC 24 Oct 12 07:54:57 PM UTC 24 5632395420 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4198908130 Oct 12 07:53:00 PM UTC 24 Oct 12 07:55:05 PM UTC 24 2484371613 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2392646852 Oct 12 07:50:25 PM UTC 24 Oct 12 07:55:29 PM UTC 24 2814059029 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.567637733 Oct 12 07:47:42 PM UTC 24 Oct 12 07:55:31 PM UTC 24 4312477069 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3051856053 Oct 12 07:47:42 PM UTC 24 Oct 12 07:56:17 PM UTC 24 3886641272 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2165358261 Oct 12 07:47:31 PM UTC 24 Oct 12 07:56:24 PM UTC 24 3990014891 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.941616459 Oct 12 07:50:20 PM UTC 24 Oct 12 07:56:27 PM UTC 24 3306685488 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.4050815144 Oct 12 07:50:28 PM UTC 24 Oct 12 07:56:31 PM UTC 24 3615753640 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.959849323 Oct 12 07:50:06 PM UTC 24 Oct 12 07:56:51 PM UTC 24 6791434950 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.511603057 Oct 12 07:48:13 PM UTC 24 Oct 12 07:56:51 PM UTC 24 4251986638 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.194521527 Oct 12 07:50:21 PM UTC 24 Oct 12 07:56:54 PM UTC 24 3596120883 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.235391717 Oct 12 07:50:29 PM UTC 24 Oct 12 07:57:07 PM UTC 24 4119267888 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2856674397 Oct 12 07:48:37 PM UTC 24 Oct 12 07:57:19 PM UTC 24 4202997968 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.4061273428 Oct 12 07:48:36 PM UTC 24 Oct 12 07:57:21 PM UTC 24 6157736642 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1535320495 Oct 12 07:48:13 PM UTC 24 Oct 12 07:57:36 PM UTC 24 4389049420 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.1815159956 Oct 12 07:47:56 PM UTC 24 Oct 12 07:57:50 PM UTC 24 4791749794 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.1831516269 Oct 12 07:49:53 PM UTC 24 Oct 12 07:58:00 PM UTC 24 4360219082 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.1746757906 Oct 12 07:49:50 PM UTC 24 Oct 12 07:58:09 PM UTC 24 3863689400 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.44446760 Oct 12 07:48:37 PM UTC 24 Oct 12 07:58:10 PM UTC 24 4166769900 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.804051412 Oct 12 07:49:44 PM UTC 24 Oct 12 07:58:35 PM UTC 24 4110082120 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.1343788695 Oct 12 07:48:16 PM UTC 24 Oct 12 07:58:36 PM UTC 24 4440798464 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.3772263642 Oct 12 07:50:20 PM UTC 24 Oct 12 07:58:44 PM UTC 24 4108901896 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.3435526436 Oct 12 07:54:13 PM UTC 24 Oct 12 07:59:04 PM UTC 24 2726818344 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.1618487750 Oct 12 07:50:06 PM UTC 24 Oct 12 07:59:29 PM UTC 24 5237724840 ps
T685 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.249351851 Oct 12 07:54:12 PM UTC 24 Oct 12 07:59:46 PM UTC 24 3496374232 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1179649634 Oct 12 07:48:16 PM UTC 24 Oct 12 07:59:57 PM UTC 24 4686316760 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_descrambling.1744157012 Oct 12 07:50:22 PM UTC 24 Oct 12 08:00:18 PM UTC 24 4392607520 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3217060972 Oct 12 07:56:00 PM UTC 24 Oct 12 08:00:41 PM UTC 24 3454517532 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1372259565 Oct 12 07:50:25 PM UTC 24 Oct 12 08:01:30 PM UTC 24 4246900982 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.2127910968 Oct 12 07:48:12 PM UTC 24 Oct 12 08:01:43 PM UTC 24 5062640112 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1862774583 Oct 12 07:56:25 PM UTC 24 Oct 12 08:03:02 PM UTC 24 7410701244 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2999916001 Oct 12 07:47:44 PM UTC 24 Oct 12 08:03:02 PM UTC 24 7749947791 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3876353262 Oct 12 07:50:04 PM UTC 24 Oct 12 08:03:13 PM UTC 24 4717555720 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2939686279 Oct 12 07:58:51 PM UTC 24 Oct 12 08:03:18 PM UTC 24 3125385734 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.294240155 Oct 12 07:58:37 PM UTC 24 Oct 12 08:04:14 PM UTC 24 6066652446 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1067366325 Oct 12 07:48:41 PM UTC 24 Oct 12 08:04:38 PM UTC 24 5667721675 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.455166337 Oct 12 07:58:50 PM UTC 24 Oct 12 08:04:57 PM UTC 24 3257371745 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3542688893 Oct 12 07:48:10 PM UTC 24 Oct 12 08:05:01 PM UTC 24 7895516332 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3163782837 Oct 12 07:48:10 PM UTC 24 Oct 12 08:05:13 PM UTC 24 6190360951 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.4053602310 Oct 12 07:52:31 PM UTC 24 Oct 12 08:05:27 PM UTC 24 9104985044 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.3840929699 Oct 12 08:00:53 PM UTC 24 Oct 12 08:05:39 PM UTC 24 2487539424 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.768414914 Oct 12 07:49:57 PM UTC 24 Oct 12 08:06:08 PM UTC 24 5571955560 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.356715601 Oct 12 07:48:08 PM UTC 24 Oct 12 08:06:33 PM UTC 24 7790174170 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.2977225317 Oct 12 08:00:43 PM UTC 24 Oct 12 08:07:11 PM UTC 24 4629864296 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1576567746 Oct 12 08:00:07 PM UTC 24 Oct 12 08:07:35 PM UTC 24 5418128558 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1905655254 Oct 12 08:04:09 PM UTC 24 Oct 12 08:07:38 PM UTC 24 2522920607 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1441776472 Oct 12 07:57:56 PM UTC 24 Oct 12 08:07:42 PM UTC 24 6477029664 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.4124369694 Oct 12 08:04:10 PM UTC 24 Oct 12 08:07:48 PM UTC 24 2697839824 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3310278078 Oct 12 08:00:37 PM UTC 24 Oct 12 08:08:12 PM UTC 24 3797781366 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3473122721 Oct 12 08:00:19 PM UTC 24 Oct 12 08:08:33 PM UTC 24 4159918400 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.1461393223 Oct 12 07:47:00 PM UTC 24 Oct 12 08:08:57 PM UTC 24 8686611400 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.2250377034 Oct 12 08:04:12 PM UTC 24 Oct 12 08:08:59 PM UTC 24 3328401582 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1254580426 Oct 12 08:00:37 PM UTC 24 Oct 12 08:09:01 PM UTC 24 3900893320 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3104483871 Oct 12 07:55:03 PM UTC 24 Oct 12 08:09:10 PM UTC 24 6531844072 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2078605229 Oct 12 08:00:42 PM UTC 24 Oct 12 08:09:20 PM UTC 24 6613801640 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.624965865 Oct 12 08:04:49 PM UTC 24 Oct 12 08:09:22 PM UTC 24 3092957046 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.257796529 Oct 12 08:00:41 PM UTC 24 Oct 12 08:09:31 PM UTC 24 4464453484 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.2765355017 Oct 12 08:04:13 PM UTC 24 Oct 12 08:09:49 PM UTC 24 3345609736 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1312483618 Oct 12 07:49:54 PM UTC 24 Oct 12 08:10:02 PM UTC 24 8499088640 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.614509377 Oct 12 08:02:05 PM UTC 24 Oct 12 08:10:21 PM UTC 24 4152680472 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3815692312 Oct 12 08:01:01 PM UTC 24 Oct 12 08:10:32 PM UTC 24 19431384272 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.3985429622 Oct 12 07:47:45 PM UTC 24 Oct 12 08:11:40 PM UTC 24 8571072140 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2334123709 Oct 12 08:00:37 PM UTC 24 Oct 12 08:11:47 PM UTC 24 5231565448 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.2652755300 Oct 12 08:07:48 PM UTC 24 Oct 12 08:12:12 PM UTC 24 2785930056 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.155993136 Oct 12 08:00:03 PM UTC 24 Oct 12 08:12:34 PM UTC 24 8050335140 ps
T691 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4023334128 Oct 12 08:00:15 PM UTC 24 Oct 12 08:12:47 PM UTC 24 9503242056 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1861379536 Oct 12 08:06:17 PM UTC 24 Oct 12 08:12:50 PM UTC 24 3918415276 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.3391380315 Oct 12 08:06:05 PM UTC 24 Oct 12 08:13:05 PM UTC 24 4799865064 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.3347870672 Oct 12 08:07:10 PM UTC 24 Oct 12 08:13:28 PM UTC 24 3093203565 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3395766760 Oct 12 08:08:48 PM UTC 24 Oct 12 08:13:40 PM UTC 24 3095696384 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1181673501 Oct 12 08:10:15 PM UTC 24 Oct 12 08:13:47 PM UTC 24 2828003370 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3748033658 Oct 12 07:48:41 PM UTC 24 Oct 12 08:14:37 PM UTC 24 8485040789 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.947152675 Oct 12 07:47:55 PM UTC 24 Oct 12 08:14:54 PM UTC 24 8266452512 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1819407530 Oct 12 07:56:31 PM UTC 24 Oct 12 08:15:04 PM UTC 24 12096690038 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.2475728737 Oct 12 08:11:25 PM UTC 24 Oct 12 08:15:26 PM UTC 24 2454380852 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.4085445022 Oct 12 08:05:48 PM UTC 24 Oct 12 08:15:27 PM UTC 24 4904362228 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.3694116622 Oct 12 08:01:00 PM UTC 24 Oct 12 08:15:43 PM UTC 24 5983729994 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.2496176796 Oct 12 08:11:24 PM UTC 24 Oct 12 08:15:52 PM UTC 24 3523764642 ps
T686 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.4041713669 Oct 12 08:11:21 PM UTC 24 Oct 12 08:16:00 PM UTC 24 2880006500 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.4108019018 Oct 12 08:08:55 PM UTC 24 Oct 12 08:16:42 PM UTC 24 3310992112 ps
T687 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.288481101 Oct 12 08:11:24 PM UTC 24 Oct 12 08:16:50 PM UTC 24 2880175468 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.2089186453 Oct 12 08:11:23 PM UTC 24 Oct 12 08:17:03 PM UTC 24 3299098500 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1303269031 Oct 12 07:55:59 PM UTC 24 Oct 12 08:17:14 PM UTC 24 7887556292 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3230274334 Oct 12 08:10:15 PM UTC 24 Oct 12 08:17:19 PM UTC 24 3768768900 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.3162708058 Oct 12 08:14:12 PM UTC 24 Oct 12 08:17:49 PM UTC 24 2695622904 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.530409064 Oct 12 07:56:32 PM UTC 24 Oct 12 08:18:00 PM UTC 24 17449430687 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.993286752 Oct 12 08:03:11 PM UTC 24 Oct 12 08:18:02 PM UTC 24 5042170440 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.1759996516 Oct 12 07:55:02 PM UTC 24 Oct 12 08:18:18 PM UTC 24 9164599080 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.1230939368 Oct 12 08:02:20 PM UTC 24 Oct 12 08:18:44 PM UTC 24 5886642688 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.728092025 Oct 12 08:15:14 PM UTC 24 Oct 12 08:18:44 PM UTC 24 2997197124 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.1198615536 Oct 12 07:46:59 PM UTC 24 Oct 12 08:18:58 PM UTC 24 23913015560 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2902827859 Oct 12 08:14:28 PM UTC 24 Oct 12 08:19:11 PM UTC 24 3044371569 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.1416089271 Oct 12 08:15:40 PM UTC 24 Oct 12 08:19:55 PM UTC 24 2921489184 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.3124486145 Oct 12 08:09:09 PM UTC 24 Oct 12 08:19:59 PM UTC 24 3458999068 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.876736605 Oct 12 08:14:27 PM UTC 24 Oct 12 08:20:06 PM UTC 24 2780357442 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.980665719 Oct 12 08:09:13 PM UTC 24 Oct 12 08:21:43 PM UTC 24 6740835495 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.3439968980 Oct 12 08:17:37 PM UTC 24 Oct 12 08:21:52 PM UTC 24 3037304482 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.3249366034 Oct 12 08:18:58 PM UTC 24 Oct 12 08:23:30 PM UTC 24 3203731032 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3020875502 Oct 12 08:15:43 PM UTC 24 Oct 12 08:23:46 PM UTC 24 9249457552 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3147385080 Oct 12 08:16:49 PM UTC 24 Oct 12 08:25:06 PM UTC 24 7087814048 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3991316311 Oct 12 08:16:46 PM UTC 24 Oct 12 08:25:14 PM UTC 24 4076591399 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2920374202 Oct 12 08:17:56 PM UTC 24 Oct 12 08:25:36 PM UTC 24 5376509702 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1092076076 Oct 12 07:56:27 PM UTC 24 Oct 12 08:25:48 PM UTC 24 11898578071 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.941395816 Oct 12 08:10:59 PM UTC 24 Oct 12 08:25:51 PM UTC 24 5649876620 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2747727633 Oct 12 08:19:37 PM UTC 24 Oct 12 08:26:13 PM UTC 24 4241594580 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3356285261 Oct 12 08:16:41 PM UTC 24 Oct 12 08:26:48 PM UTC 24 4963597438 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3814810821 Oct 12 08:19:52 PM UTC 24 Oct 12 08:27:06 PM UTC 24 4669544516 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.732927871 Oct 12 08:11:20 PM UTC 24 Oct 12 08:27:26 PM UTC 24 6570790104 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.369744986 Oct 12 08:19:53 PM UTC 24 Oct 12 08:27:57 PM UTC 24 4871638800 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.1367588960 Oct 12 08:08:58 PM UTC 24 Oct 12 08:28:00 PM UTC 24 4983851100 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2722517590 Oct 12 08:16:47 PM UTC 24 Oct 12 08:28:10 PM UTC 24 9302044616 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.349991354 Oct 12 08:18:59 PM UTC 24 Oct 12 08:28:25 PM UTC 24 4350100250 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1468488368 Oct 12 08:06:16 PM UTC 24 Oct 12 08:28:53 PM UTC 24 7647563448 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2602784682 Oct 12 08:00:10 PM UTC 24 Oct 12 08:29:37 PM UTC 24 21981362554 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.511869421 Oct 12 08:20:50 PM UTC 24 Oct 12 08:29:43 PM UTC 24 4306013156 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.108257541 Oct 12 08:16:50 PM UTC 24 Oct 12 08:29:51 PM UTC 24 6753468308 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.212047374 Oct 12 08:26:34 PM UTC 24 Oct 12 08:30:33 PM UTC 24 2302243047 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4097441517 Oct 12 08:20:53 PM UTC 24 Oct 12 08:31:00 PM UTC 24 4029611578 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.3889327675 Oct 12 08:08:56 PM UTC 24 Oct 12 08:31:02 PM UTC 24 6894583810 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.1024752412 Oct 12 08:11:20 PM UTC 24 Oct 12 08:31:18 PM UTC 24 5811564978 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.127074617 Oct 12 08:22:31 PM UTC 24 Oct 12 08:32:03 PM UTC 24 4249341212 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.2115067892 Oct 12 08:18:58 PM UTC 24 Oct 12 08:32:08 PM UTC 24 4320779768 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2594991148 Oct 12 08:06:16 PM UTC 24 Oct 12 08:33:12 PM UTC 24 12781369776 ps
T701 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.3705279544 Oct 12 08:25:53 PM UTC 24 Oct 12 08:33:24 PM UTC 24 3739965704 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.802641606 Oct 12 07:46:26 PM UTC 24 Oct 12 08:33:30 PM UTC 24 12192716658 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2187427352 Oct 12 08:06:45 PM UTC 24 Oct 12 08:33:36 PM UTC 24 7686520500 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.3042980342 Oct 12 08:17:35 PM UTC 24 Oct 12 08:33:58 PM UTC 24 8183906604 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1707925439 Oct 12 08:26:33 PM UTC 24 Oct 12 08:34:51 PM UTC 24 3451953384 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3419745026 Oct 12 08:22:31 PM UTC 24 Oct 12 08:35:20 PM UTC 24 4270468632 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.367323709 Oct 12 08:18:53 PM UTC 24 Oct 12 08:35:26 PM UTC 24 6057378672 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.876110102 Oct 12 08:32:37 PM UTC 24 Oct 12 08:35:31 PM UTC 24 2900610959 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.3137002635 Oct 12 08:31:47 PM UTC 24 Oct 12 08:35:35 PM UTC 24 2354547702 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.663004527 Oct 12 07:53:50 PM UTC 24 Oct 12 08:35:45 PM UTC 24 36672894018 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3621930235 Oct 12 08:24:22 PM UTC 24 Oct 12 08:35:51 PM UTC 24 4111215548 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3283017725 Oct 12 08:29:13 PM UTC 24 Oct 12 08:36:06 PM UTC 24 4139827808 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2683956827 Oct 12 08:26:35 PM UTC 24 Oct 12 08:36:14 PM UTC 24 4223484048 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.4174213775 Oct 12 08:32:38 PM UTC 24 Oct 12 08:36:19 PM UTC 24 2675840353 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1731409677 Oct 12 08:27:59 PM UTC 24 Oct 12 08:36:31 PM UTC 24 4043508834 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.2767088908 Oct 12 08:30:36 PM UTC 24 Oct 12 08:37:14 PM UTC 24 4767200408 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3298574220 Oct 12 08:31:38 PM UTC 24 Oct 12 08:37:21 PM UTC 24 4343611571 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2742312912 Oct 12 08:29:10 PM UTC 24 Oct 12 08:37:22 PM UTC 24 7085190894 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.616275960 Oct 12 08:25:52 PM UTC 24 Oct 12 08:37:33 PM UTC 24 5593386440 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2593177965 Oct 12 08:29:29 PM UTC 24 Oct 12 08:37:36 PM UTC 24 6807458640 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4035136156 Oct 12 08:20:51 PM UTC 24 Oct 12 08:37:37 PM UTC 24 10352328272 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2280491234 Oct 12 07:56:14 PM UTC 24 Oct 12 08:37:37 PM UTC 24 19891584983 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3946624435 Oct 12 08:31:10 PM UTC 24 Oct 12 08:37:59 PM UTC 24 6024930120 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.334882684 Oct 12 08:13:49 PM UTC 24 Oct 12 08:37:59 PM UTC 24 8080725570 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4276835824 Oct 12 08:24:07 PM UTC 24 Oct 12 08:38:00 PM UTC 24 5460395872 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1112119593 Oct 12 08:33:47 PM UTC 24 Oct 12 08:38:11 PM UTC 24 2797255040 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.954478872 Oct 12 08:06:20 PM UTC 24 Oct 12 08:38:22 PM UTC 24 8660506512 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3423938345 Oct 12 08:34:19 PM UTC 24 Oct 12 08:38:50 PM UTC 24 2534583477 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.3977330794 Oct 12 08:34:32 PM UTC 24 Oct 12 08:39:23 PM UTC 24 2593132258 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.701271456 Oct 12 08:30:37 PM UTC 24 Oct 12 08:39:36 PM UTC 24 5113840018 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.503452313 Oct 12 08:37:27 PM UTC 24 Oct 12 08:40:07 PM UTC 24 2971382929 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.38134768 Oct 12 08:30:36 PM UTC 24 Oct 12 08:40:27 PM UTC 24 5963649288 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.3141291462 Oct 12 08:27:43 PM UTC 24 Oct 12 08:40:36 PM UTC 24 7030018904 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.1604297652 Oct 12 08:13:49 PM UTC 24 Oct 12 08:40:45 PM UTC 24 8760211158 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2408337247 Oct 12 08:37:32 PM UTC 24 Oct 12 08:41:17 PM UTC 24 2690688243 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.1040373697 Oct 12 08:35:28 PM UTC 24 Oct 12 08:41:34 PM UTC 24 2713005674 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2947963127 Oct 12 08:37:38 PM UTC 24 Oct 12 08:42:04 PM UTC 24 3268142455 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1661300465 Oct 12 08:37:38 PM UTC 24 Oct 12 08:42:15 PM UTC 24 3205901379 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4098578606 Oct 12 08:31:41 PM UTC 24 Oct 12 08:43:04 PM UTC 24 5195387385 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.4016090674 Oct 12 08:12:27 PM UTC 24 Oct 12 08:44:18 PM UTC 24 8425992520 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.846908424 Oct 12 08:34:36 PM UTC 24 Oct 12 08:44:47 PM UTC 24 6121499000 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.835014045 Oct 12 08:19:47 PM UTC 24 Oct 12 08:44:49 PM UTC 24 13090011320 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2493255543 Oct 12 08:42:26 PM UTC 24 Oct 12 08:45:24 PM UTC 24 2773184046 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3107194263 Oct 12 08:36:38 PM UTC 24 Oct 12 08:46:29 PM UTC 24 5338002638 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.2962594855 Oct 12 08:39:02 PM UTC 24 Oct 12 08:46:58 PM UTC 24 11020734860 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2608467906 Oct 12 08:26:35 PM UTC 24 Oct 12 08:47:33 PM UTC 24 12757410828 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2659255276 Oct 12 08:39:24 PM UTC 24 Oct 12 08:47:36 PM UTC 24 5080432852 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.2503293567 Oct 12 08:40:24 PM UTC 24 Oct 12 08:51:06 PM UTC 24 4318864936 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2840699429 Oct 12 08:29:10 PM UTC 24 Oct 12 08:51:32 PM UTC 24 21127717204 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1759519306 Oct 12 08:27:12 PM UTC 24 Oct 12 08:52:01 PM UTC 24 14385321112 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1999552928 Oct 12 08:37:06 PM UTC 24 Oct 12 08:55:03 PM UTC 24 6817528753 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1201338793 Oct 12 08:00:28 PM UTC 24 Oct 12 08:59:33 PM UTC 24 20465504435 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1490138637 Oct 12 08:41:33 PM UTC 24 Oct 12 09:00:14 PM UTC 24 5636336784 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1426445834 Oct 12 08:29:10 PM UTC 24 Oct 12 09:00:18 PM UTC 24 24530664472 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3928046298 Oct 12 08:41:39 PM UTC 24 Oct 12 09:04:39 PM UTC 24 5672465992 ps
T925 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2647252054 Oct 12 07:45:18 PM UTC 24 Oct 12 09:08:56 PM UTC 24 18815332200 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3493202671 Oct 12 08:37:37 PM UTC 24 Oct 12 09:10:58 PM UTC 24 17293294009 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.437738755 Oct 12 08:01:01 PM UTC 24 Oct 12 09:13:13 PM UTC 24 17752848334 ps
T926 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4136872589 Oct 12 08:18:01 PM UTC 24 Oct 12 09:13:36 PM UTC 24 32625754204 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.424012931 Oct 12 08:01:17 PM UTC 24 Oct 12 09:18:49 PM UTC 24 18026950521 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.2455754983 Oct 12 07:49:53 PM UTC 24 Oct 12 09:19:22 PM UTC 24 45107400223 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.3243167892 Oct 12 08:13:49 PM UTC 24 Oct 12 09:23:28 PM UTC 24 14860161612 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1030113040 Oct 12 09:24:06 PM UTC 24 Oct 12 09:27:06 PM UTC 24 2746559456 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1349864276 Oct 12 08:37:33 PM UTC 24 Oct 12 09:27:29 PM UTC 24 15393633706 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3570088346 Oct 12 09:27:44 PM UTC 24 Oct 12 09:32:11 PM UTC 24 5899735227 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1404285639 Oct 12 08:43:11 PM UTC 24 Oct 12 09:36:26 PM UTC 24 11082305354 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2056614216 Oct 12 09:00:55 PM UTC 24 Oct 12 09:37:27 PM UTC 24 10913209069 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3519395820 Oct 12 08:48:59 PM UTC 24 Oct 12 09:38:06 PM UTC 24 11948071000 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.2249413203 Oct 12 09:05:13 PM UTC 24 Oct 12 09:39:13 PM UTC 24 11094433571 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.4207966446 Oct 12 07:49:26 PM UTC 24 Oct 12 09:39:40 PM UTC 24 26873469938 ps
T928 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3929089396 Oct 12 09:00:54 PM UTC 24 Oct 12 09:40:21 PM UTC 24 10218982792 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2025342125 Oct 12 08:49:11 PM UTC 24 Oct 12 09:40:27 PM UTC 24 11866993086 ps
T929 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2534465450 Oct 12 09:32:40 PM UTC 24 Oct 12 09:41:58 PM UTC 24 4705185264 ps
T930 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.3963023364 Oct 12 09:37:03 PM UTC 24 Oct 12 09:42:10 PM UTC 24 2785525140 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.3160497186 Oct 12 09:38:42 PM UTC 24 Oct 12 09:42:47 PM UTC 24 2527645512 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.2510785209 Oct 12 09:39:50 PM UTC 24 Oct 12 09:43:57 PM UTC 24 2672555098 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.1687693861 Oct 12 09:38:04 PM UTC 24 Oct 12 09:44:10 PM UTC 24 2797933704 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3891189966 Oct 12 07:53:38 PM UTC 24 Oct 12 09:45:22 PM UTC 24 45939540658 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.807498477 Oct 12 08:45:37 PM UTC 24 Oct 12 09:45:43 PM UTC 24 11918215412 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.1416277945 Oct 12 07:52:16 PM UTC 24 Oct 12 09:45:49 PM UTC 24 50825751528 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.4107953232 Oct 12 09:41:06 PM UTC 24 Oct 12 09:46:30 PM UTC 24 2336405428 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.2304405702 Oct 12 08:41:38 PM UTC 24 Oct 12 09:46:43 PM UTC 24 30313243427 ps
T934 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.567470192 Oct 12 09:41:06 PM UTC 24 Oct 12 09:47:21 PM UTC 24 2406309684 ps
T935 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2466039605 Oct 12 08:52:40 PM UTC 24 Oct 12 09:47:58 PM UTC 24 11873083563 ps
T936 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.3694864789 Oct 12 09:43:24 PM UTC 24 Oct 12 09:48:06 PM UTC 24 3261747212 ps
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T938 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.4149711523 Oct 12 08:41:49 PM UTC 24 Oct 12 09:48:29 PM UTC 24 15296261062 ps
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T941 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2896245683 Oct 12 09:48:35 PM UTC 24 Oct 12 09:50:54 PM UTC 24 2416432226 ps
T942 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1841919785 Oct 12 08:43:24 PM UTC 24 Oct 12 09:50:54 PM UTC 24 15337003424 ps
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T944 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.1974509652 Oct 12 09:46:31 PM UTC 24 Oct 12 09:51:28 PM UTC 24 2746500590 ps
T945 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.1164696957 Oct 12 08:41:15 PM UTC 24 Oct 12 09:51:41 PM UTC 24 15228155266 ps
T946 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.4030436347 Oct 12 09:47:20 PM UTC 24 Oct 12 09:51:47 PM UTC 24 3300461780 ps
T947 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4214780542 Oct 12 08:52:14 PM UTC 24 Oct 12 09:51:47 PM UTC 24 13842414055 ps
T948 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.3760231971 Oct 12 09:47:58 PM UTC 24 Oct 12 09:52:08 PM UTC 24 3212582128 ps
T949 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1188645789 Oct 12 08:48:51 PM UTC 24 Oct 12 09:52:19 PM UTC 24 14601613864 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3708535947 Oct 12 09:44:47 PM UTC 24 Oct 12 09:52:49 PM UTC 24 5433259416 ps
T950 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.2206156006 Oct 12 09:48:50 PM UTC 24 Oct 12 09:53:07 PM UTC 24 3239669432 ps
T951 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2376240728 Oct 12 09:48:51 PM UTC 24 Oct 12 09:53:13 PM UTC 24 2825819036 ps
T952 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1799645698 Oct 12 08:49:53 PM UTC 24 Oct 12 09:53:41 PM UTC 24 15192715950 ps
T953 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1073848497 Oct 12 09:49:16 PM UTC 24 Oct 12 09:53:52 PM UTC 24 3559721928 ps
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