Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3757	1			T454	1		T431	1		T555	6
all_values[1]	3696	1			T430	2		T431	4		T555	6
all_values[2]	3666	1			T430	3		T431	3		T555	7
all_values[3]	3758	1			T430	1		T454	5		T431	1
all_values[4]	3771	1			T430	1		T454	1		T431	1
all_values[5]	3854	1			T430	4		T454	2		T431	1
all_values[6]	3693	1			T430	1		T454	1		T431	1
all_values[7]	3667	1			T430	1		T454	1		T431	1
all_values[8]	3643	1			T430	5		T454	2		T555	7
all_values[9]	3786	1			T430	3		T454	2		T431	1
all_values[10]	3675	1			T430	4		T454	1		T431	2
all_values[11]	3600	1			T430	3		T454	1		T431	3
all_values[12]	3689	1			T430	1		T454	1		T555	6
all_values[13]	3698	1			T454	2		T431	2		T555	7
all_values[14]	3781	1			T430	1		T454	1		T431	1
all_values[15]	3776	1			T430	2		T454	2		T431	1
all_values[16]	3633	1			T430	4		T431	2		T555	1
all_values[17]	3784	1			T430	1		T454	1		T431	1
all_values[18]	3841	1			T430	1		T454	3		T431	1
all_values[19]	3758	1			T430	2		T454	2		T431	1
all_values[20]	3767	1			T430	5		T454	2		T555	7
all_values[21]	3778	1			T430	2		T431	4		T555	6
all_values[22]	3713	1			T430	2		T454	3		T431	2
all_values[23]	3684	1			T430	1		T454	3		T555	7
all_values[24]	3739	1			T430	3		T454	1		T431	2
all_values[25]	3725	1			T430	1		T431	2		T555	6
all_values[26]	3726	1			T430	3		T454	2		T431	2
all_values[27]	3740	1			T430	3		T454	4		T431	3
all_values[28]	3606	1			T430	3		T454	4		T555	15
all_values[29]	3684	1			T430	1		T454	1		T431	2
all_values[30]	3588	1			T454	1		T431	1		T555	6
all_values[31]	3728	1			T430	2		T454	3		T431	1
all_values[32]	3763	1			T430	3		T454	1		T431	4
all_values[33]	3726	1			T430	1		T454	2		T431	2
all_values[34]	3705	1			T430	2		T454	1		T431	2
all_values[35]	3742	1			T454	3		T431	3		T555	9
all_values[36]	3744	1			T454	1		T431	1		T555	4
all_values[37]	3711	1			T430	2		T454	2		T431	1
all_values[38]	3748	1			T430	4		T454	1		T431	2
all_values[39]	3710	1			T430	2		T431	4		T555	3
all_values[40]	3763	1			T430	4		T454	1		T431	3
all_values[41]	3801	1			T430	4		T454	3		T431	2
all_values[42]	3788	1			T430	1		T454	4		T431	2
all_values[43]	3786	1			T430	3		T431	1		T555	7
all_values[44]	3754	1			T430	2		T431	1		T555	4
all_values[45]	3655	1			T430	1		T454	2		T431	3
all_values[46]	3814	1			T430	3		T454	1		T431	2
all_values[47]	3801	1			T430	5		T431	3		T555	10
all_values[48]	3710	1			T454	2		T431	1		T555	1
all_values[49]	3878	1			T430	1		T454	3		T555	4
all_values[50]	3826	1			T454	1		T555	6		T463	1
all_values[51]	3660	1			T430	3		T431	1		T555	3
all_values[52]	3742	1			T430	1		T454	4		T431	1
all_values[53]	3861	1			T430	1		T431	1		T555	7
all_values[54]	3825	1			T430	1		T454	3		T431	2
all_values[55]	3806	1			T454	1		T431	3		T555	7
all_values[56]	3680	1			T454	1		T431	2		T555	7
all_values[57]	3891	1			T430	7		T454	1		T431	2
all_values[58]	3735	1			T430	1		T431	3		T555	5
all_values[59]	3838	1			T430	4		T454	1		T555	7
all_values[60]	3721	1			T431	2		T555	9		T463	2
all_values[61]	3779	1			T454	2		T431	2		T555	4
all_values[62]	3719	1			T430	1		T454	2		T431	1
all_values[63]	3657	1			T430	3		T454	2		T431	3