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 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T68,T213,T448
1	0	1	Covered	T73,T75,T214
1	1	0	Covered	T456,T548,T561
1	1	1	Covered	T73,T75,T76

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T75,T76
1	0	1	Covered	T73,T75,T214
1	1	0	Covered	T558,T475,T584
1	1	1	Covered	T448,T131,T674

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T73,T75,T76
1	0	1	Covered	T73,T287,T278
1	1	0	Covered	T430,T455,T456
1	1	1	Covered	T234,T430,T438

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T451,T455,T438
1	1	0	Covered	T675,T676
1	1	1	Covered	T25,T7,T4

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T234,T451,T559
1	1	0	Covered	T677,T678
1	1	1	Covered	T25,T7,T4

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T25,T7,T4
1	0	1	Covered	T91,T451,T454
1	1	0	Covered	T679,T680
1	1	1	Covered	T1,T2,T3