Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T124 T125 T319 | T124 T125 T319 | T124 T125 T319 | T124 T125 T319 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T124 T125 T319 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T126 T127 T128 | T37 T319 T38 | T37 T319 T38 | T37 T319 T38 | T37 T319 T38 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T37 T319 T38 | T39 T319 T40 | T39 T319 T40 | T39 T319 T40 | T39 T319 T40 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T39 T319 T40 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T8 T122 T215 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T19 T122 T20 | T122 T178 T179 | T122 T178 T179 | T31 T325 T32 | T31 T325 T32 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T31 T325 T32 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T36 T325 T133 | T36 T325 T133 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T35 T36 T325 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T122 T178 T179 | T5 T122 T130 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T76 T231 T348 | T73 T75 T214 | T325 T329 T326 | T181 T325 T330 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T43 T319 T224 | T134 T325 T331 | T332 T254 T325 | T253 T254 T348 | T169 T122 T333 | T122 T178 T179 | T118 T140 T320 | T118 T140 T320 | T140 T320 T325 | T140 T320 T325 | T118 T140 T320 | T325 T326 T327 | T321 T322 T325 | T325 T326 T327 | T325 T326 T327 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T154 T122 T171 | T122 T178 T179 | T325 T326 T327 | T317 T325 T326 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T317 T325 T326 | T325 T326 T327 | T317 T325 T326 | T325 T326 T327
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T265 T266 T318 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T19 | T19 T265 T122 | T19 T265 T122 | T8 T19 T9 | T8 T19 T9 | T19 T265 T122 | T265 T122 T319 | T265 T122 T319 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T31 T265 T122 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T265 T122 T319 | T33 T265 T122 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T36 T265 T122 | T36 T265 T122 | T265 T122 T319 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T265 T122 T319 | T35 T36 T265 | T35 T265 T122 | T265 T122 T319 | T35 T265 T122 | T35 T265 T122 | T35 T265 T122 | T5 T265 T122 | T5 T265 T122 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T73 T75 T76 | T73 T75 T76 | T73 T75 T76 | T73 T75 T76 | T8 T9 T265 | T8 T9 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T25 T4 T6 | T43 T265 T122 | T134 T265 T122 | T73 T75 T76 | T73 T253 T75 | T169 T265 T122 | T265 T122 T319 | T118 T140 T320 | T118 T140 T320 | T118 T140 T320 | T118 T140 T320 | T118 T140 T320 | T265 T122 T319 | T321 T322 T265 | T321 T322 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T154 T265 T122 | T265 T122 T319 | T265 T122 T319 | T265 T122 T317 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T317 | T265 T122 T319 | T265 T122 T317 | T265 T122 T319
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T4 T5 T6 | T5 T28 T8 | T28 T39 T126 | T5 T28 T8 | T4 T6 T26 | T39 T126 T124 | T28 T39 T265 | T28 T8 T19 | T5 T76 T35 | T4 T6 T26 | T118 T140 T320 | T126 T124 T127 | T39 T126 T37 | T28 T39 T265 | T28 T265 T122 | T28 T8 T19 | T31 T33 T265 | T36 T33 T265 | T5 T76 T35 | T73 T75 T76 | T4 T6 T26 | T118 T140 T320 | T265 T122 T317 | T124 T125 T265 | T126 T124 T127 | T126 T37 T127 | T39 T37 T265 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T265 | T8 T19 T9 | T31 T265 T122 | T33 T265 T122 | T33 T265 T122 | T36 T265 T122 | T35 T36 T265 | T5 T76 T35 | T73 T8 T9 | T265 T122 T319 | T265 T122 T319 | T4 T6 T26 | T118 T140 T320 | T154 T265 T122 | T265 T122 T317 | T124 T125 T265 | T124 T125 T265 | T126 T124 T127 | T126 T127 T128 | T126 T37 T127 | T37 T265 T122 | T37 T265 T122 | T39 T265 T122 | T39 T265 T122 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T19 | T8 T19 T9 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T35 T36 T265 | T5 T35 T265 | T76 T231 T348 | T73 T75 T76 | T8 T9 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T4 T6 T26 | T73 T253 T75 | T118 T140 T320 | T118 T140 T320 | T265 T122 T319 | T154 T265 T122 | T265 T122 T319 | T265 T122 T317 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T37 T127 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T19 | T19 T265 T122 | T8 T19 T9 | T19 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T265 T122 T319 | T265 T122 T319 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T35 T36 T265 | T35 T265 T122 | T35 T265 T122 | T5 T265 T122 | T265 T122 T319 | T73 T75 T76 | T73 T75 T76 | T73 T8 T9 | T8 T9 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T25 T4 T6 | T43 T134 T265 | T73 T253 T75 | T169 T265 T122 | T118 T140 T320 | T118 T140 T320 | T118 T140 T320 | T321 T322 T265 | T265 T122 T319 | T265 T122 T319 | T154 T265 T122 | T265 T122 T317 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T317 | T265 T122 T317
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T4 T5 T6 | T5 T28 T8 | T4 T6 T26 | T28 T39 T126 | T5 T28 T8 | T4 T6 T26 | T39 T126 T124 | T28 T39 T319 | T28 T8 T19 | T5 T76 T35 | T4 T6 T26 | T118 T140 T320 | T126 T124 T127 | T39 T126 T37 | T28 T39 T319 | T28 T325 T30 | T28 T8 T19 | T31 T33 T325 | T36 T33 T325 | T5 T76 T35 | T73 T75 T214 | T4 T6 T26 | T118 T140 T320 | T317 T325 T326 | T124 T125 T319 | T126 T124 T127 | T126 T37 T127 | T39 T37 T319 | T28 T39 T319 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T8 T122 | T19 T31 T122 | T31 T325 T32 | T33 T325 T34 | T33 T325 T34 | T36 T325 T133 | T35 T36 T325 | T5 T76 T231 | T73 T75 T214 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T118 T140 T320 | T154 T122 T317 | T317 T325 T326 | T317 T325 T326 | T124 T125 T319 | T124 T125 T319 | T126 T124 T127 | T126 T127 T128 | T126 T37 T127 | T37 T319 T38 | T37 T319 T38 | T39 T319 T40 | T319 T323 T324 | T28 T39 T319 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T8 T122 | T19 T122 T20 | T31 T122 T325 | T325 T326 T327 | T31 T325 T32 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T33 T325 T34 | T36 T325 T133 | T36 T325 T133 | T325 T326 T327 | T35 T36 T325 | T5 T122 T325 | T76 T231 T348 | T73 T75 T214 | T122 T319 T178 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T253 T332 T254 | T118 T140 T320 | T118 T140 T320 | T122 T325 T178 | T154 T122 T317 | T325 T326 T327 | T317 T325 T326 | T317 T325 T326 | T124 T125 T319 | T124 T125 T319 | T124 T125 T319 | T319 T323 T324 | T124 T125 T319 | T126 T127 T128 | T126 T127 T128 | T319 T323 T324 | T319 T323 T324 | T126 T37 T127 | T37 T319 T38 | T37 T319 T38 | T319 T323 T324 | T37 T319 T38 | T39 T319 T40 | T39 T319 T40 | T319 T323 T324 | T319 T323 T324 | T28 T39 T319 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T8 T122 | T122 T178 T179 | T122 T178 T179 | T19 T122 T20 | T31 T122 T325 | T31 T325 T32 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T31 T325 T32 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T36 T325 T133 | T36 T325 T133 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T35 T36 T325 | T325 T326 T327 | T325 T326 T327 | T5 T122 T130 | T122 T178 T179 | T76 T231 T348 | T73 T75 T214 | T181 T122 T325 | T122 T178 T179 | T122 T319 T178 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T43 T134 T319 | T253 T332 T254 | T169 T122 T333 | T118 T140 T320 | T140 T320 T325 | T118 T140 T320 | T321 T322 T325 | T122 T325 T178 | T122 T178 T179 | T154 T122 T171 | T317 T325 T326 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T317 T325 T326 | T317 T325 T326
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T4 T5 T6 | T5 T28 T8 | T4 T6 T26 | T28 T39 T126 | T5 T28 T8 | T4 T6 T26 | T39 T126 T124 | T28 T39 T319 | T28 T8 T19 | T5 T76 T35 | T4 T6 T26 | T118 T140 T320 | T126 T124 T127 | T39 T126 T37 | T28 T39 T319 | T28 T325 T30 | T28 T8 T19 | T31 T33 T325 | T36 T33 T325 | T5 T76 T35 | T181 T122 T319 | T4 T6 T26 | T118 T140 T320 | T317 T325 T326 | T124 T125 T319 | T126 T124 T127 | T126 T37 T127 | T39 T37 T319 | T28 T39 T319 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T8 T122 | T19 T31 T122 | T31 T325 T32 | T33 T325 T34 | T33 T325 T34 | T36 T325 T133 | T35 T36 T325 | T5 T76 T231 | T181 T122 T319 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T118 T140 T320 | T154 T122 T317 | T317 T325 T326 | T325 T326 T327 | T124 T125 T319 | T319 T323 T324 | T126 T124 T127 | T126 T127 T128 | T126 T37 T127 | T37 T319 T38 | T37 T319 T38 | T39 T319 T40 | T319 T323 T324 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T8 T122 T215 | T19 T122 T20 | T31 T325 T32 | T325 T326 T327 | T31 T325 T32 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T33 T325 T34 | T36 T325 T133 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T5 T122 T325 | T76 T231 T348 | T181 T122 T325 | T122 T319 T178 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T253 T254 T348 | T118 T140 T320 | T321 T322 T325 | T122 T178 T179 | T122 T317 T325 | T325 T326 T327 | T317 T325 T326 | T325 T326 T327 | T124 T125 T319 | T124 T125 T319 | T319 T323 T324 | T319 T323 T324 | T124 T125 T319 | T126 T127 T128 | T126 T127 T128 | T319 T323 T324 | T319 T323 T324 | T37 T319 T38 | T37 T319 T38 | T319 T323 T324 | T319 T323 T324 | T37 T319 T38 | T39 T319 T40 | T39 T319 T40 | T319 T323 T324 | T319 T323 T324 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T28 T325 T30 | T8 T122 T215 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T31 T325 T32 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T33 T325 T34 | T325 T326 T327 | T325 T326 T327 | T36 T325 T133 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T5 T122 T130 | T122 T178 T179 | T76 T231 T348 | T325 T329 T326 | T122 T178 T179 | T122 T178 T179 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T319 T323 T324 | T4 T6 T26 | T134 T325 T331 | T253 T254 T348 | T122 T178 T179 | T118 T140 T320 | T140 T320 T325 | T325 T326 T327 | T325 T326 T327 | T122 T178 T179 | T122 T178 T179 | T122 T178 T179 | T317 T325 T326 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327 | T325 T326 T327
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T4 T5 T6 | T5 T28 T8 | T4 T6 T26 | T28 T39 T126 | T5 T28 T8 | T4 T6 T26 | T39 T126 T124 | T28 T39 T265 | T28 T8 T19 | T5 T76 T35 | T4 T6 T26 | T118 T140 T320 | T126 T124 T127 | T39 T126 T37 | T28 T39 T265 | T28 T265 T122 | T28 T8 T19 | T31 T33 T265 | T36 T33 T265 | T5 T76 T35 | T73 T75 T76 | T4 T6 T26 | T118 T140 T320 | T265 T122 T317 | T124 T125 T265 | T126 T124 T127 | T126 T37 T127 | T39 T37 T265 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T265 | T8 T19 T9 | T31 T265 T122 | T33 T265 T122 | T33 T265 T122 | T36 T265 T122 | T35 T36 T265 | T5 T76 T35 | T73 T8 T9 | T265 T122 T319 | T265 T122 T319 | T4 T6 T26 | T118 T140 T320 | T154 T265 T122 | T265 T122 T317 | T265 T122 T317 | T124 T125 T265 | T124 T125 T265 | T126 T124 T127 | T126 T127 T128 | T126 T37 T127 | T37 T265 T122 | T37 T265 T122 | T39 T265 T122 | T39 T265 T122 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T19 | T8 T19 T9 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T35 T36 T265 | T5 T35 T265 | T76 T231 T348 | T73 T75 T76 | T8 T9 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T4 T6 T26 | T73 T253 T75 | T118 T140 T320 | T118 T140 T320 | T265 T122 T319 | T154 T265 T122 | T265 T122 T319 | T265 T122 T317 | T265 T122 T317 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T124 T125 T265 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T127 T128 | T126 T37 T127 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T37 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T39 T265 T122 | T28 T39 T265 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T265 T122 | T28 T8 T19 | T19 T265 T122 | T8 T19 T9 | T19 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T31 T265 T122 | T265 T122 T319 | T265 T122 T319 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T33 T265 T122 | T265 T122 T319 | T265 T122 T319 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T36 T265 T122 | T35 T36 T265 | T35 T265 T122 | T35 T265 T122 | T5 T265 T122 | T265 T122 T319 | T73 T75 T76 | T73 T75 T76 | T73 T8 T9 | T8 T9 T265 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T25 T4 T6 | T43 T134 T265 | T73 T253 T75 | T169 T265 T122 | T118 T140 T320 | T118 T140 T320 | T118 T140 T320 | T321 T322 T265 | T265 T122 T319 | T265 T122 T319 | T154 T265 T122 | T265 T122 T317 | T265 T122 T319 | T265 T122 T319 | T265 T122 T319 | T265 T122 T317 | T265 T122 T317
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T4 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T4 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T4 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);