| | | | | | | |
|
prim_fifo_sync_cnt |
81.94 |
88.89 |
|
|
|
75.00 |
|
prim_fifo_sync |
92.42 |
100.00 |
80.94 |
|
|
88.75 |
100.00 |
|
prim_fifo_sync |
100.00 |
|
|
|
|
|
100.00 |
|
prim_fifo_sync ( parameter Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
80.77 |
|
80.77 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
91.76 |
100.00 |
85.29 |
|
|
90.00 |
|
|
prim_fifo_sync ( parameter Width=110,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=112,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_fifo_sync ( parameter Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
76.92 |
|
76.92 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
80.77 |
|
80.77 |
|
|
|
|
|
prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) |
93.75 |
100.00 |
|
|
|
87.50 |
|
|
prim_arbiter_ppc |
94.95 |
100.00 |
92.31 |
|
|
100.00 |
87.50 |
|
prim_arbiter_ppc |
93.75 |
|
|
|
|
100.00 |
87.50 |
|
prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 ) |
96.15 |
100.00 |
92.31 |
|
|
|
|
|
prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 ) |
96.15 |
100.00 |
92.31 |
|
|
|
|
|
tlul_socket_m1 |
98.48 |
100.00 |
95.45 |
|
|
|
100.00 |
|
tlul_socket_m1 |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 ) |
95.45 |
100.00 |
90.91 |
|
|
|
|
|
tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_fifo_async |
99.11 |
100.00 |
96.43 |
|
|
100.00 |
100.00 |
|
prim_fifo_async |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 ) |
92.86 |
|
92.86 |
|
|
|
|
|
tlul_socket_1n |
99.23 |
100.00 |
96.90 |
|
|
100.00 |
100.00 |
|
tlul_socket_1n |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 ) |
98.40 |
100.00 |
95.19 |
|
|
100.00 |
|
|
tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 ) |
99.54 |
100.00 |
98.61 |
|
|
100.00 |
|
|
xbar_main |
99.70 |
100.00 |
100.00 |
98.80 |
|
100.00 |
|
|
tlul_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
tlul_fifo_sync |
100.00 |
|
100.00 |
|
|
100.00 |
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
tlul_err_resp |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_data_integ_enc |
|
|
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|
|
|
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tlul_fifo_async |
|
|
|
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prim_flop |
|
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prim_flop_2sync |
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tb |
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