Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1708250 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266750 1 T1 378 T2 28 T3 27


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 661400 1 T1 956 T2 58 T3 59
values[0x0] 648200 1 T1 958 T2 60 T3 59
values[0x1] 665400 1 T1 947 T2 68 T3 68


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1319850 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 655150 1 T1 932 T2 68 T3 68


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 41250 1 T1 45 T4 75 T5 75
valid_sources[0x01] 20100 1 T1 18 T2 15 T4 44
valid_sources[0x02] 17900 1 T1 21 T4 6 T5 6
valid_sources[0x03] 31900 1 T1 43 T4 20 T5 20
valid_sources[0x04] 24850 1 T1 28 T4 5 T5 5
valid_sources[0x05] 24200 1 T1 45 T4 42 T5 42
valid_sources[0x06] 29600 1 T1 13 T3 52 T4 34
valid_sources[0x07] 37250 1 T1 117 T4 43 T5 43
valid_sources[0x08] 27800 1 T1 58 T2 14 T4 13
valid_sources[0x09] 46400 1 T1 63 T3 15 T4 39
valid_sources[0x0a] 24900 1 T1 34 T4 49 T5 49
valid_sources[0x0b] 28100 1 T1 35 T4 47 T5 47
valid_sources[0x0c] 28400 1 T1 34 T4 13 T5 13
valid_sources[0x0d] 32400 1 T1 13 T4 24 T5 24
valid_sources[0x0e] 38600 1 T1 34 T4 76 T5 76
valid_sources[0x0f] 22750 1 T1 29 T3 10 T4 43
valid_sources[0x10] 21950 1 T1 26 T4 39 T5 39
valid_sources[0x11] 34700 1 T1 46 T4 62 T5 62
valid_sources[0x12] 39300 1 T1 34 T2 3 T3 3
valid_sources[0x13] 36100 1 T1 111 T4 31 T5 31
valid_sources[0x14] 31850 1 T1 103 T4 12 T5 12
valid_sources[0x15] 32100 1 T1 54 T4 34 T5 34
valid_sources[0x16] 31600 1 T1 41 T4 31 T5 31
valid_sources[0x17] 39900 1 T1 74 T2 8 T4 33
valid_sources[0x18] 38000 1 T1 32 T4 62 T5 62
valid_sources[0x19] 17900 1 T1 19 T2 2 T4 44
valid_sources[0x1a] 31000 1 T1 69 T4 34 T5 34
valid_sources[0x1b] 28400 1 T1 54 T4 16 T5 16
valid_sources[0x1c] 16050 1 T1 22 T4 10 T5 10
valid_sources[0x1d] 30100 1 T1 34 T4 7 T5 7
valid_sources[0x1e] 33450 1 T1 93 T2 8 T4 54
valid_sources[0x1f] 43800 1 T1 1 T2 13 T4 35
valid_sources[0x20] 37750 1 T1 78 T2 4 T4 50


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 30250 1 T1 49 T2 4 T3 4
values[0x0] all_enables biggest_size 203650 1 T1 284 T2 21 T3 20
values[0x1] all_enables biggest_size 32850 1 T1 45 T2 3 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1634350 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 276600 1 T1 377 T2 21 T3 21


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 672100 1 T1 867 T2 52 T3 52
values[0x0] 607300 1 T1 819 T2 47 T3 47
values[0x1] 631550 1 T1 816 T2 52 T3 52


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1270150 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 640800 1 T1 833 T2 56 T3 56


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29350 1 T1 35 T4 58 T5 58
valid_sources[0x01] 29250 1 T1 38 T2 2 T3 2
valid_sources[0x02] 26050 1 T1 50 T4 16 T5 16
valid_sources[0x03] 27900 1 T1 49 T2 1 T3 2
valid_sources[0x04] 31600 1 T1 30 T2 7 T3 11
valid_sources[0x05] 32250 1 T1 20 T2 5 T3 4
valid_sources[0x06] 32100 1 T1 34 T2 4 T3 9
valid_sources[0x07] 33850 1 T1 29 T2 1 T3 1
valid_sources[0x08] 31800 1 T1 41 T2 1 T3 1
valid_sources[0x09] 34300 1 T1 40 T2 2 T3 5
valid_sources[0x0a] 25800 1 T1 60 T2 12 T3 7
valid_sources[0x0b] 30450 1 T1 57 T2 3 T3 5
valid_sources[0x0c] 27050 1 T1 32 T2 3 T3 1
valid_sources[0x0d] 28100 1 T1 45 T4 39 T5 39
valid_sources[0x0e] 28650 1 T1 47 T2 10 T3 8
valid_sources[0x0f] 31000 1 T1 57 T2 4 T3 2
valid_sources[0x10] 34750 1 T1 57 T2 1 T4 41
valid_sources[0x11] 25600 1 T1 48 T2 5 T3 6
valid_sources[0x12] 30900 1 T1 36 T4 7 T5 7
valid_sources[0x13] 34000 1 T1 34 T2 4 T3 8
valid_sources[0x14] 26550 1 T1 30 T2 2 T4 11
valid_sources[0x15] 31850 1 T1 29 T2 1 T3 6
valid_sources[0x16] 32550 1 T1 44 T2 3 T4 33
valid_sources[0x17] 29650 1 T1 36 T2 5 T4 36
valid_sources[0x18] 32500 1 T1 35 T4 57 T5 57
valid_sources[0x19] 26000 1 T1 32 T2 3 T4 46
valid_sources[0x1a] 31000 1 T1 54 T2 3 T3 3
valid_sources[0x1b] 27600 1 T1 40 T2 12 T3 6
valid_sources[0x1c] 26200 1 T1 37 T2 5 T3 3
valid_sources[0x1d] 31600 1 T1 35 T2 3 T4 10
valid_sources[0x1e] 30050 1 T1 28 T3 2 T4 43
valid_sources[0x1f] 26250 1 T1 50 T2 3 T3 10
valid_sources[0x20] 30450 1 T1 41 T2 1 T4 59


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 33700 1 T1 45 T2 4 T3 4
values[0x0] all_enables biggest_size 213050 1 T1 291 T2 14 T3 14
values[0x1] all_enables biggest_size 29850 1 T1 41 T2 3 T3 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1646500 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 266300 1 T1 367 T2 16 T3 16


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 650250 1 T1 867 T2 65 T3 65
values[0x0] 613700 1 T1 838 T2 43 T3 43
values[0x1] 648850 1 T1 880 T2 51 T3 51


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1269750 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 643050 1 T1 865 T2 47 T3 47


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 31250 1 T1 38 T2 3 T3 3
valid_sources[0x01] 29600 1 T1 39 T2 9 T3 9
valid_sources[0x02] 29450 1 T1 38 T2 3 T3 3
valid_sources[0x03] 28050 1 T1 35 T4 20 T5 20
valid_sources[0x04] 30700 1 T1 36 T2 1 T3 1
valid_sources[0x05] 30350 1 T1 39 T2 1 T3 1
valid_sources[0x06] 31150 1 T1 40 T2 3 T3 3
valid_sources[0x07] 34000 1 T1 36 T2 3 T3 3
valid_sources[0x08] 28600 1 T1 44 T2 3 T3 3
valid_sources[0x09] 35500 1 T1 41 T2 3 T3 3
valid_sources[0x0a] 25850 1 T1 23 T2 4 T3 4
valid_sources[0x0b] 28000 1 T1 28 T2 2 T3 2
valid_sources[0x0c] 31400 1 T1 56 T2 4 T3 5
valid_sources[0x0d] 26850 1 T1 31 T2 3 T3 3
valid_sources[0x0e] 29550 1 T1 46 T2 1 T3 1
valid_sources[0x0f] 30100 1 T1 32 T2 4 T3 4
valid_sources[0x10] 30500 1 T1 48 T2 2 T3 3
valid_sources[0x11] 30400 1 T1 41 T2 4 T3 3
valid_sources[0x12] 29900 1 T1 33 T2 5 T3 4
valid_sources[0x13] 33800 1 T1 45 T2 7 T3 7
valid_sources[0x14] 25800 1 T1 41 T2 1 T3 1
valid_sources[0x15] 33850 1 T1 48 T2 4 T3 4
valid_sources[0x16] 31250 1 T1 35 T2 3 T3 3
valid_sources[0x17] 30700 1 T1 32 T2 2 T3 2
valid_sources[0x18] 30200 1 T1 38 T2 2 T3 2
valid_sources[0x19] 27650 1 T1 51 T2 4 T3 4
valid_sources[0x1a] 29450 1 T1 31 T4 38 T5 38
valid_sources[0x1b] 25750 1 T1 26 T4 7 T5 7
valid_sources[0x1c] 26200 1 T1 33 T4 6 T5 6
valid_sources[0x1d] 31400 1 T1 53 T2 1 T3 1
valid_sources[0x1e] 28050 1 T1 29 T4 54 T5 54
valid_sources[0x1f] 28500 1 T1 43 T2 2 T3 2
valid_sources[0x20] 30900 1 T1 44 T2 4 T3 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24500 1 T1 29 T2 2 T3 2
values[0x0] all_enables biggest_size 214500 1 T1 301 T2 12 T3 12
values[0x1] all_enables biggest_size 27300 1 T1 37 T2 2 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%