Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	100.00	81.82				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7599350	0	0
GntImpliesValid_A	2147483647	7599350	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7599350	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	657297650	0	0
ReadyAndValidImplyGrant_A	2147483647	7599350	0	0
ReqAndReadyImplyGrant_A	2147483647	7599350	0	0
ReqImpliesValid_A	2147483647	42538050	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	3450	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7599350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4845648	4845624	0	0
T2	44616	44352	0	0
T3	257256	256992	0	0
T4	2732592	2732208	0	0
T5	2732592	2732208	0	0
T6	294480	294216	0	0
T7	10913064	10912800	0	0
T8	6782304	6782040	0	0
T9	7249656	7249632	0	0
T10	257256	256992	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4845648	4845624	0	0
T2	44616	44352	0	0
T3	257256	256992	0	0
T4	2732592	2732208	0	0
T5	2732592	2732208	0	0
T6	294480	294216	0	0
T7	10913064	10912800	0	0
T8	6782304	6782040	0	0
T9	7249656	7249632	0	0
T10	257256	256992	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4845648	4845624	0	0
T2	44616	44352	0	0
T3	257256	256992	0	0
T4	2732592	2732208	0	0
T5	2732592	2732208	0	0
T6	294480	294216	0	0
T7	10913064	10912800	0	0
T8	6782304	6782040	0	0
T9	7249656	7249632	0	0
T10	257256	256992	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	657297650	0	0
T1	4845648	197252	0	0
T2	44616	494	0	0
T3	257256	12585	0	0
T4	2732592	141371	0	0
T5	2732592	141371	0	0
T6	294480	7836	0	0
T7	10913064	561566	0	0
T8	6782304	236948	0	0
T9	7249656	2368875	0	0
T10	257256	12585	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42538050	0	0
T1	4845648	12576	0	0
T2	44616	537	0	0
T3	257256	1045	0	0
T4	2732592	12457	0	0
T5	2732592	12457	0	0
T6	294480	9275	0	0
T7	10913064	25351	0	0
T8	6782304	799	0	0
T9	7249656	471277	0	0
T10	257256	1045	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3450	0	21600
T4	227716	3	0	2
T5	227716	3	0	2
T6	24540	28	0	2
T7	909422	0	0	2
T8	565192	0	0	2
T9	604138	0	0	2
T10	21438	0	0	2
T11	0	2	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	15	0	0
T16	0	15	0	0
T17	0	2	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	18	0	0
T21	0	1	0	0
T22	0	18	0	0
T23	403804	0	0	2
T24	140876	0	0	2
T25	105824	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4845648	4845624	0	0
T2	44616	44352	0	0
T3	257256	256992	0	0
T4	2732592	2732208	0	0
T5	2732592	2732208	0	0
T6	294480	294216	0	0
T7	10913064	10912800	0	0
T8	6782304	6782040	0	0
T9	7249656	7249632	0	0
T10	257256	256992	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7599350	0	0
T1	4845648	7945	0	0
T2	44616	496	0	0
T3	257256	496	0	0
T4	2732592	6755	0	0
T5	2732592	6755	0	0
T6	294480	8238	0	0
T7	10913064	496	0	0
T8	6782304	496	0	0
T9	7249656	8087	0	0
T10	257256	496	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	788150	0	0
GntImpliesValid_A	596015100	788150	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	788150	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	20687850	0	0
ReadyAndValidImplyGrant_A	596015100	788150	0	0
ReqAndReadyImplyGrant_A	596015100	788150	0	0
ReqImpliesValid_A	596015100	3196850	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	788150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	20687850	0	0
T1	201902	3606	0	0
T2	1859	54	0	0
T3	10719	507	0	0
T4	113858	6020	0	0
T5	113858	6020	0	0
T6	12270	642	0	0
T7	454711	18397	0	0
T8	282596	243	0	0
T9	302069	298042	0	0
T10	10719	507	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	3196850	0	0
T1	201902	1270	0	0
T2	1859	67	0	0
T3	10719	87	0	0
T4	113858	903	0	0
T5	113858	903	0	0
T6	12270	1141	0	0
T7	454711	683	0	0
T8	282596	77	0	0
T9	302069	39418	0	0
T10	10719	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	788150	0	0
T1	201902	878	0	0
T2	1859	60	0	0
T3	10719	61	0	0
T4	113858	774	0	0
T5	113858	774	0	0
T6	12270	891	0	0
T7	454711	61	0	0
T8	282596	63	0	0
T9	302069	907	0	0
T10	10719	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	915800	0	0
GntImpliesValid_A	596015100	915800	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	915800	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	17640700	0	0
ReadyAndValidImplyGrant_A	596015100	915800	0	0
ReqAndReadyImplyGrant_A	596015100	915800	0	0
ReqImpliesValid_A	596015100	3000850	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	915800	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	17640700	0	0
T1	201902	3631	0	0
T2	1859	41	0	0
T3	10719	345	0	0
T4	113858	5802	0	0
T5	113858	5802	0	0
T6	12270	664	0	0
T7	454711	16734	0	0
T8	282596	217	0	0
T9	302069	238558	0	0
T10	10719	345	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	3000850	0	0
T1	201902	1138	0	0
T2	1859	54	0	0
T3	10719	49	0	0
T4	113858	886	0	0
T5	113858	886	0	0
T6	12270	1089	0	0
T7	454711	282	0	0
T8	282596	70	0	0
T9	302069	28208	0	0
T10	10719	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	915800	0	0
T1	201902	863	0	0
T2	1859	47	0	0
T3	10719	49	0	0
T4	113858	777	0	0
T5	113858	777	0	0
T6	12270	876	0	0
T7	454711	49	0	0
T8	282596	48	0	0
T9	302069	836	0	0
T10	10719	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	210950	0	0
GntImpliesValid_A	596015100	210950	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	210950	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5000850	0	0
ReadyAndValidImplyGrant_A	596015100	210950	0	0
ReqAndReadyImplyGrant_A	596015100	210950	0	0
ReqImpliesValid_A	596015100	688300	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	210950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5000850	0	0
T1	201902	861	0	0
T2	1859	10	0	0
T3	10719	77	0	0
T4	113858	1461	0	0
T5	113858	1461	0	0
T6	12270	236	0	0
T7	454711	2098	0	0
T8	282596	33	0	0
T9	302069	75394	0	0
T10	10719	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	688300	0	0
T1	201902	267	0	0
T2	1859	13	0	0
T3	10719	9	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	249	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	4037	0	0
T10	10719	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	210950	0	0
T1	201902	222	0	0
T2	1859	11	0	0
T3	10719	8	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	242	0	0
T7	454711	7	0	0
T8	282596	10	0	0
T9	302069	230	0	0
T10	10719	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	180100	0	0
GntImpliesValid_A	596015100	180100	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	180100	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5469000	0	0
ReadyAndValidImplyGrant_A	596015100	180100	0	0
ReqAndReadyImplyGrant_A	596015100	180100	0	0
ReqImpliesValid_A	596015100	454900	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	180100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5469000	0	0
T1	201902	968	0	0
T2	1859	19	0	0
T3	10719	160	0	0
T4	113858	1391	0	0
T5	113858	1391	0	0
T6	12270	230	0	0
T7	454711	5037	0	0
T8	282596	81	0	0
T9	302069	82112	0	0
T10	10719	160	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	454900	0	0
T1	201902	299	0	0
T2	1859	24	0	0
T3	10719	17	0	0
T4	113858	191	0	0
T5	113858	191	0	0
T6	12270	265	0	0
T7	454711	13	0	0
T8	282596	21	0	0
T9	302069	4905	0	0
T10	10719	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	180100	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	247	0	0
T7	454711	13	0	0
T8	282596	20	0	0
T9	302069	247	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	172150	0	0
GntImpliesValid_A	596015100	172150	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	172150	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	2250900	0	0
ReadyAndValidImplyGrant_A	596015100	172150	0	0
ReqAndReadyImplyGrant_A	596015100	172150	0	0
ReqImpliesValid_A	596015100	270550	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	172150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	2250900	0	0
T1	201902	1014	0	0
T2	1859	59	0	0
T3	10719	95	0	0
T4	113858	1159	0	0
T5	113858	1159	0	0
T6	12270	865	0	0
T7	454711	1593	0	0
T8	282596	80	0	0
T9	302069	25117	0	0
T10	10719	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270550	0	0
T1	201902	276	0	0
T2	1859	21	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	341	0	0
T7	454711	160	0	0
T8	282596	16	0	0
T9	302069	1320	0	0
T10	10719	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172150	0	0
T1	201902	210	0	0
T2	1859	16	0	0
T3	10719	15	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	237	0	0
T7	454711	14	0	0
T8	282596	16	0	0
T9	302069	229	0	0
T10	10719	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	268800	0	0
GntImpliesValid_A	596015100	268800	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	268800	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	2087550	0	0
ReadyAndValidImplyGrant_A	596015100	268800	0	0
ReqAndReadyImplyGrant_A	596015100	268800	0	0
ReqImpliesValid_A	596015100	534800	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	268800	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	2087550	0	0
T1	201902	977	0	0
T2	1859	43	0	0
T3	10719	100	0	0
T4	113858	1039	0	0
T5	113858	1039	0	0
T6	12270	640	0	0
T7	454711	1108	0	0
T8	282596	64	0	0
T9	302069	19195	0	0
T10	10719	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	534800	0	0
T1	201902	251	0	0
T2	1859	21	0	0
T3	10719	18	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	261	0	0
T7	454711	42	0	0
T8	282596	17	0	0
T9	302069	887	0	0
T10	10719	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	268800	0	0
T1	201902	217	0	0
T2	1859	14	0	0
T3	10719	18	0	0
T4	113858	190	0	0
T5	113858	190	0	0
T6	12270	197	0	0
T7	454711	15	0	0
T8	282596	14	0	0
T9	302069	216	0	0
T10	10719	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	226900	0	0
GntImpliesValid_A	596015100	226900	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	226900	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	1673900	0	0
ReadyAndValidImplyGrant_A	596015100	226900	0	0
ReqAndReadyImplyGrant_A	596015100	226900	0	0
ReqImpliesValid_A	596015100	361000	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	226900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	1673900	0	0
T1	201902	969	0	0
T2	1859	34	0	0
T3	10719	37	0	0
T4	113858	948	0	0
T5	113858	948	0	0
T6	12270	792	0	0
T7	454711	699	0	0
T8	282596	48	0	0
T9	302069	15161	0	0
T10	10719	37	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	361000	0	0
T1	201902	284	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	207	0	0
T5	113858	207	0	0
T6	12270	342	0	0
T7	454711	10	0	0
T8	282596	14	0	0
T9	302069	548	0	0
T10	10719	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	226900	0	0
T1	201902	240	0	0
T2	1859	10	0	0
T3	10719	8	0	0
T4	113858	196	0	0
T5	113858	196	0	0
T6	12270	250	0	0
T7	454711	10	0	0
T8	282596	12	0	0
T9	302069	238	0	0
T10	10719	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	207250	0	0
GntImpliesValid_A	596015100	207250	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	207250	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	1868000	0	0
ReadyAndValidImplyGrant_A	596015100	207250	0	0
ReqAndReadyImplyGrant_A	596015100	207250	0	0
ReqImpliesValid_A	596015100	373050	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	207250	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	1868000	0	0
T1	201902	950	0	0
T2	1859	30	0	0
T3	10719	46	0	0
T4	113858	938	0	0
T5	113858	938	0	0
T6	12270	692	0	0
T7	454711	644	0	0
T8	282596	41	0	0
T9	302069	18889	0	0
T10	10719	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	373050	0	0
T1	201902	242	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	308	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	898	0	0
T10	10719	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	207250	0	0
T1	201902	207	0	0
T2	1859	9	0	0
T3	10719	9	0	0
T4	113858	176	0	0
T5	113858	176	0	0
T6	12270	215	0	0
T7	454711	13	0	0
T8	282596	9	0	0
T9	302069	209	0	0
T10	10719	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	170500	0	0
GntImpliesValid_A	596015100	170500	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	170500	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	4794250	0	0
ReadyAndValidImplyGrant_A	596015100	170500	0	0
ReqAndReadyImplyGrant_A	596015100	170500	0	0
ReqImpliesValid_A	596015100	422800	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	170500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	4794250	0	0
T1	201902	927	0	0
T2	1859	20	0	0
T3	10719	133	0	0
T4	113858	1324	0	0
T5	113858	1324	0	0
T6	12270	216	0	0
T7	454711	3330	0	0
T8	282596	66	0	0
T9	302069	71759	0	0
T10	10719	133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	422800	0	0
T1	201902	271	0	0
T2	1859	21	0	0
T3	10719	17	0	0
T4	113858	217	0	0
T5	113858	217	0	0
T6	12270	241	0	0
T7	454711	14	0	0
T8	282596	22	0	0
T9	302069	4422	0	0
T10	10719	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	170500	0	0
T1	201902	218	0	0
T2	1859	20	0	0
T3	10719	17	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	228	0	0
T7	454711	14	0	0
T8	282596	19	0	0
T9	302069	238	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	227050	0	0
GntImpliesValid_A	596015100	227050	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	227050	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5053700	0	0
ReadyAndValidImplyGrant_A	596015100	227050	0	0
ReqAndReadyImplyGrant_A	596015100	227050	0	0
ReqImpliesValid_A	596015100	517850	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	227050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5053700	0	0
T1	201902	986	0	0
T2	1859	12	0	0
T3	10719	72	0	0
T4	113858	1469	0	0
T5	113858	1469	0	0
T6	12270	229	0	0
T7	454711	3667	0	0
T8	282596	60	0	0
T9	302069	72906	0	0
T10	10719	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	517850	0	0
T1	201902	277	0	0
T2	1859	13	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	256	0	0
T7	454711	8	0	0
T8	282596	14	0	0
T9	302069	2566	0	0
T10	10719	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	227050	0	0
T1	201902	245	0	0
T2	1859	12	0	0
T3	10719	8	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	242	0	0
T7	454711	8	0	0
T8	282596	13	0	0
T9	302069	236	0	0
T10	10719	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	222550	0	0
GntImpliesValid_A	596015100	222550	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	222550	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5467700	0	0
ReadyAndValidImplyGrant_A	596015100	222550	0	0
ReqAndReadyImplyGrant_A	596015100	222550	0	0
ReqImpliesValid_A	596015100	516650	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	222550	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5467700	0	0
T1	201902	985	0	0
T2	1859	14	0	0
T3	10719	134	0	0
T4	113858	1571	0	0
T5	113858	1571	0	0
T6	12270	237	0	0
T7	454711	6093	0	0
T8	282596	62	0	0
T9	302069	77528	0	0
T10	10719	134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	516650	0	0
T1	201902	284	0	0
T2	1859	13	0	0
T3	10719	32	0	0
T4	113858	205	0	0
T5	113858	205	0	0
T6	12270	260	0	0
T7	454711	785	0	0
T8	282596	18	0	0
T9	302069	2640	0	0
T10	10719	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	222550	0	0
T1	201902	224	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	192	0	0
T5	113858	192	0	0
T6	12270	248	0	0
T7	454711	19	0	0
T8	282596	15	0	0
T9	302069	225	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	369350	0	0
GntImpliesValid_A	596015100	369350	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	369350	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5649550	0	0
ReadyAndValidImplyGrant_A	596015100	369350	0	0
ReqAndReadyImplyGrant_A	596015100	369350	0	0
ReqImpliesValid_A	596015100	1840900	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	369350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5649550	0	0
T1	201902	875	0	0
T2	1859	13	0	0
T3	10719	52	0	0
T4	113858	1369	0	0
T5	113858	1369	0	0
T6	12270	214	0	0
T7	454711	3984	0	0
T8	282596	69	0	0
T9	302069	77990	0	0
T10	10719	52	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	1840900	0	0
T1	201902	278	0	0
T2	1859	18	0	0
T3	10719	9	0	0
T4	113858	191	0	0
T5	113858	191	0	0
T6	12270	241	0	0
T7	454711	66	0	0
T8	282596	16	0	0
T9	302069	7531	0	0
T10	10719	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	369350	0	0
T1	201902	210	0	0
T2	1859	15	0	0
T3	10719	9	0	0
T4	113858	175	0	0
T5	113858	175	0	0
T6	12270	227	0	0
T7	454711	16	0	0
T8	282596	14	0	0
T9	302069	239	0	0
T10	10719	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	209500	0	0
GntImpliesValid_A	596015100	209500	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	209500	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5254250	0	0
ReadyAndValidImplyGrant_A	596015100	209500	0	0
ReqAndReadyImplyGrant_A	596015100	209500	0	0
ReqImpliesValid_A	596015100	680000	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	209500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5254250	0	0
T1	201902	986	0	0
T2	1859	14	0	0
T3	10719	108	0	0
T4	113858	1295	0	0
T5	113858	1295	0	0
T6	12270	220	0	0
T7	454711	4990	0	0
T8	282596	62	0	0
T9	302069	77753	0	0
T10	10719	108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	680000	0	0
T1	201902	285	0	0
T2	1859	13	0	0
T3	10719	27	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	247	0	0
T7	454711	153	0	0
T8	282596	22	0	0
T9	302069	3608	0	0
T10	10719	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	209500	0	0
T1	201902	227	0	0
T2	1859	13	0	0
T3	10719	14	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	16	0	0
T8	282596	15	0	0
T9	302069	229	0	0
T10	10719	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	211750	0	0
GntImpliesValid_A	596015100	211750	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	211750	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	4833400	0	0
ReadyAndValidImplyGrant_A	596015100	211750	0	0
ReqAndReadyImplyGrant_A	596015100	211750	0	0
ReqImpliesValid_A	596015100	490300	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	211750	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	4833400	0	0
T1	201902	986	0	0
T2	1859	14	0	0
T3	10719	150	0	0
T4	113858	1485	0	0
T5	113858	1485	0	0
T6	12270	209	0	0
T7	454711	7335	0	0
T8	282596	60	0	0
T9	302069	66202	0	0
T10	10719	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	490300	0	0
T1	201902	281	0	0
T2	1859	13	0	0
T3	10719	20	0	0
T4	113858	206	0	0
T5	113858	206	0	0
T6	12270	232	0	0
T7	454711	20	0	0
T8	282596	15	0	0
T9	302069	2602	0	0
T10	10719	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	211750	0	0
T1	201902	228	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	199	0	0
T5	113858	199	0	0
T6	12270	220	0	0
T7	454711	20	0	0
T8	282596	13	0	0
T9	302069	229	0	0
T10	10719	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	168400	0	0
GntImpliesValid_A	596015100	168400	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	168400	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5140600	0	0
ReadyAndValidImplyGrant_A	596015100	168400	0	0
ReqAndReadyImplyGrant_A	596015100	168400	0	0
ReqImpliesValid_A	596015100	396050	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	168400	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5140600	0	0
T1	201902	1046	0	0
T2	1859	13	0	0
T3	10719	97	0	0
T4	113858	1431	0	0
T5	113858	1431	0	0
T6	12270	228	0	0
T7	454711	3919	0	0
T8	282596	40	0	0
T9	302069	76981	0	0
T10	10719	97	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	396050	0	0
T1	201902	268	0	0
T2	1859	12	0	0
T3	10719	35	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	245	0	0
T7	454711	203	0	0
T8	282596	17	0	0
T9	302069	3810	0	0
T10	10719	35	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	168400	0	0
T1	201902	231	0	0
T2	1859	12	0	0
T3	10719	15	0	0
T4	113858	185	0	0
T5	113858	185	0	0
T6	12270	236	0	0
T7	454711	13	0	0
T8	282596	12	0	0
T9	302069	234	0	0
T10	10719	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	178000	0	0
GntImpliesValid_A	596015100	178000	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	178000	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5395550	0	0
ReadyAndValidImplyGrant_A	596015100	178000	0	0
ReqAndReadyImplyGrant_A	596015100	178000	0	0
ReqImpliesValid_A	596015100	665200	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	178000	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5395550	0	0
T1	201902	1052	0	0
T2	1859	17	0	0
T3	10719	131	0	0
T4	113858	1581	0	0
T5	113858	1581	0	0
T6	12270	223	0	0
T7	454711	4274	0	0
T8	282596	70	0	0
T9	302069	81057	0	0
T10	10719	131	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	665200	0	0
T1	201902	278	0	0
T2	1859	18	0	0
T3	10719	20	0	0
T4	113858	211	0	0
T5	113858	211	0	0
T6	12270	250	0	0
T7	454711	315	0	0
T8	282596	31	0	0
T9	302069	8622	0	0
T10	10719	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	178000	0	0
T1	201902	247	0	0
T2	1859	17	0	0
T3	10719	17	0	0
T4	113858	202	0	0
T5	113858	202	0	0
T6	12270	236	0	0
T7	454711	16	0	0
T8	282596	16	0	0
T9	302069	245	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	174700	0	0
GntImpliesValid_A	596015100	174700	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	174700	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	4284150	0	0
ReadyAndValidImplyGrant_A	596015100	174700	0	0
ReqAndReadyImplyGrant_A	596015100	174700	0	0
ReqImpliesValid_A	596015100	396100	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	174700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	4284150	0	0
T1	201902	845	0	0
T2	1859	15	0	0
T3	10719	149	0	0
T4	113858	1285	0	0
T5	113858	1285	0	0
T6	12270	189	0	0
T7	454711	3843	0	0
T8	282596	57	0	0
T9	302069	59405	0	0
T10	10719	149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	396100	0	0
T1	201902	239	0	0
T2	1859	16	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	216	0	0
T7	454711	575	0	0
T8	282596	15	0	0
T9	302069	3005	0	0
T10	10719	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	174700	0	0
T1	201902	198	0	0
T2	1859	15	0	0
T3	10719	17	0	0
T4	113858	171	0	0
T5	113858	171	0	0
T6	12270	202	0	0
T7	454711	12	0	0
T8	282596	14	0	0
T9	302069	194	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	172650	0	0
GntImpliesValid_A	596015100	172650	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	172650	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5173800	0	0
ReadyAndValidImplyGrant_A	596015100	172650	0	0
ReqAndReadyImplyGrant_A	596015100	172650	0	0
ReqImpliesValid_A	596015100	368350	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	172650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5173800	0	0
T1	201902	949	0	0
T2	1859	18	0	0
T3	10719	110	0	0
T4	113858	1292	0	0
T5	113858	1292	0	0
T6	12270	216	0	0
T7	454711	7466	0	0
T8	282596	90	0	0
T9	302069	75127	0	0
T10	10719	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	368350	0	0
T1	201902	249	0	0
T2	1859	19	0	0
T3	10719	44	0	0
T4	113858	180	0	0
T5	113858	180	0	0
T6	12270	255	0	0
T7	454711	443	0	0
T8	282596	23	0	0
T9	302069	3005	0	0
T10	10719	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	172650	0	0
T1	201902	227	0	0
T2	1859	18	0	0
T3	10719	19	0	0
T4	113858	177	0	0
T5	113858	177	0	0
T6	12270	235	0	0
T7	454711	18	0	0
T8	282596	18	0	0
T9	302069	247	0	0
T10	10719	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	270100	0	0
GntImpliesValid_A	596015100	270100	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	270100	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5645650	0	0
ReadyAndValidImplyGrant_A	596015100	270100	0	0
ReqAndReadyImplyGrant_A	596015100	270100	0	0
ReqImpliesValid_A	596015100	1163150	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	270100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5645650	0	0
T1	201902	921	0	0
T2	1859	15	0	0
T3	10719	99	0	0
T4	113858	1321	0	0
T5	113858	1321	0	0
T6	12270	217	0	0
T7	454711	5403	0	0
T8	282596	79	0	0
T9	302069	81944	0	0
T10	10719	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	1163150	0	0
T1	201902	306	0	0
T2	1859	16	0	0
T3	10719	17	0	0
T4	113858	178	0	0
T5	113858	178	0	0
T6	12270	250	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	7030	0	0
T10	10719	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	270100	0	0
T1	201902	238	0	0
T2	1859	15	0	0
T3	10719	15	0	0
T4	113858	174	0	0
T5	113858	174	0	0
T6	12270	233	0	0
T7	454711	14	0	0
T8	282596	14	0	0
T9	302069	245	0	0
T10	10719	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T6,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	164650	0	0
GntImpliesValid_A	596015100	164650	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	164650	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	4561150	0	0
ReadyAndValidImplyGrant_A	596015100	164650	0	0
ReqAndReadyImplyGrant_A	596015100	164650	0	0
ReqImpliesValid_A	596015100	414650	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	164650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	4561150	0	0
T1	201902	864	0	0
T2	1859	9	0	0
T3	10719	31	0	0
T4	113858	1424	0	0
T5	113858	1424	0	0
T6	12270	216	0	0
T7	454711	1187	0	0
T8	282596	44	0	0
T9	302069	69121	0	0
T10	10719	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	414650	0	0
T1	201902	267	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	253	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	4585	0	0
T10	10719	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	164650	0	0
T1	201902	216	0	0
T2	1859	8	0	0
T3	10719	6	0	0
T4	113858	181	0	0
T5	113858	181	0	0
T6	12270	234	0	0
T7	454711	5	0	0
T8	282596	9	0	0
T9	302069	226	0	0
T10	10719	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	252900	0	0
GntImpliesValid_A	596015100	252900	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	252900	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5105050	0	0
ReadyAndValidImplyGrant_A	596015100	252900	0	0
ReqAndReadyImplyGrant_A	596015100	252900	0	0
ReqImpliesValid_A	596015100	699250	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	252900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5105050	0	0
T1	201902	949	0	0
T2	1859	14	0	0
T3	10719	156	0	0
T4	113858	1356	0	0
T5	113858	1356	0	0
T6	12270	229	0	0
T7	454711	5992	0	0
T8	282596	65	0	0
T9	302069	70841	0	0
T10	10719	156	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	699250	0	0
T1	201902	279	0	0
T2	1859	13	0	0
T3	10719	19	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	242	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	4282	0	0
T10	10719	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	252900	0	0
T1	201902	222	0	0
T2	1859	13	0	0
T3	10719	17	0	0
T4	113858	183	0	0
T5	113858	183	0	0
T6	12270	235	0	0
T7	454711	17	0	0
T8	282596	14	0	0
T9	302069	223	0	0
T10	10719	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	171600	0	0
GntImpliesValid_A	596015100	171600	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	171600	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	5145550	0	0
ReadyAndValidImplyGrant_A	596015100	171600	0	0
ReqAndReadyImplyGrant_A	596015100	171600	0	0
ReqImpliesValid_A	596015100	398100	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	0	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	171600	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	5145550	0	0
T1	201902	1088	0	0
T2	1859	14	0	0
T3	10719	68	0	0
T4	113858	1383	0	0
T5	113858	1383	0	0
T6	12270	230	0	0
T7	454711	3062	0	0
T8	282596	55	0	0
T9	302069	78743	0	0
T10	10719	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	398100	0	0
T1	201902	292	0	0
T2	1859	15	0	0
T3	10719	11	0	0
T4	113858	193	0	0
T5	113858	193	0	0
T6	12270	263	0	0
T7	454711	13	0	0
T8	282596	19	0	0
T9	302069	4044	0	0
T10	10719	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	171600	0	0
T1	201902	248	0	0
T2	1859	14	0	0
T3	10719	11	0	0
T4	113858	188	0	0
T5	113858	188	0	0
T6	12270	246	0	0
T7	454711	13	0	0
T8	282596	13	0	0
T9	302069	245	0	0
T10	10719	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	903950	0	0
GntImpliesValid_A	596015100	903950	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	903950	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	19845500	0	0
ReadyAndValidImplyGrant_A	596015100	903950	0	0
ReqAndReadyImplyGrant_A	596015100	903950	0	0
ReqImpliesValid_A	596015100	3733150	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	2550	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	903950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	19845500	0	0
T1	201902	2832	0	0
T2	1859	1	0	0
T3	10719	414	0	0
T4	113858	4764	0	0
T5	113858	4764	0	0
T6	12270	1	0	0
T7	454711	17535	0	0
T8	282596	173	0	0
T9	302069	287202	0	0
T10	10719	414	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	3733150	0	0
T1	201902	1104	0	0
T2	1859	52	0	0
T3	10719	87	0	0
T4	113858	832	0	0
T5	113858	832	0	0
T6	12270	946	0	0
T7	454711	844	0	0
T8	282596	61	0	0
T9	302069	32267	0	0
T10	10719	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	2550	0	900
T4	113858	1	0	1
T5	113858	1	0	1
T6	12270	18	0	1
T7	454711	0	0	1
T8	282596	0	0	1
T9	302069	0	0	1
T10	10719	0	0	1
T15	0	14	0	0
T16	0	14	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	18	0	0
T21	0	1	0	0
T22	0	18	0	0
T23	201902	0	0	1
T24	70438	0	0	1
T25	52912	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	903950	0	0
T1	201902	846	0	0
T2	1859	52	0	0
T3	10719	53	0	0
T4	113858	729	0	0
T5	113858	729	0	0
T6	12270	946	0	0
T7	454711	49	0	0
T8	282596	51	0	0
T9	302069	871	0	0
T10	10719	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	596015100	595957550	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	596015100	761600	0	0
GntImpliesValid_A	596015100	761600	0	0
GrantKnown_A	596015100	595957550	0	0
IdxKnown_A	596015100	595957550	0	0
IndexIsCorrect_A	596015100	761600	0	0
LockArbDecision_A	596015100	0	0	0
NoReadyValidNoGrant_A	596015100	509269050	0	0
ReadyAndValidImplyGrant_A	596015100	761600	0	0
ReqAndReadyImplyGrant_A	596015100	761600	0	0
ReqImpliesValid_A	596015100	20955250	0	0
ReqStaysHighUntilGranted0_M	596015100	0	0	0
RoundRobin_A	596015100	900	0	900
ValidKnown_A	596015100	595957550	0	0
gen_data_port_assertion.DataFlow_A	596015100	761600	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	509269050	0	0
T1	201902	167985	0	0
T2	1859	1	0	0
T3	10719	9314	0	0
T4	113858	98263	0	0
T5	113858	98263	0	0
T6	12270	1	0	0
T7	454711	433176	0	0
T8	282596	235089	0	0
T9	302069	271848	0	0
T10	10719	9314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	20955250	0	0
T1	201902	3591	0	0
T2	1859	58	0	0
T3	10719	464	0	0
T4	113858	6029	0	0
T5	113858	6029	0	0
T6	12270	882	0	0
T7	454711	20666	0	0
T8	282596	255	0	0
T9	302069	297037	0	0
T10	10719	464	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	900	0	900
T4	113858	2	0	1
T5	113858	2	0	1
T6	12270	10	0	1
T7	454711	0	0	1
T8	282596	0	0	1
T9	302069	0	0	1
T10	10719	0	0	1
T11	0	2	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	0	2	0	0
T23	201902	0	0	1
T24	70438	0	0	1
T25	52912	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	595957550	0	0
T1	201902	201901	0	0
T2	1859	1848	0	0
T3	10719	10708	0	0
T4	113858	113842	0	0
T5	113858	113842	0	0
T6	12270	12259	0	0
T7	454711	454700	0	0
T8	282596	282585	0	0
T9	302069	302068	0	0
T10	10719	10708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596015100	761600	0	0
T1	201902	832	0	0
T2	1859	58	0	0
T3	10719	57	0	0
T4	113858	787	0	0
T5	113858	787	0	0
T6	12270	882	0	0
T7	454711	64	0	0
T8	282596	54	0	0
T9	302069	849	0	0
T10	10719	57	0	0