Unified Coverage Report :: Module :: tlul_socket_1n

Module : tlul_socket_1n

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78	100.00	95.14			100.00	100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_32	97.84	100.00	91.35			100.00	100.00
tb.dut.u_s1n_57	97.92	100.00	91.67			100.00	100.00
tb.dut.u_s1n_27	99.65	100.00	98.61			100.00	100.00

Line Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Line Coverage for Module self-instances :

SCORE	LINE
99.65	100.00

tb.dut.u_s1n_27

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
ALWAYS	178	6	6	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	4	4	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
122	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
			MISSING_ELSE
130	1	1
143	1	1
153	4	4
155	4	4
156	4	4
157	4	4
158	4	4
159	4	4
160	4	4
161	4	4
162	4	4
165	4	4
169	4	4
178	1	1
179	1	1
181	2	2
			MISSING_ELSE
183	2	2
			MISSING_ELSE
187	1	1
190	1	1
191	1	1
192	2	2
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
228	1	1
229	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1

---

Line Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Line Coverage for Module self-instances :

SCORE	LINE
97.84	100.00

tb.dut.u_s1n_32

SCORE	LINE
97.92	100.00

tb.dut.u_s1n_57

	Line No.	Total	Covered	Percent
TOTAL		307	307	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
ALWAYS	178	6	6	100.00
CONT_ASSIGN	187	1	1	100.00
ALWAYS	190	4	4	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
122	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
			MISSING_ELSE
130	1	1
143	1	1
153	24	24
155	24	24
156	24	24
157	24	24
158	24	24
159	24	24
160	24	24
161	24	24
162	24	24
165	24	24
169	24	24
178	1	1
179	1	1
181	2	2
			MISSING_ELSE
183	2	2
			MISSING_ELSE
187	1	1
190	1	1
191	1	1
192	2	2
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
228	1	1
229	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1

---

Cond Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Cond Coverage for Module self-instances :

SCORE	COND
99.65	98.61

tb.dut.u_s1n_27

	Total	Covered	Percent
Conditions	72	71	98.61
Logical	72	71	98.61
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION ((dev_select_t == 3'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 3'(0))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION ((dev_select_t == 3'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 3'(1))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION ((dev_select_t == 3'(2)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 3'(2))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION ((dev_select_t == 3'(3)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (dev_select_t == 3'(3))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[2].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION (tl_t_o.a_valid & gen_u_o[3].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (gen_u_o[2].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       165
 EXPRESSION (gen_u_o[3].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       181
 EXPRESSION (dev_select_t == 3'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (dev_select_outstanding == 3'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       229
 EXPRESSION (tl_t_o.a_valid & (dev_select_t >= 3'(N)) & ((~hold_all_requests)))
             -------1------   -----------2-----------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T25,T11,T12
1	1	1	Covered	T1,T4,T5

---

Cond Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Cond Coverage for Module self-instances :

SCORE	COND
97.84	91.35

tb.dut.u_s1n_32

SCORE	COND
97.92	91.67

tb.dut.u_s1n_57

	Total	Covered	Percent
Conditions	312	286	91.67
Logical	312	286	91.67
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
112-187	91.83
192-229	83.33

---

Branch Coverage for Module : tlul_socket_1n ( parameter N=4,HReqPass=1,HRspPass=1,DReqPass=15,DRspPass=15,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=3,OutstandingW=9 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.65	100.00

tb.dut.u_s1n_27

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
IF	116	5	5	100.00
IF	181	2	2	100.00
IF	183	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	119	if (accept_t_req)
-3-:	120	if ((!accept_t_rsp))
-4-:	125	if (accept_t_rsp)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Covered	T1,T2,T3
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	181	if ((dev_select_t == 3'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (hold_all_requests)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if ((dev_select_outstanding == 3'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_socket_1n ( parameter N=24,HReqPass=1,HRspPass=1,DReqPass=16777215,DRspPass=16777215,HReqDepth=0,HRspDepth=0,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 + N=24,HReqPass=0,HRspPass=0,DReqPass=16777215,DRspPass=16777215,HReqDepth=1,HRspDepth=1,DReqDepth=0,DRspDepth=0,ExplicitErrs=1,NWD=5,OutstandingW=9 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.84	100.00

tb.dut.u_s1n_32

SCORE	BRANCH
97.92	100.00

tb.dut.u_s1n_57

	Line No.	Total	Covered	Percent
Branches		107	107	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
TERNARY	162	2	2	100.00
TERNARY	165	2	2	100.00
IF	116	5	5	100.00
IF	181	2	2	100.00
IF	183	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	162	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[2].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[3].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[4].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[4].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[5].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[5].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[6].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[6].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[7].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[7].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[8].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[8].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[9].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[9].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[10].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[10].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[11].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[11].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[12].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[12].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[13].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[13].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[14].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[14].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[15].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[15].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[16].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[16].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[17].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[17].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[18].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[18].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[19].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[19].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[20].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[20].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[21].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[21].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[22].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[22].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	162	(gen_u_o[23].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	(gen_u_o[23].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	119	if (accept_t_req)
-3-:	120	if ((!accept_t_rsp))
-4-:	125	if (accept_t_rsp)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Covered	T1,T2,T3
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	181	if ((dev_select_t == 5'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (hold_all_requests)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if ((dev_select_outstanding == 5'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_1n

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NotOverflowed_A	8251850	8251850	0	0
maxN	2700	2700	0	0

NotOverflowed_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8251850	8251850	0	0
T1	7945	7945	0	0
T2	482	482	0	0
T3	493	493	0	0
T4	6786	6786	0	0
T5	6786	6786	0	0
T6	7935	7935	0	0
T7	491	491	0	0
T8	496	496	0	0
T9	8054	8054	0	0
T10	493	493	0	0

maxN

Name	Attempts	Real Successes	Failures	Incomplete
Total	2700	2700	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0