Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1482752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235762

1

T1

72

T2

637

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	583505	1			T1	266		T2	1597		T3	62
values[0x0]	550428	1			T1	53		T2	1596		T3	59
values[0x1]	584581	1			T1	299		T2	1519		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1145462	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

573052

1

T1

241

T2

1544

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27560	1			T1	9		T2	70		T3	6
valid_sources[0x01]	25690	1			T1	9		T2	75		T4	1
valid_sources[0x02]	27908	1			T1	13		T2	73		T5	38
valid_sources[0x03]	28135	1			T1	20		T2	77		T4	1
valid_sources[0x04]	25946	1			T1	9		T2	61		T5	8
valid_sources[0x05]	27800	1			T1	8		T2	76		T5	20
valid_sources[0x06]	27243	1			T1	10		T2	75		T5	13
valid_sources[0x07]	26743	1			T1	7		T2	68		T4	1
valid_sources[0x08]	26321	1			T1	14		T2	68		T4	1
valid_sources[0x09]	27502	1			T1	8		T2	79		T4	1
valid_sources[0x0a]	28334	1			T1	13		T2	72		T3	1
valid_sources[0x0b]	27003	1			T1	10		T2	57		T5	20
valid_sources[0x0c]	26374	1			T1	10		T2	72		T4	1
valid_sources[0x0d]	26209	1			T1	13		T2	75		T5	24
valid_sources[0x0e]	26980	1			T1	14		T2	77		T5	18
valid_sources[0x0f]	27024	1			T1	8		T2	60		T4	1
valid_sources[0x10]	26558	1			T1	8		T2	67		T5	18
valid_sources[0x11]	26583	1			T1	12		T2	77		T3	6
valid_sources[0x12]	26770	1			T1	12		T2	77		T5	25
valid_sources[0x13]	26131	1			T1	5		T2	76		T3	15
valid_sources[0x14]	26806	1			T1	12		T2	81		T5	14
valid_sources[0x15]	26509	1			T1	12		T2	74		T5	11
valid_sources[0x16]	26979	1			T1	6		T2	75		T5	19
valid_sources[0x17]	26255	1			T1	7		T2	82		T5	22
valid_sources[0x18]	27426	1			T1	14		T2	62		T5	20
valid_sources[0x19]	27541	1			T1	6		T2	71		T5	15
valid_sources[0x1a]	28112	1			T1	15		T2	63		T3	10
valid_sources[0x1b]	26232	1			T1	4		T2	74		T3	22
valid_sources[0x1c]	27401	1			T1	12		T2	78		T3	8
valid_sources[0x1d]	27514	1			T1	16		T2	69		T3	31
valid_sources[0x1e]	27044	1			T1	6		T2	70		T5	9
valid_sources[0x1f]	26875	1			T1	7		T2	77		T5	23
valid_sources[0x20]	26684	1			T1	13		T2	78		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24895

1

T1

20

T2

47

T3

5

values[0x0]

all_enables

biggest_size

186158

1

T1

23

T2

536

T3

20

values[0x1]

all_enables

biggest_size

24709

1

T1

29

T2

54

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1491545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241937

1

T1

68

T2

624

T3

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	593991	1			T1	289		T2	1524		T3	38
values[0x0]	545213	1			T1	57		T2	1431		T3	34
values[0x1]	594278	1			T1	312		T2	1538		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1144849	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

588633

1

T1

248

T2

1548

T3

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26688	1			T1	11		T2	62		T3	1
valid_sources[0x01]	27019	1			T1	15		T2	74		T3	2
valid_sources[0x02]	27352	1			T1	14		T2	67		T4	1
valid_sources[0x03]	27420	1			T1	19		T2	79		T4	1
valid_sources[0x04]	27385	1			T1	9		T2	96		T3	1
valid_sources[0x05]	28163	1			T1	15		T2	77		T3	1
valid_sources[0x06]	26822	1			T1	7		T2	60		T3	1
valid_sources[0x07]	26747	1			T1	12		T2	40		T3	4
valid_sources[0x08]	26196	1			T1	12		T2	55		T3	1
valid_sources[0x09]	26877	1			T1	11		T2	92		T3	2
valid_sources[0x0a]	27593	1			T1	11		T2	36		T3	2
valid_sources[0x0b]	26263	1			T1	13		T2	33		T3	2
valid_sources[0x0c]	27411	1			T1	8		T2	91		T3	2
valid_sources[0x0d]	26482	1			T1	12		T2	50		T4	1
valid_sources[0x0e]	27036	1			T1	10		T2	60		T5	18
valid_sources[0x0f]	27128	1			T1	6		T2	45		T3	1
valid_sources[0x10]	27873	1			T1	13		T2	88		T3	5
valid_sources[0x11]	26552	1			T1	10		T2	65		T4	1
valid_sources[0x12]	27393	1			T1	8		T2	60		T5	14
valid_sources[0x13]	27830	1			T1	12		T2	33		T3	4
valid_sources[0x14]	26732	1			T1	9		T2	112		T3	3
valid_sources[0x15]	27355	1			T1	16		T2	41		T3	3
valid_sources[0x16]	27410	1			T1	6		T2	47		T3	3
valid_sources[0x17]	27065	1			T1	15		T2	99		T4	2
valid_sources[0x18]	26590	1			T1	10		T2	57		T5	12
valid_sources[0x19]	27293	1			T1	4		T2	86		T5	8
valid_sources[0x1a]	27155	1			T1	10		T2	55		T3	1
valid_sources[0x1b]	27164	1			T1	5		T2	87		T3	3
valid_sources[0x1c]	26708	1			T1	12		T2	81		T3	1
valid_sources[0x1d]	27356	1			T1	12		T2	94		T5	16
valid_sources[0x1e]	27318	1			T1	6		T2	90		T3	5
valid_sources[0x1f]	26520	1			T1	8		T2	55		T3	2
valid_sources[0x20]	26386	1			T1	18		T2	59		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25548

1

T1

26

T2

66

T3

1

values[0x0]

all_enables

biggest_size

190830

1

T1

21

T2

481

T3

9

values[0x1]

all_enables

biggest_size

25559

1

T1

21

T2

77

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1490344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236763

1

T1

82

T2

617

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586803	1			T1	329		T2	1481		T3	67
values[0x0]	553696	1			T1	47		T2	1430		T3	75
values[0x1]	586608	1			T1	296		T2	1503		T3	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1151491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

575616

1

T1

273

T2

1451

T3

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27928	1			T1	14		T2	70		T3	1
valid_sources[0x01]	27323	1			T1	12		T2	66		T3	6
valid_sources[0x02]	27554	1			T1	6		T2	62		T3	4
valid_sources[0x03]	26312	1			T1	14		T2	72		T3	9
valid_sources[0x04]	26103	1			T1	12		T2	66		T3	3
valid_sources[0x05]	27315	1			T1	11		T2	61		T3	5
valid_sources[0x06]	26855	1			T1	15		T2	65		T3	4
valid_sources[0x07]	26480	1			T1	13		T2	63		T3	4
valid_sources[0x08]	26804	1			T1	14		T2	69		T3	2
valid_sources[0x09]	27561	1			T1	8		T2	73		T3	1
valid_sources[0x0a]	28030	1			T1	8		T2	79		T3	1
valid_sources[0x0b]	27192	1			T1	11		T2	73		T3	1
valid_sources[0x0c]	26983	1			T1	6		T2	66		T3	5
valid_sources[0x0d]	27309	1			T1	15		T2	66		T3	2
valid_sources[0x0e]	26459	1			T1	16		T2	57		T3	2
valid_sources[0x0f]	26922	1			T1	16		T2	78		T3	5
valid_sources[0x10]	27989	1			T1	9		T2	69		T3	11
valid_sources[0x11]	26692	1			T1	5		T2	66		T3	1
valid_sources[0x12]	27116	1			T1	11		T2	72		T3	4
valid_sources[0x13]	26310	1			T1	10		T2	73		T3	6
valid_sources[0x14]	26978	1			T1	10		T2	71		T3	2
valid_sources[0x15]	26152	1			T1	14		T2	69		T3	1
valid_sources[0x16]	27108	1			T1	9		T2	78		T3	6
valid_sources[0x17]	27893	1			T1	8		T2	65		T3	1
valid_sources[0x18]	27043	1			T1	8		T2	72		T4	1
valid_sources[0x19]	27446	1			T1	12		T2	75		T5	18
valid_sources[0x1a]	27227	1			T1	11		T2	75		T3	4
valid_sources[0x1b]	26478	1			T1	6		T2	72		T3	2
valid_sources[0x1c]	27228	1			T1	7		T2	65		T3	3
valid_sources[0x1d]	27498	1			T1	11		T2	73		T3	3
valid_sources[0x1e]	26794	1			T1	10		T2	59		T3	3
valid_sources[0x1f]	27126	1			T1	10		T2	67		T3	2
valid_sources[0x20]	25431	1			T1	6		T2	75		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24743

1

T1

28

T2

62

T3

3

values[0x0]

all_enables

biggest_size

186595

1

T1

21

T2

488

T3

30

values[0x1]

all_enables

biggest_size

25425

1

T1

33

T2

67

T3

3