Unified Coverage Report :: Module

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_28.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_28.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_29.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_29.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_31.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_31.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_33.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_33.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_34.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_34.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_43.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_43.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_44.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_44.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_45.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_45.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_46.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_46.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_47.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_47.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_48.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_48.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_49.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_49.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_50.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_50.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_51.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_51.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_52.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_52.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_53.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_53.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_54.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_54.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_55.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_55.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_56.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_sm1_56.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_s1n_57.fifo_h.reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	100.00	85.29			90.00	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_29.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_29.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_31.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_31.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_34.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_34.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.fifo_h.reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.11	100.00	76.92			87.50	100.00	reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.07	100.00	80.77			87.50	100.00	rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_28.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_29.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_31.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_33.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_34.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_43.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_44.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_45.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_46.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_47.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_48.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_49.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_50.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_51.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_52.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_53.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_54.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_55.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_sm1_56.u_devicefifo.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T3,T4
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_57.fifo_h.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_s1n_57.fifo_h.reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	74	7	6	85.71
ALWAYS	86	7	6	85.71

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
74	1	1
75	1	1
76	1	1
77		unreachable
78	1	1
79	1	1
80	1	1
81	0	1
			MISSING_ELSE
86	1	1
87	1	1
88	1	1
89		unreachable
90	1	1
91	1	1
92	1	1
93	0	1
			MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_s1n_57.fifo_h.rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	74	4	3	75.00
IF	86	4	3	75.00



	LineNo.	Expression
-1-:	74	if ((!rst_ni))
-2-:	76	if (clr_i)
-3-:	78	if (wptr_wrap)
-4-:	80	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	86	if ((!rst_ni))
-2-:	88	if (clr_i)
-3-:	90	if (rptr_wrap)
-4-:	92	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3