Line Coverage for Module :
prim_fifo_sync ( parameter Width=110,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=112,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) 
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 4 | 4 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 44 |
1 |
1 |
| 45 |
1 |
1 |
| 48 |
1 |
1 |
| 49 |
1 |
1 |
| 53 |
|
unreachable |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 22 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| ALWAYS | 157 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
| 72 |
1 |
1 |
| 73 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 98 |
1 |
1 |
| 99 |
1 |
1 |
| 100 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 154 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 172 |
1 |
1 |
| 173 |
1 |
1 |
| 180 |
1 |
1 |
Line Coverage for Module :
prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 22 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| ALWAYS | 157 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 70 |
1 |
1 |
| 71 |
1 |
1 |
| 72 |
1 |
1 |
| 73 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 98 |
1 |
1 |
| 99 |
1 |
1 |
| 100 |
1 |
1 |
| 145 |
1 |
1 |
| 146 |
1 |
1 |
| 154 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
|
|
|
MISSING_ELSE |
| 175 |
1 |
1 |
| 176 |
1 |
1 |
| 180 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 26 | 21 | 80.77 |
| Logical | 26 | 21 | 80.77 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 34 | 29 | 85.29 |
| Logical | 34 | 29 | 85.29 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T5 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 172
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 172
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 173
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 26 | 21 | 80.77 |
| Logical | 26 | 21 | 80.77 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_sync ( parameter Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 26 | 20 | 76.92 |
| Logical | 26 | 20 | 76.92 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=65,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=108,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=112,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
7 |
87.50 |
| TERNARY |
88 |
3 |
2 |
66.67 |
| TERNARY |
180 |
2 |
2 |
100.00 |
| IF |
70 |
2 |
2 |
100.00 |
| IF |
157 |
1 |
1 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Excluded |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Excluded |
T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
9 |
90.00 |
| TERNARY |
88 |
3 |
2 |
66.67 |
| TERNARY |
172 |
2 |
2 |
100.00 |
| TERNARY |
180 |
1 |
1 |
100.00 |
| IF |
70 |
2 |
2 |
100.00 |
| IF |
157 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T5 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 172 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Excluded |
T1,T2,T3 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Excluded |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 157 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1320304036 |
0 |
0 |
| T1 |
113081820 |
2362409 |
0 |
0 |
| T2 |
154330052 |
7511541 |
0 |
0 |
| T3 |
657096 |
5779 |
0 |
0 |
| T4 |
716832 |
16946 |
0 |
0 |
| T5 |
6730780 |
73538 |
0 |
0 |
| T6 |
9741946 |
195299 |
0 |
0 |
| T7 |
581902 |
4930 |
0 |
0 |
| T8 |
34040874 |
3544169 |
0 |
0 |
| T9 |
804340 |
6162 |
0 |
0 |
| T10 |
70049368 |
700971 |
0 |
0 |
| T11 |
0 |
692 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
113081820 |
113057454 |
0 |
0 |
| T2 |
154330052 |
154329004 |
0 |
0 |
| T3 |
657096 |
649760 |
0 |
0 |
| T4 |
716832 |
706090 |
0 |
0 |
| T5 |
6730780 |
6718990 |
0 |
0 |
| T6 |
9741946 |
9375146 |
0 |
0 |
| T7 |
581902 |
568278 |
0 |
0 |
| T8 |
34040874 |
34040088 |
0 |
0 |
| T9 |
804340 |
790716 |
0 |
0 |
| T10 |
70049368 |
70039412 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
113081820 |
113057454 |
0 |
0 |
| T2 |
154330052 |
154329004 |
0 |
0 |
| T3 |
657096 |
649760 |
0 |
0 |
| T4 |
716832 |
706090 |
0 |
0 |
| T5 |
6730780 |
6718990 |
0 |
0 |
| T6 |
9741946 |
9375146 |
0 |
0 |
| T7 |
581902 |
568278 |
0 |
0 |
| T8 |
34040874 |
34040088 |
0 |
0 |
| T9 |
804340 |
790716 |
0 |
0 |
| T10 |
70049368 |
70039412 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
113081820 |
113057454 |
0 |
0 |
| T2 |
154330052 |
154329004 |
0 |
0 |
| T3 |
657096 |
649760 |
0 |
0 |
| T4 |
716832 |
706090 |
0 |
0 |
| T5 |
6730780 |
6718990 |
0 |
0 |
| T6 |
9741946 |
9375146 |
0 |
0 |
| T7 |
581902 |
568278 |
0 |
0 |
| T8 |
34040874 |
34040088 |
0 |
0 |
| T9 |
804340 |
790716 |
0 |
0 |
| T10 |
70049368 |
70039412 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
428130173 |
0 |
0 |
| T1 |
17264400 |
819218 |
0 |
0 |
| T2 |
23561840 |
2196181 |
0 |
0 |
| T3 |
100320 |
1829 |
0 |
0 |
| T4 |
109440 |
4832 |
0 |
0 |
| T5 |
1027600 |
34718 |
0 |
0 |
| T6 |
1487320 |
49828 |
0 |
0 |
| T7 |
88840 |
1381 |
0 |
0 |
| T8 |
5197080 |
1062752 |
0 |
0 |
| T9 |
122800 |
1824 |
0 |
0 |
| T10 |
10694560 |
181533 |
0 |
0 |
| T11 |
0 |
134 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
194472 |
194472 |
0 |
0 |
| T1 |
222 |
222 |
0 |
0 |
| T2 |
222 |
222 |
0 |
0 |
| T3 |
222 |
222 |
0 |
0 |
| T4 |
222 |
222 |
0 |
0 |
| T5 |
222 |
222 |
0 |
0 |
| T6 |
222 |
222 |
0 |
0 |
| T7 |
222 |
222 |
0 |
0 |
| T8 |
222 |
222 |
0 |
0 |
| T9 |
222 |
222 |
0 |
0 |
| T10 |
222 |
222 |
0 |
0 |