Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21024	21024	0	0
GntImpliesReady_A	2147483647	7882849	0	0
GntImpliesValid_A	2147483647	7882849	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7882849	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	419833222	0	0
ReadyAndValidImplyGrant_A	2147483647	7882849	0	0
ReqAndReadyImplyGrant_A	2147483647	7882849	0	0
ReqImpliesValid_A	2147483647	31963482	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	52080	0	21024
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7882849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10358640	10356408	0	0
T2	14137104	14137008	0	0
T3	60192	59520	0	0
T4	65664	64680	0	0
T5	616560	615480	0	0
T6	892392	858792	0	0
T7	53304	52056	0	0
T8	3118248	3118176	0	0
T9	73680	72432	0	0
T10	6416736	6415824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21024	21024	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10358640	10356408	0	0
T2	14137104	14137008	0	0
T3	60192	59520	0	0
T4	65664	64680	0	0
T5	616560	615480	0	0
T6	892392	858792	0	0
T7	53304	52056	0	0
T8	3118248	3118176	0	0
T9	73680	72432	0	0
T10	6416736	6415824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10358640	10356408	0	0
T2	14137104	14137008	0	0
T3	60192	59520	0	0
T4	65664	64680	0	0
T5	616560	615480	0	0
T6	892392	858792	0	0
T7	53304	52056	0	0
T8	3118248	3118176	0	0
T9	73680	72432	0	0
T10	6416736	6415824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	419833222	0	0
T1	10358640	592551	0	0
T2	14137104	540236	0	0
T3	60192	824	0	0
T4	65664	1709	0	0
T5	616560	36821	0	0
T6	892392	19339	0	0
T7	53304	648	0	0
T8	3118248	131648	0	0
T9	73680	1004	0	0
T10	6416736	223976	0	0
T11	0	157	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31963482	0	0
T1	10358640	196361	0	0
T2	14137104	33265	0	0
T3	60192	603	0	0
T4	65664	1827	0	0
T5	616560	4013	0	0
T6	892392	21875	0	0
T7	53304	515	0	0
T8	3118248	8814	0	0
T9	73680	592	0	0
T10	6416736	563	0	0
T11	0	114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52080	0	21024
T1	863220	32	0	2
T2	1178092	0	0	2
T3	5016	0	0	2
T4	5472	5	0	2
T5	51380	0	0	2
T6	74366	40	0	2
T7	4442	0	0	2
T8	259854	0	0	2
T9	6140	0	0	2
T10	534728	0	0	2
T11	0	2	0	0
T12	0	94	0	0
T13	0	3	0	0
T14	0	854	0	0
T15	0	10	0	0
T16	0	2	0	0
T17	0	30	0	0
T18	0	9	0	0
T19	0	646	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10358640	10356408	0	0
T2	14137104	14137008	0	0
T3	60192	59520	0	0
T4	65664	64680	0	0
T5	616560	615480	0	0
T6	892392	858792	0	0
T7	53304	52056	0	0
T8	3118248	3118176	0	0
T9	73680	72432	0	0
T10	6416736	6415824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7882849	0	0
T1	10358640	42502	0	0
T2	14137104	13616	0	0
T3	60192	498	0	0
T4	65664	1555	0	0
T5	616560	1845	0	0
T6	892392	16422	0	0
T7	53304	432	0	0
T8	3118248	5231	0	0
T9	73680	521	0	0
T10	6416736	355	0	0
T11	0	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	885775	0	0
GntImpliesValid_A	389577334	885775	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	885775	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	11093569	0	0
ReadyAndValidImplyGrant_A	389577334	885775	0	0
ReqAndReadyImplyGrant_A	389577334	885775	0	0
ReqImpliesValid_A	389577334	2368669	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	885775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	11093569	0	0
T1	431610	30652	0	0
T2	589046	8383	0	0
T3	2508	32	0	0
T4	2736	129	0	0
T5	25690	1418	0	0
T6	37183	1412	0	0
T7	2221	39	0	0
T8	129927	2470	0	0
T9	3070	37	0	0
T10	267364	130	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2368669	0	0
T1	431610	10184	0	0
T2	589046	4973	0	0
T3	2508	53	0	0
T4	2736	220	0	0
T5	25690	280	0	0
T6	37183	2390	0	0
T7	2221	62	0	0
T8	129927	885	0	0
T9	3070	48	0	0
T10	267364	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	885775	0	0
T1	431610	4440	0	0
T2	589046	2387	0	0
T3	2508	42	0	0
T4	2736	174	0	0
T5	25690	187	0	0
T6	37183	1895	0	0
T7	2221	50	0	0
T8	129927	613	0	0
T9	3070	42	0	0
T10	267364	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	871462	0	0
GntImpliesValid_A	389577334	871462	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	871462	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	10866690	0	0
ReadyAndValidImplyGrant_A	389577334	871462	0	0
ReqAndReadyImplyGrant_A	389577334	871462	0	0
ReqImpliesValid_A	389577334	2252726	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	871462	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	10866690	0	0
T1	431610	27338	0	0
T2	589046	6299	0	0
T3	2508	31	0	0
T4	2736	130	0	0
T5	25690	1263	0	0
T6	37183	1509	0	0
T7	2221	24	0	0
T8	129927	2658	0	0
T9	3070	44	0	0
T10	267364	161	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2252726	0	0
T1	431610	12289	0	0
T2	589046	3299	0	0
T3	2508	48	0	0
T4	2736	213	0	0
T5	25690	280	0	0
T6	37183	3186	0	0
T7	2221	47	0	0
T8	129927	836	0	0
T9	3070	69	0	0
T10	267364	54	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	871462	0	0
T1	431610	4202	0	0
T2	589046	1718	0	0
T3	2508	39	0	0
T4	2736	171	0	0
T5	25690	186	0	0
T6	37183	2342	0	0
T7	2221	35	0	0
T8	129927	609	0	0
T9	3070	56	0	0
T10	267364	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	217541	0	0
GntImpliesValid_A	389577334	217541	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	217541	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2701115	0	0
ReadyAndValidImplyGrant_A	389577334	217541	0	0
ReqAndReadyImplyGrant_A	389577334	217541	0	0
ReqImpliesValid_A	389577334	534850	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	217541	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2701115	0	0
T1	431610	3027	0	0
T2	589046	1	0	0
T3	2508	15	0	0
T4	2736	45	0	0
T5	25690	393	0	0
T6	37183	586	0	0
T7	2221	15	0	0
T8	129927	532	0	0
T9	3070	13	0	0
T10	267364	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	534850	0	0
T1	431610	454	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	46	0	0
T5	25690	86	0	0
T6	37183	864	0	0
T7	2221	14	0	0
T8	129927	160	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	217541	0	0
T1	431610	397	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	52	0	0
T6	37183	719	0	0
T7	2221	14	0	0
T8	129927	128	0	0
T9	3070	12	0	0
T10	267364	7	0	0
T11	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	225694	0	0
GntImpliesValid_A	389577334	225694	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	225694	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2772886	0	0
ReadyAndValidImplyGrant_A	389577334	225694	0	0
ReqAndReadyImplyGrant_A	389577334	225694	0	0
ReqImpliesValid_A	389577334	566244	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	225694	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2772886	0	0
T1	431610	7800	0	0
T2	589046	1	0	0
T3	2508	16	0	0
T4	2736	42	0	0
T5	25690	346	0	0
T6	37183	305	0	0
T7	2221	11	0	0
T8	129927	725	0	0
T9	3070	14	0	0
T10	267364	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	566244	0	0
T1	431610	5412	0	0
T2	589046	0	0	0
T3	2508	17	0	0
T4	2736	47	0	0
T5	25690	46	0	0
T6	37183	1197	0	0
T7	2221	10	0	0
T8	129927	217	0	0
T9	3070	15	0	0
T10	267364	27	0	0
T11	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	225694	0	0
T1	431610	1851	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	44	0	0
T5	25690	46	0	0
T6	37183	745	0	0
T7	2221	10	0	0
T8	129927	176	0	0
T9	3070	14	0	0
T10	267364	17	0	0
T11	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	210496	0	0
GntImpliesValid_A	389577334	210496	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	210496	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	4443982	0	0
ReadyAndValidImplyGrant_A	389577334	210496	0	0
ReqAndReadyImplyGrant_A	389577334	210496	0	0
ReqImpliesValid_A	389577334	1046371	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	210496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	4443982	0	0
T1	431610	11103	0	0
T2	589046	0	0	0
T3	2508	253	0	0
T4	2736	112	0	0
T5	25690	899	0	0
T6	37183	3099	0	0
T7	2221	97	0	0
T8	129927	4244	0	0
T9	3070	72	0	0
T10	267364	74	0	0
T11	0	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	1046371	0	0
T1	431610	818	0	0
T2	589046	0	0	0
T3	2508	90	0	0
T4	2736	45	0	0
T5	25690	55	0	0
T6	37183	2520	0	0
T7	2221	34	0	0
T8	129927	510	0	0
T9	3070	18	0	0
T10	267364	12	0	0
T11	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	210496	0	0
T1	431610	435	0	0
T2	589046	0	0	0
T3	2508	24	0	0
T4	2736	28	0	0
T5	25690	52	0	0
T6	37183	781	0	0
T7	2221	19	0	0
T8	129927	157	0	0
T9	3070	11	0	0
T10	267364	12	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	205367	0	0
GntImpliesValid_A	389577334	205367	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	205367	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	4608423	0	0
ReadyAndValidImplyGrant_A	389577334	205367	0	0
ReqAndReadyImplyGrant_A	389577334	205367	0	0
ReqImpliesValid_A	389577334	997781	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	205367	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	4608423	0	0
T1	431610	15401	0	0
T2	589046	0	0	0
T3	2508	95	0	0
T4	2736	307	0	0
T5	25690	757	0	0
T6	37183	2578	0	0
T7	2221	167	0	0
T8	129927	1213	0	0
T9	3070	354	0	0
T10	267364	117	0	0
T11	0	27	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	997781	0	0
T1	431610	14148	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	123	0	0
T5	25690	98	0	0
T6	37183	517	0	0
T7	2221	46	0	0
T8	129927	235	0	0
T9	3070	50	0	0
T10	267364	12	0	0
T11	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205367	0	0
T1	431610	1354	0	0
T2	589046	0	0	0
T3	2508	16	0	0
T4	2736	62	0	0
T5	25690	54	0	0
T6	37183	327	0	0
T7	2221	15	0	0
T8	129927	144	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	230025	0	0
GntImpliesValid_A	389577334	230025	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	230025	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	4125152	0	0
ReadyAndValidImplyGrant_A	389577334	230025	0	0
ReqAndReadyImplyGrant_A	389577334	230025	0	0
ReqImpliesValid_A	389577334	1142307	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	230025	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	4125152	0	0
T1	431610	6621	0	0
T2	589046	10189	0	0
T3	2508	87	0	0
T4	2736	178	0	0
T5	25690	990	0	0
T6	37183	2866	0	0
T7	2221	52	0	0
T8	129927	727	0	0
T9	3070	153	0	0
T10	267364	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	1142307	0	0
T1	431610	2465	0	0
T2	589046	4625	0	0
T3	2508	18	0	0
T4	2736	77	0	0
T5	25690	78	0	0
T6	37183	1408	0	0
T7	2221	11	0	0
T8	129927	168	0	0
T9	3070	20	0	0
T10	267364	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230025	0	0
T1	431610	859	0	0
T2	589046	1061	0	0
T3	2508	13	0	0
T4	2736	41	0	0
T5	25690	45	0	0
T6	37183	433	0	0
T7	2221	11	0	0
T8	129927	129	0	0
T9	3070	20	0	0
T10	267364	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	218870	0	0
GntImpliesValid_A	389577334	218870	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	218870	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	4510209	0	0
ReadyAndValidImplyGrant_A	389577334	218870	0	0
ReqAndReadyImplyGrant_A	389577334	218870	0	0
ReqImpliesValid_A	389577334	1056076	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	218870	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	4510209	0	0
T1	431610	8471	0	0
T2	589046	0	0	0
T3	2508	53	0	0
T4	2736	206	0	0
T5	25690	2365	0	0
T6	37183	1834	0	0
T7	2221	47	0	0
T8	129927	844	0	0
T9	3070	76	0	0
T10	267364	26	0	0
T11	0	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	1056076	0	0
T1	431610	526	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	84	0	0
T5	25690	329	0	0
T6	37183	315	0	0
T7	2221	9	0	0
T8	129927	148	0	0
T9	3070	11	0	0
T10	267364	10	0	0
T11	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	218870	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	11	0	0
T4	2736	48	0	0
T5	25690	60	0	0
T6	37183	276	0	0
T7	2221	9	0	0
T8	129927	131	0	0
T9	3070	11	0	0
T10	267364	7	0	0
T11	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	211188	0	0
GntImpliesValid_A	389577334	211188	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	211188	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2726843	0	0
ReadyAndValidImplyGrant_A	389577334	211188	0	0
ReqAndReadyImplyGrant_A	389577334	211188	0	0
ReqImpliesValid_A	389577334	553607	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	211188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2726843	0	0
T1	431610	8532	0	0
T2	589046	3033	0	0
T3	2508	17	0	0
T4	2736	43	0	0
T5	25690	253	0	0
T6	37183	310	0	0
T7	2221	13	0	0
T8	129927	636	0	0
T9	3070	21	0	0
T10	267364	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	553607	0	0
T1	431610	10750	0	0
T2	589046	2296	0	0
T3	2508	22	0	0
T4	2736	44	0	0
T5	25690	43	0	0
T6	37183	318	0	0
T7	2221	12	0	0
T8	129927	182	0	0
T9	3070	20	0	0
T10	267364	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	211188	0	0
T1	431610	1878	0	0
T2	589046	919	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	43	0	0
T6	37183	308	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	20	0	0
T10	267364	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	220765	0	0
GntImpliesValid_A	389577334	220765	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	220765	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2753270	0	0
ReadyAndValidImplyGrant_A	389577334	220765	0	0
ReqAndReadyImplyGrant_A	389577334	220765	0	0
ReqImpliesValid_A	389577334	586769	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	220765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2753270	0	0
T1	431610	15587	0	0
T2	589046	1	0	0
T3	2508	14	0	0
T4	2736	41	0	0
T5	25690	349	0	0
T6	37183	551	0	0
T7	2221	17	0	0
T8	129927	605	0	0
T9	3070	21	0	0
T10	267364	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	586769	0	0
T1	431610	7764	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	50	0	0
T5	25690	67	0	0
T6	37183	1153	0	0
T7	2221	22	0	0
T8	129927	165	0	0
T9	3070	20	0	0
T10	267364	11	0	0
T11	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220765	0	0
T1	431610	2389	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	51	0	0
T6	37183	846	0	0
T7	2221	19	0	0
T8	129927	133	0	0
T9	3070	20	0	0
T10	267364	10	0	0
T11	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	220732	0	0
GntImpliesValid_A	389577334	220732	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	220732	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2729998	0	0
ReadyAndValidImplyGrant_A	389577334	220732	0	0
ReqAndReadyImplyGrant_A	389577334	220732	0	0
ReqImpliesValid_A	389577334	530081	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	220732	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2729998	0	0
T1	431610	3757	0	0
T2	589046	3580	0	0
T3	2508	21	0	0
T4	2736	37	0	0
T5	25690	371	0	0
T6	37183	339	0	0
T7	2221	12	0	0
T8	129927	550	0	0
T9	3070	23	0	0
T10	267364	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	530081	0	0
T1	431610	4642	0	0
T2	589046	2401	0	0
T3	2508	20	0	0
T4	2736	38	0	0
T5	25690	76	0	0
T6	37183	345	0	0
T7	2221	11	0	0
T8	129927	149	0	0
T9	3070	22	0	0
T10	267364	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	220732	0	0
T1	431610	858	0	0
T2	589046	1055	0	0
T3	2508	20	0	0
T4	2736	37	0	0
T5	25690	57	0	0
T6	37183	336	0	0
T7	2221	11	0	0
T8	129927	131	0	0
T9	3070	22	0	0
T10	267364	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	205838	0	0
GntImpliesValid_A	389577334	205838	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	205838	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2667670	0	0
ReadyAndValidImplyGrant_A	389577334	205838	0	0
ReqAndReadyImplyGrant_A	389577334	205838	0	0
ReqImpliesValid_A	389577334	516737	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	205838	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2667670	0	0
T1	431610	3511	0	0
T2	589046	1	0	0
T3	2508	21	0	0
T4	2736	39	0	0
T5	25690	352	0	0
T6	37183	323	0	0
T7	2221	14	0	0
T8	129927	574	0	0
T9	3070	13	0	0
T10	267364	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	516737	0	0
T1	431610	538	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	46	0	0
T5	25690	58	0	0
T6	37183	319	0	0
T7	2221	15	0	0
T8	129927	191	0	0
T9	3070	14	0	0
T10	267364	12	0	0
T11	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	205838	0	0
T1	431610	455	0	0
T2	589046	0	0	0
T3	2508	20	0	0
T4	2736	42	0	0
T5	25690	51	0	0
T6	37183	315	0	0
T7	2221	14	0	0
T8	129927	139	0	0
T9	3070	13	0	0
T10	267364	12	0	0
T11	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	227652	0	0
GntImpliesValid_A	389577334	227652	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	227652	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2782077	0	0
ReadyAndValidImplyGrant_A	389577334	227652	0	0
ReqAndReadyImplyGrant_A	389577334	227652	0	0
ReqImpliesValid_A	389577334	600112	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	227652	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2782077	0	0
T1	431610	3478	0	0
T2	589046	1	0	0
T3	2508	14	0	0
T4	2736	45	0	0
T5	25690	364	0	0
T6	37183	297	0	0
T7	2221	16	0	0
T8	129927	575	0	0
T9	3070	17	0	0
T10	267364	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	600112	0	0
T1	431610	487	0	0
T2	589046	0	0	0
T3	2508	17	0	0
T4	2736	50	0	0
T5	25690	55	0	0
T6	37183	291	0	0
T7	2221	19	0	0
T8	129927	159	0	0
T9	3070	18	0	0
T10	267364	17	0	0
T11	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	227652	0	0
T1	431610	459	0	0
T2	589046	0	0	0
T3	2508	15	0	0
T4	2736	47	0	0
T5	25690	47	0	0
T6	37183	288	0	0
T7	2221	17	0	0
T8	129927	146	0	0
T9	3070	17	0	0
T10	267364	13	0	0
T11	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	215522	0	0
GntImpliesValid_A	389577334	215522	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	215522	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2758523	0	0
ReadyAndValidImplyGrant_A	389577334	215522	0	0
ReqAndReadyImplyGrant_A	389577334	215522	0	0
ReqImpliesValid_A	389577334	541928	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	215522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2758523	0	0
T1	431610	3329	0	0
T2	589046	3237	0	0
T3	2508	21	0	0
T4	2736	35	0	0
T5	25690	334	0	0
T6	37183	281	0	0
T7	2221	13	0	0
T8	129927	627	0	0
T9	3070	17	0	0
T10	267364	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	541928	0	0
T1	431610	564	0	0
T2	589046	2336	0	0
T3	2508	20	0	0
T4	2736	36	0	0
T5	25690	60	0	0
T6	37183	283	0	0
T7	2221	14	0	0
T8	129927	176	0	0
T9	3070	16	0	0
T10	267364	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215522	0	0
T1	431610	456	0	0
T2	589046	1005	0	0
T3	2508	20	0	0
T4	2736	35	0	0
T5	25690	56	0	0
T6	37183	276	0	0
T7	2221	13	0	0
T8	129927	157	0	0
T9	3070	16	0	0
T10	267364	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	230513	0	0
GntImpliesValid_A	389577334	230513	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	230513	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2770693	0	0
ReadyAndValidImplyGrant_A	389577334	230513	0	0
ReqAndReadyImplyGrant_A	389577334	230513	0	0
ReqImpliesValid_A	389577334	611249	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	230513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2770693	0	0
T1	431610	6256	0	0
T2	589046	1666	0	0
T3	2508	21	0	0
T4	2736	35	0	0
T5	25690	412	0	0
T6	37183	294	0	0
T7	2221	16	0	0
T8	129927	576	0	0
T9	3070	21	0	0
T10	267364	41	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	611249	0	0
T1	431610	9115	0	0
T2	589046	1146	0	0
T3	2508	24	0	0
T4	2736	38	0	0
T5	25690	80	0	0
T6	37183	290	0	0
T7	2221	21	0	0
T8	129927	151	0	0
T9	3070	20	0	0
T10	267364	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	230513	0	0
T1	431610	1490	0	0
T2	589046	481	0	0
T3	2508	22	0	0
T4	2736	36	0	0
T5	25690	49	0	0
T6	37183	286	0	0
T7	2221	18	0	0
T8	129927	140	0	0
T9	3070	20	0	0
T10	267364	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	215588	0	0
GntImpliesValid_A	389577334	215588	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	215588	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2740622	0	0
ReadyAndValidImplyGrant_A	389577334	215588	0	0
ReqAndReadyImplyGrant_A	389577334	215588	0	0
ReqImpliesValid_A	389577334	562013	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	215588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2740622	0	0
T1	431610	5877	0	0
T2	589046	1973	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	316	0	0
T6	37183	294	0	0
T7	2221	12	0	0
T8	129927	619	0	0
T9	3070	15	0	0
T10	267364	49	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	562013	0	0
T1	431610	14984	0	0
T2	589046	1167	0	0
T3	2508	16	0	0
T4	2736	33	0	0
T5	25690	45	0	0
T6	37183	290	0	0
T7	2221	11	0	0
T8	129927	178	0	0
T9	3070	14	0	0
T10	267364	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215588	0	0
T1	431610	1978	0	0
T2	589046	548	0	0
T3	2508	15	0	0
T4	2736	32	0	0
T5	25690	45	0	0
T6	37183	286	0	0
T7	2221	11	0	0
T8	129927	138	0	0
T9	3070	14	0	0
T10	267364	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	236353	0	0
GntImpliesValid_A	389577334	236353	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	236353	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2826249	0	0
ReadyAndValidImplyGrant_A	389577334	236353	0	0
ReqAndReadyImplyGrant_A	389577334	236353	0	0
ReqImpliesValid_A	389577334	592207	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	236353	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2826249	0	0
T1	431610	5662	0	0
T2	589046	1	0	0
T3	2508	14	0	0
T4	2736	47	0	0
T5	25690	786	0	0
T6	37183	543	0	0
T7	2221	13	0	0
T8	129927	479	0	0
T9	3070	11	0	0
T10	267364	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	592207	0	0
T1	431610	3546	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	58	0	0
T5	25690	133	0	0
T6	37183	641	0	0
T7	2221	16	0	0
T8	129927	136	0	0
T9	3070	12	0	0
T10	267364	11	0	0
T11	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	236353	0	0
T1	431610	972	0	0
T2	589046	0	0	0
T3	2508	13	0	0
T4	2736	52	0	0
T5	25690	96	0	0
T6	37183	586	0	0
T7	2221	14	0	0
T8	129927	116	0	0
T9	3070	11	0	0
T10	267364	11	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	222209	0	0
GntImpliesValid_A	389577334	222209	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	222209	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2762895	0	0
ReadyAndValidImplyGrant_A	389577334	222209	0	0
ReqAndReadyImplyGrant_A	389577334	222209	0	0
ReqImpliesValid_A	389577334	595300	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	222209	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2762895	0	0
T1	431610	3911	0	0
T2	589046	1734	0	0
T3	2508	20	0	0
T4	2736	40	0	0
T5	25690	545	0	0
T6	37183	450	0	0
T7	2221	13	0	0
T8	129927	660	0	0
T9	3070	14	0	0
T10	267364	21	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	595300	0	0
T1	431610	6362	0	0
T2	589046	1162	0	0
T3	2508	19	0	0
T4	2736	43	0	0
T5	25690	83	0	0
T6	37183	499	0	0
T7	2221	12	0	0
T8	129927	173	0	0
T9	3070	13	0	0
T10	267364	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	222209	0	0
T1	431610	994	0	0
T2	589046	532	0	0
T3	2508	19	0	0
T4	2736	41	0	0
T5	25690	66	0	0
T6	37183	469	0	0
T7	2221	12	0	0
T8	129927	147	0	0
T9	3070	13	0	0
T10	267364	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	224213	0	0
GntImpliesValid_A	389577334	224213	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	224213	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2792706	0	0
ReadyAndValidImplyGrant_A	389577334	224213	0	0
ReqAndReadyImplyGrant_A	389577334	224213	0	0
ReqImpliesValid_A	389577334	591775	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	224213	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2792706	0	0
T1	431610	15976	0	0
T2	589046	5138	0	0
T3	2508	13	0	0
T4	2736	30	0	0
T5	25690	411	0	0
T6	37183	350	0	0
T7	2221	16	0	0
T8	129927	626	0	0
T9	3070	20	0	0
T10	267364	51	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	591775	0	0
T1	431610	25741	0	0
T2	589046	3538	0	0
T3	2508	18	0	0
T4	2736	31	0	0
T5	25690	75	0	0
T6	37183	350	0	0
T7	2221	15	0	0
T8	129927	190	0	0
T9	3070	27	0	0
T10	267364	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	224213	0	0
T1	431610	3996	0	0
T2	589046	1551	0	0
T3	2508	15	0	0
T4	2736	30	0	0
T5	25690	55	0	0
T6	37183	344	0	0
T7	2221	15	0	0
T8	129927	152	0	0
T9	3070	23	0	0
T10	267364	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	216939	0	0
GntImpliesValid_A	389577334	216939	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	216939	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2736754	0	0
ReadyAndValidImplyGrant_A	389577334	216939	0	0
ReqAndReadyImplyGrant_A	389577334	216939	0	0
ReqImpliesValid_A	389577334	528382	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	216939	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2736754	0	0
T1	431610	3157	0	0
T2	589046	1651	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	316	0	0
T6	37183	283	0	0
T7	2221	18	0	0
T8	129927	547	0	0
T9	3070	19	0	0
T10	267364	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	528382	0	0
T1	431610	476	0	0
T2	589046	1138	0	0
T3	2508	24	0	0
T4	2736	50	0	0
T5	25690	54	0	0
T6	37183	281	0	0
T7	2221	19	0	0
T8	129927	153	0	0
T9	3070	18	0	0
T10	267364	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	216939	0	0
T1	431610	419	0	0
T2	589046	491	0	0
T3	2508	23	0	0
T4	2736	49	0	0
T5	25690	50	0	0
T6	37183	276	0	0
T7	2221	18	0	0
T8	129927	134	0	0
T9	3070	18	0	0
T10	267364	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	214647	0	0
GntImpliesValid_A	389577334	214647	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	214647	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2738698	0	0
ReadyAndValidImplyGrant_A	389577334	214647	0	0
ReqAndReadyImplyGrant_A	389577334	214647	0	0
ReqImpliesValid_A	389577334	568554	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	214647	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2738698	0	0
T1	431610	6644	0	0
T2	589046	1	0	0
T3	2508	15	0	0
T4	2736	35	0	0
T5	25690	464	0	0
T6	37183	516	0	0
T7	2221	10	0	0
T8	129927	579	0	0
T9	3070	10	0	0
T10	267364	47	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	568554	0	0
T1	431610	7385	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	36	0	0
T5	25690	81	0	0
T6	37183	750	0	0
T7	2221	9	0	0
T8	129927	187	0	0
T9	3070	11	0	0
T10	267364	10	0	0
T11	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	214647	0	0
T1	431610	1366	0	0
T2	589046	0	0	0
T3	2508	14	0	0
T4	2736	35	0	0
T5	25690	57	0	0
T6	37183	627	0	0
T7	2221	9	0	0
T8	129927	151	0	0
T9	3070	10	0	0
T10	267364	10	0	0
T11	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	215957	0	0
GntImpliesValid_A	389577334	215957	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	215957	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	2717947	0	0
ReadyAndValidImplyGrant_A	389577334	215957	0	0
ReqAndReadyImplyGrant_A	389577334	215957	0	0
ReqImpliesValid_A	389577334	536239	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	0	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	215957	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2717947	0	0
T1	431610	3330	0	0
T2	589046	1	0	0
T3	2508	11	0	0
T4	2736	50	0	0
T5	25690	377	0	0
T6	37183	306	0	0
T7	2221	11	0	0
T8	129927	549	0	0
T9	3070	17	0	0
T10	267364	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	536239	0	0
T1	431610	507	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	51	0	0
T5	25690	51	0	0
T6	37183	308	0	0
T7	2221	10	0	0
T8	129927	156	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	876

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	215957	0	0
T1	431610	439	0	0
T2	589046	0	0	0
T3	2508	10	0	0
T4	2736	50	0	0
T5	25690	42	0	0
T6	37183	301	0	0
T7	2221	10	0	0
T8	129927	136	0	0
T9	3070	16	0	0
T10	267364	8	0	0
T11	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	874743	0	0
GntImpliesValid_A	389577334	874743	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	874743	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	10354057	0	0
ReadyAndValidImplyGrant_A	389577334	874743	0	0
ReqAndReadyImplyGrant_A	389577334	874743	0	0
ReqImpliesValid_A	389577334	2209799	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	19224	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	874743	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	10354057	0	0
T1	431610	31954	0	0
T2	589046	3012	0	0
T3	2508	1	0	0
T4	2736	1	0	0
T5	25690	1288	0	0
T6	37183	12	0	0
T7	2221	1	0	0
T8	129927	1932	0	0
T9	3070	1	0	0
T10	267364	168	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	2209799	0	0
T1	431610	21641	0	0
T2	589046	1215	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	240	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	851	0	0
T9	3070	51	0	0
T10	267364	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	19224	0	876
T1	431610	27	0	1
T2	589046	0	0	1
T3	2508	0	0	1
T4	2736	1	0	1
T5	25690	0	0	1
T6	37183	19	0	1
T7	2221	0	0	1
T8	129927	0	0	1
T9	3070	0	0	1
T10	267364	0	0	1
T12	0	16	0	0
T13	0	1	0	0
T14	0	308	0	0
T15	0	2	0	0
T17	0	17	0	0
T18	0	9	0	0
T19	0	646	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	874743	0	0
T1	431610	6001	0	0
T2	589046	943	0	0
T3	2508	42	0	0
T4	2736	178	0	0
T5	25690	196	0	0
T6	37183	1672	0	0
T7	2221	42	0	0
T8	129927	631	0	0
T9	3070	51	0	0
T10	267364	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389577334	389465567	0	0
CheckNGreaterZero_A	876	876	0	0
GntImpliesReady_A	389577334	864760	0	0
GntImpliesValid_A	389577334	864760	0	0
GrantKnown_A	389577334	389465567	0	0
IdxKnown_A	389577334	389465567	0	0
IndexIsCorrect_A	389577334	864760	0	0
LockArbDecision_A	389577334	0	0	0
NoReadyValidNoGrant_A	389577334	325852194	0	0
ReadyAndValidImplyGrant_A	389577334	864760	0	0
ReqAndReadyImplyGrant_A	389577334	864760	0	0
ReqImpliesValid_A	389577334	11873706	0	0
ReqStaysHighUntilGranted0_M	389577334	0	0	0
RoundRobin_A	389577334	32856	0	876
ValidKnown_A	389577334	389465567	0	0
gen_data_port_assertion.DataFlow_A	389577334	864760	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	876	876	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	325852194	0	0
T1	431610	361177	0	0
T2	589046	490333	0	0
T3	2508	1	0	0
T4	2736	1	0	0
T5	25690	21452	0	0
T6	37183	1	0	0
T7	2221	1	0	0
T8	129927	108101	0	0
T9	3070	1	0	0
T10	267364	222594	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	11873706	0	0
T1	431610	35563	0	0
T2	589046	3969	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	1560	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	2458	0	0
T9	3070	57	0	0
T10	267364	170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	32856	0	876
T1	431610	5	0	1
T2	589046	0	0	1
T3	2508	0	0	1
T4	2736	4	0	1
T5	25690	0	0	1
T6	37183	21	0	1
T7	2221	0	0	1
T8	129927	0	0	1
T9	3070	0	0	1
T10	267364	0	0	1
T11	0	2	0	0
T12	0	78	0	0
T13	0	2	0	0
T14	0	546	0	0
T15	0	8	0	0
T16	0	2	0	0
T17	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	389465567	0	0
T1	431610	431517	0	0
T2	589046	589042	0	0
T3	2508	2480	0	0
T4	2736	2695	0	0
T5	25690	25645	0	0
T6	37183	35783	0	0
T7	2221	2169	0	0
T8	129927	129924	0	0
T9	3070	3018	0	0
T10	267364	267326	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389577334	864760	0	0
T1	431610	4327	0	0
T2	589046	925	0	0
T3	2508	42	0	0
T4	2736	190	0	0
T5	25690	202	0	0
T6	37183	1688	0	0
T7	2221	34	0	0
T8	129927	546	0	0
T9	3070	57	0	0
T10	267364	40	0	0