9601d3bbdd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | xbar_smoke | xbar_smoke | 4.060s | 176.364us | 50 | 50 | 100.00 |
| V1 | TOTAL | 50 | 50 | 100.00 | |||
| V2 | xbar_base_random_sequence | xbar_random | 37.530s | 1.342ms | 49 | 50 | 98.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 2.620s | 41.406us | 50 | 50 | 100.00 |
| xbar_smoke_large_delays | 51.820s | 47.711ms | 47 | 50 | 94.00 | ||
| xbar_smoke_slow_rsp | 1.047m | 34.357ms | 49 | 50 | 98.00 | ||
| xbar_random_zero_delays | 24.920s | 336.648us | 50 | 50 | 100.00 | ||
| xbar_random_large_delays | 5.502m | 231.741ms | 50 | 50 | 100.00 | ||
| xbar_random_slow_rsp | 5.820m | 129.200ms | 50 | 50 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 32.120s | 2.143ms | 50 | 50 | 100.00 |
| xbar_error_and_unmapped_addr | 34.030s | 4.105ms | 44 | 50 | 88.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 30.610s | 967.659us | 47 | 50 | 94.00 |
| xbar_error_and_unmapped_addr | 34.030s | 4.105ms | 44 | 50 | 88.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 1.051m | 8.244ms | 50 | 50 | 100.00 |
| xbar_access_same_device_slow_rsp | 12.942m | 207.431ms | 47 | 50 | 94.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 35.560s | 2.047ms | 49 | 50 | 98.00 |
| V2 | xbar_stress_all | xbar_stress_all | 5.938m | 12.379ms | 47 | 50 | 94.00 |
| xbar_stress_all_with_error | 5.780m | 67.044ms | 50 | 50 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 11.146m | 4.271ms | 48 | 50 | 96.00 |
| xbar_stress_all_with_reset_error | 7.786m | 14.404ms | 49 | 50 | 98.00 | ||
| V2 | TOTAL | 826 | 850 | 97.18 | |||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 876 | 900 | 97.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 1 | 1 | 1 | 100.00 |
| V2 | 17 | 17 | 7 | 41.18 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.74 | 98.53 | 90.16 | 98.80 | -- | 93.72 | 99.26 | 100.00 |
Offending '(num_req_outstanding <= MaxOutstanding)' has 20 failures:
Test xbar_stress_all has 3 failures.
0.xbar_stress_all.84321417715106700719562224365095616824951480569822365949813002108509405580869
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/0.xbar_stress_all/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 7463 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 53458212 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 190 requests
UVM_INFO @ 65471489 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 192 requests
UVM_INFO @ 67407460 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 111 requests
6.xbar_stress_all.52558455173098352522723568734501709260121698415656459601829068581086850590069
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 7495 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 5533855 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_same_source_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 6 requests
UVM_INFO @ 10047049 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_same_source_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 12 requests
UVM_INFO @ 20928715 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_same_source_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 13 requests
... and 1 more failures.
Test xbar_stress_all_with_rand_reset has 1 failures.
6.xbar_stress_all_with_rand_reset.14605984659368883472687708005215294450804828672978758360924051542201514947224
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 6602 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 1476405 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 104 requests
UVM_INFO @ 1476405 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 104 requests
UVM_INFO @ 1476405 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 172 requests
Test xbar_error_and_unmapped_addr has 5 failures.
8.xbar_error_and_unmapped_addr.15445192159650890970615635472712449513831062922288547308093844598228434707347
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 5552 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 3903480 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 135 requests
UVM_INFO @ 4883064 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 112 requests
UVM_INFO @ 5230000 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 114 requests
9.xbar_error_and_unmapped_addr.19675365828407381000021947750648320666476680616318909961836416210666196995262
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 8857 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 25242193 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 132 requests
UVM_INFO @ 27965521 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 114 requests
UVM_INFO @ 30433537 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_unmapped_addr_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 130 requests
... and 3 more failures.
Test xbar_smoke_large_delays has 2 failures.
12.xbar_smoke_large_delays.29839272886079320959133317269187010310032253981401835330658161310520755186248
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 8341 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 1803522769 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 162 requests
UVM_INFO @ 3948493417 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 196 requests
UVM_INFO @ 5709856345 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 166 requests
33.xbar_smoke_large_delays.56608942655198272644792065642297603480548107498023642583941355307267888156846
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/33.xbar_smoke_large_delays/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 8288 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 2072968560 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 125 requests
UVM_INFO @ 4975440224 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 151 requests
UVM_INFO @ 7396381328 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_smoke_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 191 requests
Test xbar_error_random has 3 failures.
12.xbar_error_random.99760843290530247234406165630613647803417943552053811525713747816497563258448
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/12.xbar_error_random/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 6306 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 4893966 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 140 requests
UVM_INFO @ 7332178 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 130 requests
UVM_INFO @ 8837802 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 148 requests
16.xbar_error_random.2993243420972943421522892029999938389627465132489611441322432005062054188566
Line 249, in log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/16.xbar_error_random/latest/run.log
Offending '(num_req_outstanding <= MaxOutstanding)'
UVM_ERROR @ 6357 ps: (tlul_socket_1n.sv:121) [ASSERT FAILED] NotOverflowed_A
UVM_INFO @ 38215737 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__corei_agent.sequencer.rv_core_ibex__corei_seq finished sending 152 requests
UVM_INFO @ 52131109 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_core_ibex__cored_agent.sequencer.rv_core_ibex__cored_seq finished sending 121 requests
UVM_INFO @ 63667605 ps: (xbar_base_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.xbar_random_vseq] uvm_test_top.env.rv_dm__sba_agent.sequencer.rv_dm__sba_seq finished sending 150 requests
... and 1 more failures.
... and 4 more tests.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
Test xbar_stress_all_with_rand_reset has 1 failures.
13.xbar_stress_all_with_rand_reset.87869510722793930634227490522692835680734944085554923395255667837593427104439
Log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/13.xbar_stress_all_with_rand_reset/latest && /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294352055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.3294352055
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:37 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test xbar_error_and_unmapped_addr has 1 failures.
22.xbar_error_and_unmapped_addr.104785314220319324121576984069978249012805768871971096643833606670393737271487
Log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/22.xbar_error_and_unmapped_addr/latest/run.log
[make]: simulate
cd /workspace/22.xbar_error_and_unmapped_addr/latest && /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850974911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.850974911
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:37 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test xbar_smoke_large_delays has 1 failures.
29.xbar_smoke_large_delays.11427697859740679168816689658269559724414046851226675065368187857061545959664
Log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/29.xbar_smoke_large_delays/latest/run.log
[make]: simulate
cd /workspace/29.xbar_smoke_large_delays/latest && /workspace/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344883952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3344883952
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:37 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test xbar_random has 1 failures.
41.xbar_random.59343269159364457503830486076214175732419961194529404887016926457681865609989
Log /container/opentitan-public/scratch/os_regression/xbar_main-sim-vcs/41.xbar_random/latest/run.log
[make]: simulate
cd /workspace/41.xbar_random/latest && /workspace/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833098501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.833098501
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Dec 20 12:37 2023
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255