XBAR_MAIN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	xbar_smoke	xbar_smoke	35.184s		49	50	98.00
V1		TOTAL			49	50	98.00
V2	xbar_base_random_sequence	xbar_random	50.470s	826.603us	50	50	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	3.770s	29.915us	50	50	100.00
		xbar_smoke_large_delays	1.210m	7.044ms	50	50	100.00
		xbar_smoke_slow_rsp	52.340s	6.288ms	50	50	100.00
		xbar_random_zero_delays	35.330s	293.615us	50	50	100.00
		xbar_random_large_delays	3.775m	153.052ms	50	50	100.00
		xbar_random_slow_rsp	3.513m	98.653ms	50	50	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	39.680s	766.504us	50	50	100.00
		xbar_error_and_unmapped_addr	31.280s	1.787ms	50	50	100.00
V2	xbar_error_cases	xbar_error_random	39.820s	1.899ms	50	50	100.00
		xbar_error_and_unmapped_addr	31.280s	1.787ms	50	50	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.272m	1.991ms	50	50	100.00
		xbar_access_same_device_slow_rsp	7.077m	95.087ms	50	50	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	38.160s	3.265ms	50	50	100.00
V2	xbar_stress_all	xbar_stress_all	5.144m	12.911ms	50	50	100.00
		xbar_stress_all_with_error	3.354m	9.043ms	50	50	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	10.075m	13.291ms	50	50	100.00
		xbar_stress_all_with_reset_error	7.309m	7.354ms	50	50	100.00
V2		TOTAL			850	850	100.00
V2S		TOTAL			0	0	--
V3		TOTAL			0	0	--
		TOTAL			899	900	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	1	1	0	0.00
V2	17	17	17	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	99.26	88.92	100.00	--	95.88	99.28	100.00

Failure Buckets

Job returned non-zero exit code has 1 failures:

Test xbar_smoke has 1 failures.

0.xbar_smoke.1138494648934179519408889397516996201187589671797060186258612938948629230769
Log /workspaces/repo/scratch/os_regression_2024_10_14/xbar_main-sim-vcs/0.xbar_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 14 20:56 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255