Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1568723 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 248996 1 T1 215 T2 3 T3 591


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 617554 1 T1 507 T2 20 T3 1463
values[0x0] 583245 1 T1 520 T2 4 T3 1356
values[0x1] 616920 1 T1 523 T2 26 T3 1434


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1212310 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605409 1 T1 508 T2 21 T3 1446


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28715 1 T1 31 T2 1 T3 57
valid_sources[0x01] 29248 1 T1 40 T2 1 T3 46
valid_sources[0x02] 27591 1 T1 22 T3 60 T4 15
valid_sources[0x03] 27362 1 T1 43 T3 62 T4 37
valid_sources[0x04] 27697 1 T1 25 T2 2 T3 57
valid_sources[0x05] 28919 1 T1 31 T3 110 T4 18
valid_sources[0x06] 28298 1 T1 39 T3 61 T4 39
valid_sources[0x07] 28633 1 T1 36 T3 72 T4 58
valid_sources[0x08] 27898 1 T1 6 T3 82 T4 82
valid_sources[0x09] 27630 1 T3 63 T4 64 T5 1
valid_sources[0x0a] 27601 1 T1 19 T3 69 T4 30
valid_sources[0x0b] 29832 1 T1 13 T2 2 T3 86
valid_sources[0x0c] 28554 1 T1 9 T2 2 T3 48
valid_sources[0x0d] 28710 1 T1 45 T3 46 T4 18
valid_sources[0x0e] 29265 1 T1 8 T3 81 T4 66
valid_sources[0x0f] 28745 1 T2 2 T3 74 T4 81
valid_sources[0x10] 28048 1 T1 73 T3 77 T4 34
valid_sources[0x11] 29530 1 T3 97 T4 35 T5 1
valid_sources[0x12] 27937 1 T3 86 T4 84 T5 1
valid_sources[0x13] 28277 1 T2 2 T3 36 T4 50
valid_sources[0x14] 29122 1 T3 30 T4 32 T5 3
valid_sources[0x15] 27657 1 T1 33 T2 1 T3 69
valid_sources[0x16] 27013 1 T1 34 T2 1 T3 40
valid_sources[0x17] 29039 1 T1 59 T3 87 T4 70
valid_sources[0x18] 28087 1 T1 54 T2 1 T3 69
valid_sources[0x19] 27979 1 T1 18 T2 1 T3 72
valid_sources[0x1a] 28955 1 T1 74 T2 1 T3 62
valid_sources[0x1b] 27348 1 T1 35 T3 24 T4 50
valid_sources[0x1c] 29367 1 T1 17 T3 86 T4 48
valid_sources[0x1d] 28039 1 T1 42 T3 78 T4 65
valid_sources[0x1e] 30120 1 T1 5 T3 40 T4 38
valid_sources[0x1f] 27752 1 T1 18 T2 1 T3 53
valid_sources[0x20] 27770 1 T1 41 T2 1 T3 36


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26271 1 T1 19 T3 57 T4 34
values[0x0] all_enables biggest_size 196616 1 T1 172 T2 1 T3 472
values[0x1] all_enables biggest_size 26109 1 T1 24 T2 2 T3 62


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1589200 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 258147 1 T1 223 T2 6 T3 651


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 632236 1 T1 507 T2 17 T3 1564
values[0x0] 581615 1 T1 461 T2 2 T3 1482
values[0x1] 633496 1 T1 528 T2 26 T3 1505


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1218964 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 628383 1 T1 546 T2 16 T3 1567


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29204 1 T1 25 T2 1 T3 56
valid_sources[0x01] 28868 1 T1 48 T3 54 T4 34
valid_sources[0x02] 28041 1 T1 22 T2 2 T3 70
valid_sources[0x03] 28935 1 T1 53 T2 1 T3 94
valid_sources[0x04] 29164 1 T1 31 T2 1 T3 44
valid_sources[0x05] 29009 1 T1 27 T2 2 T3 63
valid_sources[0x06] 29036 1 T1 31 T3 60 T4 35
valid_sources[0x07] 28875 1 T1 17 T3 63 T4 28
valid_sources[0x08] 29002 1 T1 17 T3 102 T4 30
valid_sources[0x09] 28672 1 T3 37 T4 39 T5 3
valid_sources[0x0a] 28870 1 T1 48 T2 3 T3 68
valid_sources[0x0b] 30163 1 T1 10 T3 123 T4 41
valid_sources[0x0c] 29028 1 T1 15 T3 31 T4 31
valid_sources[0x0d] 29369 1 T1 37 T3 121 T4 42
valid_sources[0x0e] 29277 1 T1 13 T3 103 T4 45
valid_sources[0x0f] 29031 1 T2 1 T3 90 T4 28
valid_sources[0x10] 28782 1 T1 32 T3 69 T4 42
valid_sources[0x11] 29452 1 T3 93 T4 35 T6 538
valid_sources[0x12] 28236 1 T3 92 T4 45 T5 7
valid_sources[0x13] 29303 1 T2 1 T3 35 T4 52
valid_sources[0x14] 28923 1 T2 1 T3 36 T4 26
valid_sources[0x15] 28887 1 T1 48 T2 1 T3 78
valid_sources[0x16] 28093 1 T1 20 T2 1 T3 51
valid_sources[0x17] 28958 1 T1 58 T3 57 T4 38
valid_sources[0x18] 29034 1 T1 48 T2 1 T3 52
valid_sources[0x19] 28971 1 T1 9 T3 92 T4 23
valid_sources[0x1a] 29175 1 T1 67 T3 73 T4 28
valid_sources[0x1b] 28635 1 T1 15 T2 1 T3 46
valid_sources[0x1c] 28871 1 T1 13 T2 1 T3 89
valid_sources[0x1d] 28876 1 T1 38 T3 77 T4 43
valid_sources[0x1e] 28364 1 T1 20 T2 1 T3 54
valid_sources[0x1f] 29872 1 T1 25 T3 70 T4 31
valid_sources[0x20] 29310 1 T1 30 T3 30 T4 33


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26978 1 T1 28 T2 1 T3 63
values[0x0] all_enables biggest_size 203909 1 T1 171 T3 517 T4 235
values[0x1] all_enables biggest_size 27260 1 T1 24 T2 5 T3 71


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1579481 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251398 1 T1 185 T2 4 T3 577


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 621990 1 T1 465 T2 15 T3 1491
values[0x0] 587599 1 T1 477 T2 8 T3 1377
values[0x1] 621290 1 T1 459 T2 23 T3 1429


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1220079 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 610800 1 T1 450 T2 17 T3 1391


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29663 1 T1 17 T3 53 T4 42
valid_sources[0x01] 28153 1 T1 42 T2 1 T3 82
valid_sources[0x02] 28276 1 T1 15 T3 42 T4 29
valid_sources[0x03] 28152 1 T1 45 T3 92 T4 32
valid_sources[0x04] 28616 1 T1 18 T3 69 T4 23
valid_sources[0x05] 28075 1 T1 33 T2 1 T3 80
valid_sources[0x06] 29994 1 T1 29 T2 1 T3 77
valid_sources[0x07] 28082 1 T1 22 T2 2 T3 74
valid_sources[0x08] 28556 1 T1 18 T3 62 T4 42
valid_sources[0x09] 29130 1 T2 1 T3 66 T4 36
valid_sources[0x0a] 28451 1 T1 34 T2 1 T3 83
valid_sources[0x0b] 29288 1 T1 16 T2 1 T3 113
valid_sources[0x0c] 28041 1 T1 15 T3 53 T4 43
valid_sources[0x0d] 28810 1 T1 33 T3 59 T4 43
valid_sources[0x0e] 29063 1 T1 14 T3 99 T4 43
valid_sources[0x0f] 29297 1 T3 82 T4 44 T6 390
valid_sources[0x10] 28411 1 T1 38 T3 69 T4 46
valid_sources[0x11] 29749 1 T3 94 T4 33 T6 627
valid_sources[0x12] 28408 1 T2 2 T3 81 T4 40
valid_sources[0x13] 28006 1 T3 49 T4 23 T6 415
valid_sources[0x14] 28185 1 T2 1 T3 48 T4 35
valid_sources[0x15] 28166 1 T1 33 T2 1 T3 53
valid_sources[0x16] 29532 1 T1 25 T2 2 T3 52
valid_sources[0x17] 29498 1 T1 48 T3 42 T4 21
valid_sources[0x18] 28763 1 T1 43 T2 1 T3 67
valid_sources[0x19] 27578 1 T1 9 T3 67 T4 28
valid_sources[0x1a] 28777 1 T1 62 T3 60 T4 60
valid_sources[0x1b] 27675 1 T1 23 T2 1 T3 41
valid_sources[0x1c] 28682 1 T1 9 T3 100 T4 35
valid_sources[0x1d] 29717 1 T1 31 T3 99 T4 27
valid_sources[0x1e] 28659 1 T1 19 T2 2 T3 42
valid_sources[0x1f] 29813 1 T1 21 T3 63 T4 65
valid_sources[0x20] 28516 1 T1 19 T2 2 T3 40


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26875 1 T1 18 T3 61 T4 44
values[0x0] all_enables biggest_size 198105 1 T1 139 T2 2 T3 467
values[0x1] all_enables biggest_size 26418 1 T1 28 T2 2 T3 49

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%