Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	20928	20928	0	0
GntImpliesReady_A	2147483647	8167236	0	0
GntImpliesValid_A	2147483647	8167236	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8167236	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	444214891	0	0
ReadyAndValidImplyGrant_A	2147483647	8167236	0	0
ReqAndReadyImplyGrant_A	2147483647	8167236	0	0
ReqImpliesValid_A	2147483647	36066168	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	53640	0	20928
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8167236	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1845336	1844856	0	0
T2	868032	866688	0	0
T3	3078048	3076800	0	0
T4	5740824	5740704	0	0
T5	5470128	5469648	0	0
T6	5225880	5195184	0	0
T7	8795616	8792304	0	0
T8	101712	100440	0	0
T9	2815440	2813904	0	0
T10	1399344	1379136	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20928	20928	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1845336	1844856	0	0
T2	868032	866688	0	0
T3	3078048	3076800	0	0
T4	5740824	5740704	0	0
T5	5470128	5469648	0	0
T6	5225880	5195184	0	0
T7	8795616	8792304	0	0
T8	101712	100440	0	0
T9	2815440	2813904	0	0
T10	1399344	1379136	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1845336	1844856	0	0
T2	868032	866688	0	0
T3	3078048	3076800	0	0
T4	5740824	5740704	0	0
T5	5470128	5469648	0	0
T6	5225880	5195184	0	0
T7	8795616	8792304	0	0
T8	101712	100440	0	0
T9	2815440	2813904	0	0
T10	1399344	1379136	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	444214891	0	0
T1	1845336	97290	0	0
T2	868032	54431	0	0
T3	3078048	160372	0	0
T4	5740824	230244	0	0
T5	5470128	191361	0	0
T6	5225880	84072	0	0
T7	8795616	501371	0	0
T8	101712	2764	0	0
T9	2815440	159653	0	0
T10	1399344	91662	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36066168	0	0
T1	1845336	7838	0	0
T2	868032	7579	0	0
T3	3078048	63124	0	0
T4	5740824	12113	0	0
T5	5470128	646	0	0
T6	5225880	176245	0	0
T7	8795616	115612	0	0
T8	101712	2669	0	0
T9	2815440	10095	0	0
T10	1399344	16763	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	53640	0	20928
T3	128252	6	0	1
T4	239201	0	0	1
T5	227922	0	0	1
T6	435490	3326	0	2
T7	732968	26	0	2
T8	8476	6	0	2
T9	234620	2	0	2
T10	116612	0	0	2
T11	729544	0	0	2
T12	61852	2	0	1
T13	37625	545	0	1
T14	0	35	0	0
T15	0	1	0	0
T16	0	3097	0	0
T17	0	15	0	0
T18	0	3	0	0
T19	4500	0	0	2
T20	331168	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1845336	1844856	0	0
T2	868032	866688	0	0
T3	3078048	3076800	0	0
T4	5740824	5740704	0	0
T5	5470128	5469648	0	0
T6	5225880	5195184	0	0
T7	8795616	8792304	0	0
T8	101712	100440	0	0
T9	2815440	2813904	0	0
T10	1399344	1379136	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8167236	0	0
T1	1845336	4426	0	0
T2	868032	3386	0	0
T3	3078048	13077	0	0
T4	5740824	7085	0	0
T5	5470128	411	0	0
T6	5225880	99387	0	0
T7	8795616	33325	0	0
T8	101712	2287	0	0
T9	2815440	5222	0	0
T10	1399344	4270	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	917001	0	0
GntImpliesValid_A	396104503	917001	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	917001	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	12890509	0	0
ReadyAndValidImplyGrant_A	396104503	917001	0	0
ReqAndReadyImplyGrant_A	396104503	917001	0	0
ReqImpliesValid_A	396104503	2579946	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	917001	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	12890509	0	0
T1	76889	3805	0	0
T2	36168	2626	0	0
T3	128252	8351	0	0
T4	239201	3188	0	0
T5	227922	181	0	0
T6	217745	6834	0	0
T7	366484	24303	0	0
T8	4238	178	0	0
T9	117310	4484	0	0
T10	58306	4286	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	2579946	0	0
T1	76889	535	0	0
T2	36168	570	0	0
T3	128252	1586	0	0
T4	239201	1115	0	0
T5	227922	68	0	0
T6	217745	17551	0	0
T7	366484	6847	0	0
T8	4238	283	0	0
T9	117310	697	0	0
T10	58306	2066	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917001	0	0
T1	76889	498	0	0
T2	36168	374	0	0
T3	128252	1128	0	0
T4	239201	764	0	0
T5	227922	48	0	0
T6	217745	12185	0	0
T7	366484	3760	0	0
T8	4238	230	0	0
T9	117310	612	0	0
T10	58306	657	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	907296	0	0
GntImpliesValid_A	396104503	907296	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	907296	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	12856169	0	0
ReadyAndValidImplyGrant_A	396104503	907296	0	0
ReqAndReadyImplyGrant_A	396104503	907296	0	0
ReqImpliesValid_A	396104503	2598016	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	907296	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	12856169	0	0
T1	76889	3661	0	0
T2	36168	2482	0	0
T3	128252	9227	0	0
T4	239201	3358	0	0
T5	227922	248	0	0
T6	217745	7296	0	0
T7	366484	26353	0	0
T8	4238	189	0	0
T9	117310	4276	0	0
T10	58306	3456	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	2598016	0	0
T1	76889	515	0	0
T2	36168	563	0	0
T3	128252	1846	0	0
T4	239201	1218	0	0
T5	227922	79	0	0
T6	217745	16703	0	0
T7	366484	8769	0	0
T8	4238	366	0	0
T9	117310	607	0	0
T10	58306	981	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	907296	0	0
T1	76889	491	0	0
T2	36168	357	0	0
T3	128252	1249	0	0
T4	239201	826	0	0
T5	227922	57	0	0
T6	217745	11992	0	0
T7	366484	3832	0	0
T8	4238	277	0	0
T9	117310	545	0	0
T10	58306	494	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	229907	0	0
GntImpliesValid_A	396104503	229907	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	229907	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3244763	0	0
ReadyAndValidImplyGrant_A	396104503	229907	0	0
ReqAndReadyImplyGrant_A	396104503	229907	0	0
ReqImpliesValid_A	396104503	596121	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	229907	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3244763	0	0
T1	76889	970	0	0
T2	36168	716	0	0
T3	128252	931	0	0
T4	239201	741	0	0
T5	227922	40	0	0
T6	217745	1429	0	0
T7	366484	4411	0	0
T8	4238	64	0	0
T9	117310	1316	0	0
T10	58306	448	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	596121	0	0
T1	76889	128	0	0
T2	36168	119	0	0
T3	128252	122	0	0
T4	239201	216	0	0
T5	227922	8	0	0
T6	217745	2432	0	0
T7	366484	723	0	0
T8	4238	67	0	0
T9	117310	171	0	0
T10	58306	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	229907	0	0
T1	76889	126	0	0
T2	36168	99	0	0
T3	128252	113	0	0
T4	239201	183	0	0
T5	227922	8	0	0
T6	217745	1923	0	0
T7	366484	577	0	0
T8	4238	65	0	0
T9	117310	169	0	0
T10	58306	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	224243	0	0
GntImpliesValid_A	396104503	224243	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	224243	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3170698	0	0
ReadyAndValidImplyGrant_A	396104503	224243	0	0
ReqAndReadyImplyGrant_A	396104503	224243	0	0
ReqImpliesValid_A	396104503	626318	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	224243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3170698	0	0
T1	76889	841	0	0
T2	36168	661	0	0
T3	128252	882	0	0
T4	239201	793	0	0
T5	227922	45	0	0
T6	217745	1124	0	0
T7	366484	4484	0	0
T8	4238	61	0	0
T9	117310	1194	0	0
T10	58306	645	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	626318	0	0
T1	76889	133	0	0
T2	36168	104	0	0
T3	128252	118	0	0
T4	239201	212	0	0
T5	227922	13	0	0
T6	217745	4823	0	0
T7	366484	640	0	0
T8	4238	62	0	0
T9	117310	162	0	0
T10	58306	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224243	0	0
T1	76889	123	0	0
T2	36168	87	0	0
T3	128252	117	0	0
T4	239201	180	0	0
T5	227922	13	0	0
T6	217745	2966	0	0
T7	366484	592	0	0
T8	4238	61	0	0
T9	117310	162	0	0
T10	58306	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	231337	0	0
GntImpliesValid_A	396104503	231337	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	231337	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	5499962	0	0
ReadyAndValidImplyGrant_A	396104503	231337	0	0
ReqAndReadyImplyGrant_A	396104503	231337	0	0
ReqImpliesValid_A	396104503	1263087	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	231337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	5499962	0	0
T1	76889	814	0	0
T2	36168	1697	0	0
T3	128252	1741	0	0
T4	239201	1706	0	0
T5	227922	41	0	0
T6	217745	8343	0	0
T7	366484	10956	0	0
T8	4238	326	0	0
T9	117310	2215	0	0
T10	58306	1128	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	1263087	0	0
T1	76889	151	0	0
T2	36168	174	0	0
T3	128252	166	0	0
T4	239201	290	0	0
T5	227922	8	0	0
T6	217745	21858	0	0
T7	366484	1045	0	0
T8	4238	111	0	0
T9	117310	147	0	0
T10	58306	78	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231337	0	0
T1	76889	145	0	0
T2	36168	90	0	0
T3	128252	122	0	0
T4	239201	198	0	0
T5	227922	8	0	0
T6	217745	3118	0	0
T7	366484	554	0	0
T8	4238	69	0	0
T9	117310	142	0	0
T10	58306	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	231108	0	0
GntImpliesValid_A	396104503	231108	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	231108	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	5941305	0	0
ReadyAndValidImplyGrant_A	396104503	231108	0	0
ReqAndReadyImplyGrant_A	396104503	231108	0	0
ReqImpliesValid_A	396104503	1328831	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	231108	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	5941305	0	0
T1	76889	2598	0	0
T2	36168	1594	0	0
T3	128252	993	0	0
T4	239201	3524	0	0
T5	227922	75	0	0
T6	217745	10983	0	0
T7	366484	10575	0	0
T8	4238	318	0	0
T9	117310	11034	0	0
T10	58306	19326	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	1328831	0	0
T1	76889	144	0	0
T2	36168	271	0	0
T3	128252	116	0	0
T4	239201	522	0	0
T5	227922	19	0	0
T6	217745	9845	0	0
T7	366484	3243	0	0
T8	4238	123	0	0
T9	117310	616	0	0
T10	58306	6108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	231108	0	0
T1	76889	128	0	0
T2	36168	101	0	0
T3	128252	116	0	0
T4	239201	210	0	0
T5	227922	10	0	0
T6	217745	2317	0	0
T7	366484	1066	0	0
T8	4238	76	0	0
T9	117310	137	0	0
T10	58306	569	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	217830	0	0
GntImpliesValid_A	396104503	217830	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	217830	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	5784216	0	0
ReadyAndValidImplyGrant_A	396104503	217830	0	0
ReqAndReadyImplyGrant_A	396104503	217830	0	0
ReqImpliesValid_A	396104503	1158839	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	217830	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	5784216	0	0
T1	76889	1140	0	0
T2	36168	1035	0	0
T3	128252	4070	0	0
T4	239201	1675	0	0
T5	227922	57	0	0
T6	217745	6500	0	0
T7	366484	11155	0	0
T8	4238	456	0	0
T9	117310	10187	0	0
T10	58306	1232	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	1158839	0	0
T1	76889	135	0	0
T2	36168	168	0	0
T3	128252	3031	0	0
T4	239201	320	0	0
T5	227922	10	0	0
T6	217745	5412	0	0
T7	366484	1103	0	0
T8	4238	89	0	0
T9	117310	212	0	0
T10	58306	78	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	217830	0	0
T1	76889	109	0	0
T2	36168	102	0	0
T3	128252	615	0	0
T4	239201	206	0	0
T5	227922	10	0	0
T6	217745	1488	0	0
T7	366484	547	0	0
T8	4238	44	0	0
T9	117310	127	0	0
T10	58306	70	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	212178	0	0
GntImpliesValid_A	396104503	212178	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	212178	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	5585024	0	0
ReadyAndValidImplyGrant_A	396104503	212178	0	0
ReqAndReadyImplyGrant_A	396104503	212178	0	0
ReqImpliesValid_A	396104503	1211189	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	212178	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	5585024	0	0
T1	76889	870	0	0
T2	36168	987	0	0
T3	128252	1817	0	0
T4	239201	2432	0	0
T5	227922	30	0	0
T6	217745	19746	0	0
T7	366484	14857	0	0
T8	4238	319	0	0
T9	117310	3150	0	0
T10	58306	631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	1211189	0	0
T1	76889	129	0	0
T2	36168	133	0	0
T3	128252	2649	0	0
T4	239201	344	0	0
T5	227922	6	0	0
T6	217745	22762	0	0
T7	366484	3205	0	0
T8	4238	103	0	0
T9	117310	172	0	0
T10	58306	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	212178	0	0
T1	76889	124	0	0
T2	36168	100	0	0
T3	128252	556	0	0
T4	239201	210	0	0
T5	227922	6	0	0
T6	217745	3345	0	0
T7	366484	932	0	0
T8	4238	68	0	0
T9	117310	151	0	0
T10	58306	68	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	221333	0	0
GntImpliesValid_A	396104503	221333	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	221333	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3163726	0	0
ReadyAndValidImplyGrant_A	396104503	221333	0	0
ReqAndReadyImplyGrant_A	396104503	221333	0	0
ReqImpliesValid_A	396104503	574677	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	221333	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3163726	0	0
T1	76889	1002	0	0
T2	36168	715	0	0
T3	128252	2067	0	0
T4	239201	758	0	0
T5	227922	32	0	0
T6	217745	1115	0	0
T7	366484	4314	0	0
T8	4238	43	0	0
T9	117310	1342	0	0
T10	58306	527	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	574677	0	0
T1	76889	135	0	0
T2	36168	125	0	0
T3	128252	3870	0	0
T4	239201	275	0	0
T5	227922	7	0	0
T6	217745	3075	0	0
T7	366484	654	0	0
T8	4238	50	0	0
T9	117310	168	0	0
T10	58306	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	221333	0	0
T1	76889	135	0	0
T2	36168	93	0	0
T3	128252	556	0	0
T4	239201	202	0	0
T5	227922	7	0	0
T6	217745	2088	0	0
T7	366484	573	0	0
T8	4238	46	0	0
T9	117310	159	0	0
T10	58306	67	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	230016	0	0
GntImpliesValid_A	396104503	230016	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	230016	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3215186	0	0
ReadyAndValidImplyGrant_A	396104503	230016	0	0
ReqAndReadyImplyGrant_A	396104503	230016	0	0
ReqImpliesValid_A	396104503	581644	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	230016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3215186	0	0
T1	76889	1040	0	0
T2	36168	727	0	0
T3	128252	941	0	0
T4	239201	940	0	0
T5	227922	71	0	0
T6	217745	1625	0	0
T7	366484	5239	0	0
T8	4238	54	0	0
T9	117310	1098	0	0
T10	58306	465	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	581644	0	0
T1	76889	139	0	0
T2	36168	95	0	0
T3	128252	145	0	0
T4	239201	248	0	0
T5	227922	19	0	0
T6	217745	2316	0	0
T7	366484	4815	0	0
T8	4238	59	0	0
T9	117310	170	0	0
T10	58306	69	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	230016	0	0
T1	76889	139	0	0
T2	36168	93	0	0
T3	128252	112	0	0
T4	239201	211	0	0
T5	227922	17	0	0
T6	217745	1963	0	0
T7	366484	1011	0	0
T8	4238	56	0	0
T9	117310	146	0	0
T10	58306	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	224970	0	0
GntImpliesValid_A	396104503	224970	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	224970	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3175357	0	0
ReadyAndValidImplyGrant_A	396104503	224970	0	0
ReqAndReadyImplyGrant_A	396104503	224970	0	0
ReqImpliesValid_A	396104503	584444	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	224970	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3175357	0	0
T1	76889	910	0	0
T2	36168	778	0	0
T3	128252	4758	0	0
T4	239201	844	0	0
T5	227922	34	0	0
T6	217745	2027	0	0
T7	366484	4152	0	0
T8	4238	60	0	0
T9	117310	1081	0	0
T10	58306	441	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	584444	0	0
T1	76889	116	0	0
T2	36168	119	0	0
T3	128252	11577	0	0
T4	239201	258	0	0
T5	227922	12	0	0
T6	217745	4312	0	0
T7	366484	688	0	0
T8	4238	69	0	0
T9	117310	154	0	0
T10	58306	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224970	0	0
T1	76889	116	0	0
T2	36168	98	0	0
T3	128252	1524	0	0
T4	239201	210	0	0
T5	227922	12	0	0
T6	217745	3162	0	0
T7	366484	542	0	0
T8	4238	64	0	0
T9	117310	149	0	0
T10	58306	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	225653	0	0
GntImpliesValid_A	396104503	225653	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	225653	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3266111	0	0
ReadyAndValidImplyGrant_A	396104503	225653	0	0
ReqAndReadyImplyGrant_A	396104503	225653	0	0
ReqImpliesValid_A	396104503	617809	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	225653	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3266111	0	0
T1	76889	1004	0	0
T2	36168	603	0	0
T3	128252	621	0	0
T4	239201	713	0	0
T5	227922	60	0	0
T6	217745	1820	0	0
T7	366484	3934	0	0
T8	4238	49	0	0
T9	117310	1154	0	0
T10	58306	609	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	617809	0	0
T1	76889	147	0	0
T2	36168	100	0	0
T3	128252	104	0	0
T4	239201	193	0	0
T5	227922	20	0	0
T6	217745	6267	0	0
T7	366484	632	0	0
T8	4238	60	0	0
T9	117310	160	0	0
T10	58306	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	225653	0	0
T1	76889	142	0	0
T2	36168	85	0	0
T3	128252	94	0	0
T4	239201	176	0	0
T5	227922	15	0	0
T6	217745	4036	0	0
T7	366484	534	0	0
T8	4238	54	0	0
T9	117310	157	0	0
T10	58306	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	238478	0	0
GntImpliesValid_A	396104503	238478	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	238478	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3162597	0	0
ReadyAndValidImplyGrant_A	396104503	238478	0	0
ReqAndReadyImplyGrant_A	396104503	238478	0	0
ReqImpliesValid_A	396104503	681990	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	238478	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3162597	0	0
T1	76889	935	0	0
T2	36168	670	0	0
T3	128252	1646	0	0
T4	239201	745	0	0
T5	227922	24	0	0
T6	217745	2125	0	0
T7	366484	4446	0	0
T8	4238	62	0	0
T9	117310	1101	0	0
T10	58306	541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	681990	0	0
T1	76889	129	0	0
T2	36168	115	0	0
T3	128252	6032	0	0
T4	239201	211	0	0
T5	227922	6	0	0
T6	217745	5620	0	0
T7	366484	748	0	0
T8	4238	65	0	0
T9	117310	165	0	0
T10	58306	71	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	238478	0	0
T1	76889	123	0	0
T2	36168	92	0	0
T3	128252	689	0	0
T4	239201	188	0	0
T5	227922	6	0	0
T6	217745	3865	0	0
T7	366484	573	0	0
T8	4238	63	0	0
T9	117310	150	0	0
T10	58306	71	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	224715	0	0
GntImpliesValid_A	396104503	224715	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	224715	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3164222	0	0
ReadyAndValidImplyGrant_A	396104503	224715	0	0
ReqAndReadyImplyGrant_A	396104503	224715	0	0
ReqImpliesValid_A	396104503	603397	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	224715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3164222	0	0
T1	76889	795	0	0
T2	36168	695	0	0
T3	128252	1046	0	0
T4	239201	683	0	0
T5	227922	22	0	0
T6	217745	1020	0	0
T7	366484	4179	0	0
T8	4238	67	0	0
T9	117310	879	0	0
T10	58306	357	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	603397	0	0
T1	76889	118	0	0
T2	36168	111	0	0
T3	128252	139	0	0
T4	239201	184	0	0
T5	227922	6	0	0
T6	217745	3099	0	0
T7	366484	651	0	0
T8	4238	80	0	0
T9	117310	131	0	0
T10	58306	58	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224715	0	0
T1	76889	114	0	0
T2	36168	96	0	0
T3	128252	138	0	0
T4	239201	170	0	0
T5	227922	6	0	0
T6	217745	2052	0	0
T7	366484	543	0	0
T8	4238	73	0	0
T9	117310	125	0	0
T10	58306	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	223860	0	0
GntImpliesValid_A	396104503	223860	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	223860	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3157551	0	0
ReadyAndValidImplyGrant_A	396104503	223860	0	0
ReqAndReadyImplyGrant_A	396104503	223860	0	0
ReqImpliesValid_A	396104503	572722	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	223860	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3157551	0	0
T1	76889	887	0	0
T2	36168	731	0	0
T3	128252	2810	0	0
T4	239201	788	0	0
T5	227922	60	0	0
T6	217745	1693	0	0
T7	366484	5175	0	0
T8	4238	68	0	0
T9	117310	1298	0	0
T10	58306	1033	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	572722	0	0
T1	76889	126	0	0
T2	36168	146	0	0
T3	128252	3961	0	0
T4	239201	236	0	0
T5	227922	15	0	0
T6	217745	4032	0	0
T7	366484	2803	0	0
T8	4238	75	0	0
T9	117310	158	0	0
T10	58306	606	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223860	0	0
T1	76889	126	0	0
T2	36168	101	0	0
T3	128252	1009	0	0
T4	239201	189	0	0
T5	227922	15	0	0
T6	217745	2855	0	0
T7	366484	1032	0	0
T8	4238	71	0	0
T9	117310	149	0	0
T10	58306	168	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	228788	0	0
GntImpliesValid_A	396104503	228788	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	228788	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3158698	0	0
ReadyAndValidImplyGrant_A	396104503	228788	0	0
ReqAndReadyImplyGrant_A	396104503	228788	0	0
ReqImpliesValid_A	396104503	583071	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	228788	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3158698	0	0
T1	76889	888	0	0
T2	36168	592	0	0
T3	128252	943	0	0
T4	239201	902	0	0
T5	227922	60	0	0
T6	217745	1212	0	0
T7	366484	9445	0	0
T8	4238	59	0	0
T9	117310	1197	0	0
T10	58306	472	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	583071	0	0
T1	76889	114	0	0
T2	36168	152	0	0
T3	128252	132	0	0
T4	239201	263	0	0
T5	227922	17	0	0
T6	217745	2639	0	0
T7	366484	2444	0	0
T8	4238	66	0	0
T9	117310	187	0	0
T10	58306	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	228788	0	0
T1	76889	114	0	0
T2	36168	95	0	0
T3	128252	126	0	0
T4	239201	213	0	0
T5	227922	13	0	0
T6	217745	1918	0	0
T7	366484	1447	0	0
T8	4238	62	0	0
T9	117310	164	0	0
T10	58306	65	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	244836	0	0
GntImpliesValid_A	396104503	244836	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	244836	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3360897	0	0
ReadyAndValidImplyGrant_A	396104503	244836	0	0
ReqAndReadyImplyGrant_A	396104503	244836	0	0
ReqImpliesValid_A	396104503	667824	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	244836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3360897	0	0
T1	76889	896	0	0
T2	36168	658	0	0
T3	128252	1272	0	0
T4	239201	915	0	0
T5	227922	17	0	0
T6	217745	2141	0	0
T7	366484	8585	0	0
T8	4238	62	0	0
T9	117310	973	0	0
T10	58306	522	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	667824	0	0
T1	76889	144	0	0
T2	36168	137	0	0
T3	128252	6018	0	0
T4	239201	248	0	0
T5	227922	3	0	0
T6	217745	4288	0	0
T7	366484	7324	0	0
T8	4238	75	0	0
T9	117310	140	0	0
T10	58306	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	244836	0	0
T1	76889	124	0	0
T2	36168	96	0	0
T3	128252	657	0	0
T4	239201	206	0	0
T5	227922	3	0	0
T6	217745	3207	0	0
T7	366484	1591	0	0
T8	4238	68	0	0
T9	117310	130	0	0
T10	58306	72	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	220193	0	0
GntImpliesValid_A	396104503	220193	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	220193	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3127861	0	0
ReadyAndValidImplyGrant_A	396104503	220193	0	0
ReqAndReadyImplyGrant_A	396104503	220193	0	0
ReqImpliesValid_A	396104503	537110	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	220193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3127861	0	0
T1	76889	953	0	0
T2	36168	665	0	0
T3	128252	1055	0	0
T4	239201	672	0	0
T5	227922	43	0	0
T6	217745	958	0	0
T7	366484	4083	0	0
T8	4238	63	0	0
T9	117310	971	0	0
T10	58306	394	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	537110	0	0
T1	76889	135	0	0
T2	36168	132	0	0
T3	128252	149	0	0
T4	239201	200	0	0
T5	227922	15	0	0
T6	217745	1955	0	0
T7	366484	676	0	0
T8	4238	64	0	0
T9	117310	129	0	0
T10	58306	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	220193	0	0
T1	76889	129	0	0
T2	36168	90	0	0
T3	128252	123	0	0
T4	239201	175	0	0
T5	227922	12	0	0
T6	217745	1449	0	0
T7	366484	548	0	0
T8	4238	63	0	0
T9	117310	129	0	0
T10	58306	57	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	224250	0	0
GntImpliesValid_A	396104503	224250	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	224250	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3202393	0	0
ReadyAndValidImplyGrant_A	396104503	224250	0	0
ReqAndReadyImplyGrant_A	396104503	224250	0	0
ReqImpliesValid_A	396104503	587583	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	224250	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3202393	0	0
T1	76889	745	0	0
T2	36168	732	0	0
T3	128252	868	0	0
T4	239201	772	0	0
T5	227922	43	0	0
T6	217745	1791	0	0
T7	366484	4107	0	0
T8	4238	68	0	0
T9	117310	1300	0	0
T10	58306	487	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	587583	0	0
T1	76889	125	0	0
T2	36168	139	0	0
T3	128252	128	0	0
T4	239201	234	0	0
T5	227922	12	0	0
T6	217745	4502	0	0
T7	366484	653	0	0
T8	4238	83	0	0
T9	117310	179	0	0
T10	58306	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	224250	0	0
T1	76889	110	0	0
T2	36168	101	0	0
T3	128252	122	0	0
T4	239201	189	0	0
T5	227922	12	0	0
T6	217745	3139	0	0
T7	366484	552	0	0
T8	4238	75	0	0
T9	117310	170	0	0
T10	58306	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	223474	0	0
GntImpliesValid_A	396104503	223474	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	223474	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3239570	0	0
ReadyAndValidImplyGrant_A	396104503	223474	0	0
ReqAndReadyImplyGrant_A	396104503	223474	0	0
ReqImpliesValid_A	396104503	559820	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	223474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3239570	0	0
T1	76889	1027	0	0
T2	36168	840	0	0
T3	128252	877	0	0
T4	239201	865	0	0
T5	227922	17	0	0
T6	217745	1583	0	0
T7	366484	9698	0	0
T8	4238	66	0	0
T9	117310	1075	0	0
T10	58306	1427	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	559820	0	0
T1	76889	133	0	0
T2	36168	172	0	0
T3	128252	141	0	0
T4	239201	218	0	0
T5	227922	4	0	0
T6	217745	4552	0	0
T7	366484	5889	0	0
T8	4238	73	0	0
T9	117310	140	0	0
T10	58306	1775	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	223474	0	0
T1	76889	125	0	0
T2	36168	109	0	0
T3	128252	116	0	0
T4	239201	206	0	0
T5	227922	4	0	0
T6	217745	3060	0	0
T7	366484	1563	0	0
T8	4238	69	0	0
T9	117310	140	0	0
T10	58306	460	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	227704	0	0
GntImpliesValid_A	396104503	227704	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	227704	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3266704	0	0
ReadyAndValidImplyGrant_A	396104503	227704	0	0
ReqAndReadyImplyGrant_A	396104503	227704	0	0
ReqImpliesValid_A	396104503	595915	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	227704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3266704	0	0
T1	76889	757	0	0
T2	36168	682	0	0
T3	128252	885	0	0
T4	239201	867	0	0
T5	227922	30	0	0
T6	217745	1528	0	0
T7	366484	4353	0	0
T8	4238	70	0	0
T9	117310	1138	0	0
T10	58306	605	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	595915	0	0
T1	76889	95	0	0
T2	36168	157	0	0
T3	128252	114	0	0
T4	239201	272	0	0
T5	227922	8	0	0
T6	217745	2307	0	0
T7	366484	5078	0	0
T8	4238	77	0	0
T9	117310	147	0	0
T10	58306	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	227704	0	0
T1	76889	95	0	0
T2	36168	93	0	0
T3	128252	114	0	0
T4	239201	205	0	0
T5	227922	8	0	0
T6	217745	1910	0	0
T7	366484	969	0	0
T8	4238	73	0	0
T9	117310	147	0	0
T10	58306	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	208649	0	0
GntImpliesValid_A	396104503	208649	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	208649	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	3203821	0	0
ReadyAndValidImplyGrant_A	396104503	208649	0	0
ReqAndReadyImplyGrant_A	396104503	208649	0	0
ReqImpliesValid_A	396104503	566144	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	0	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	208649	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	3203821	0	0
T1	76889	693	0	0
T2	36168	636	0	0
T3	128252	3090	0	0
T4	239201	753	0	0
T5	227922	56	0	0
T6	217745	1163	0	0
T7	366484	8258	0	0
T8	4238	60	0	0
T9	117310	1223	0	0
T10	58306	507	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	566144	0	0
T1	76889	97	0	0
T2	36168	133	0	0
T3	128252	2459	0	0
T4	239201	202	0	0
T5	227922	11	0	0
T6	217745	2240	0	0
T7	366484	7260	0	0
T8	4238	77	0	0
T9	117310	173	0	0
T10	58306	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	872

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	208649	0	0
T1	76889	97	0	0
T2	36168	82	0	0
T3	128252	553	0	0
T4	239201	176	0	0
T5	227922	11	0	0
T6	217745	1694	0	0
T7	366484	1573	0	0
T8	4238	68	0	0
T9	117310	152	0	0
T10	58306	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	917473	0	0
GntImpliesValid_A	396104503	917473	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	917473	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	12324723	0	0
ReadyAndValidImplyGrant_A	396104503	917473	0	0
ReqAndReadyImplyGrant_A	396104503	917473	0	0
ReqImpliesValid_A	396104503	2439311	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	20601	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	917473	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	12324723	0	0
T1	76889	3440	0	0
T2	36168	2668	0	0
T3	128252	7857	0	0
T4	239201	2545	0	0
T5	227922	209	0	0
T6	217745	15	0	0
T7	366484	20904	0	0
T8	4238	1	0	0
T9	117310	3306	0	0
T10	58306	2763	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	2439311	0	0
T1	76889	568	0	0
T2	36168	745	0	0
T3	128252	1757	0	0
T4	239201	1009	0	0
T5	227922	67	0	0
T6	217745	10003	0	0
T7	366484	4876	0	0
T8	4238	250	0	0
T9	117310	561	0	0
T10	58306	636	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	20601	0	872
T6	217745	682	0	1
T7	366484	1	0	1
T8	4238	3	0	1
T9	117310	1	0	1
T10	58306	0	0	1
T11	364772	0	0	1
T12	61852	1	0	1
T13	37625	21	0	1
T14	0	18	0	0
T16	0	1411	0	0
T17	0	15	0	0
T18	0	3	0	0
T19	2250	0	0	1
T20	331168	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	917473	0	0
T1	76889	516	0	0
T2	36168	398	0	0
T3	128252	1190	0	0
T4	239201	774	0	0
T5	227922	56	0	0
T6	217745	10003	0	0
T7	366484	3150	0	0
T8	4238	250	0	0
T9	117310	535	0	0
T10	58306	412	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396104503	395980091	0	0
CheckNGreaterZero_A	872	872	0	0
GntImpliesReady_A	396104503	911944	0	0
GntImpliesValid_A	396104503	911944	0	0
GrantKnown_A	396104503	395980091	0	0
IdxKnown_A	396104503	395980091	0	0
IndexIsCorrect_A	396104503	911944	0	0
LockArbDecision_A	396104503	0	0	0
NoReadyValidNoGrant_A	396104503	332052828	0	0
ReadyAndValidImplyGrant_A	396104503	911944	0	0
ReqAndReadyImplyGrant_A	396104503	911944	0	0
ReqImpliesValid_A	396104503	13950360	0	0
ReqStaysHighUntilGranted0_M	396104503	0	0	0
RoundRobin_A	396104503	33039	0	872
ValidKnown_A	396104503	395980091	0	0
gen_data_port_assertion.DataFlow_A	396104503	911944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	872	872	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	332052828	0	0
T1	76889	66619	0	0
T2	36168	30241	0	0
T3	128252	101624	0	0
T4	239201	199065	0	0
T5	227922	189866	0	0
T6	217745	1	0	0
T7	366484	293405	0	0
T8	4238	1	0	0
T9	117310	102661	0	0
T10	58306	49360	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	13950360	0	0
T1	76889	3647	0	0
T2	36168	2899	0	0
T3	128252	16764	0	0
T4	239201	3625	0	0
T5	227922	213	0	0
T6	217745	13652	0	0
T7	366484	44846	0	0
T8	4238	242	0	0
T9	117310	4549	0	0
T10	58306	3315	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	33039	0	872
T3	128252	6	0	1
T4	239201	0	0	1
T5	227922	0	0	1
T6	217745	2644	0	1
T7	366484	25	0	1
T8	4238	3	0	1
T9	117310	1	0	1
T10	58306	0	0	1
T11	364772	0	0	1
T12	0	1	0	0
T13	0	524	0	0
T14	0	17	0	0
T15	0	1	0	0
T16	0	1686	0	0
T19	2250	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	395980091	0	0
T1	76889	76869	0	0
T2	36168	36112	0	0
T3	128252	128200	0	0
T4	239201	239196	0	0
T5	227922	227902	0	0
T6	217745	216466	0	0
T7	366484	366346	0	0
T8	4238	4185	0	0
T9	117310	117246	0	0
T10	58306	57464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396104503	911944	0	0
T1	76889	477	0	0
T2	36168	354	0	0
T3	128252	1938	0	0
T4	239201	818	0	0
T5	227922	54	0	0
T6	217745	13652	0	0
T7	366484	5264	0	0
T8	4238	242	0	0
T9	117310	575	0	0
T10	58306	407	0	0