Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1488454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236935

1

T1

214

T2

1

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	585964	1			T1	598		T2	2		T3	187
values[0x0]	553448	1			T1	516		T3	28		T4	22
values[0x1]	585977	1			T1	545		T2	5		T3	172

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150567	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

574822

1

T1

547

T2

3

T3

144

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26437	1			T1	22		T3	5		T4	4
valid_sources[0x01]	27059	1			T1	20		T3	3		T4	8
valid_sources[0x02]	26420	1			T3	3		T4	6		T6	39
valid_sources[0x03]	28162	1			T1	118		T3	2		T4	9
valid_sources[0x04]	26665	1			T1	48		T3	8		T4	5
valid_sources[0x05]	26471	1			T1	67		T3	6		T4	5
valid_sources[0x06]	26919	1			T1	16		T3	5		T4	4
valid_sources[0x07]	26817	1			T1	61		T3	9		T4	5
valid_sources[0x08]	26474	1			T1	74		T2	3		T3	1
valid_sources[0x09]	27163	1			T1	20		T2	1		T3	2
valid_sources[0x0a]	27351	1			T3	5		T4	5		T6	14
valid_sources[0x0b]	27810	1			T1	11		T3	11		T4	4
valid_sources[0x0c]	26525	1			T1	10		T3	5		T4	6
valid_sources[0x0d]	27381	1			T1	11		T3	5		T4	4
valid_sources[0x0e]	26696	1			T3	9		T4	7		T5	8
valid_sources[0x0f]	27332	1			T1	24		T3	11		T4	3
valid_sources[0x10]	25519	1			T1	43		T3	7		T4	6
valid_sources[0x11]	27329	1			T1	13		T3	9		T4	2
valid_sources[0x12]	27549	1			T1	34		T3	8		T4	6
valid_sources[0x13]	28391	1			T1	24		T3	6		T4	4
valid_sources[0x14]	27547	1			T1	30		T3	4		T4	7
valid_sources[0x15]	26879	1			T1	47		T3	7		T4	7
valid_sources[0x16]	26312	1			T3	5		T4	6		T5	3
valid_sources[0x17]	26562	1			T3	2		T4	2		T5	3
valid_sources[0x18]	26659	1			T3	9		T4	7		T5	5
valid_sources[0x19]	27978	1			T1	42		T3	4		T4	8
valid_sources[0x1a]	26943	1			T1	54		T2	1		T3	8
valid_sources[0x1b]	27478	1			T3	5		T4	5		T5	2
valid_sources[0x1c]	27157	1			T1	4		T2	1		T3	6
valid_sources[0x1d]	26493	1			T1	30		T3	5		T4	9
valid_sources[0x1e]	26781	1			T1	12		T3	2		T4	4
valid_sources[0x1f]	27264	1			T1	1		T3	5		T4	5
valid_sources[0x20]	27376	1			T1	29		T3	8		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25175

1

T1

19

T3

13

T4

7

values[0x0]

all_enables

biggest_size

186851

1

T1

169

T3

11

T4

8

values[0x1]

all_enables

biggest_size

24909

1

T1

26

T2

1

T3

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1498773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

244044

1

T1

250

T2

1

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596909	1			T1	589		T2	6		T3	195
values[0x0]	549213	1			T1	566		T3	34		T4	26
values[0x1]	596695	1			T1	598		T2	4		T3	189

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1150353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

592464

1

T1

571

T2

4

T3

161

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26308	1			T1	32		T3	9		T4	4
valid_sources[0x01]	27623	1			T1	22		T3	2		T4	3
valid_sources[0x02]	26883	1			T1	11		T2	1		T3	8
valid_sources[0x03]	27795	1			T1	9		T3	15		T4	5
valid_sources[0x04]	27291	1			T1	5		T3	5		T4	4
valid_sources[0x05]	26644	1			T1	19		T3	5		T4	6
valid_sources[0x06]	27458	1			T1	30		T3	6		T5	1
valid_sources[0x07]	26769	1			T1	42		T2	1		T3	5
valid_sources[0x08]	27028	1			T1	10		T3	9		T4	3
valid_sources[0x09]	27187	1			T1	37		T3	8		T4	7
valid_sources[0x0a]	26979	1			T1	45		T3	10		T4	2
valid_sources[0x0b]	27547	1			T1	54		T3	4		T4	6
valid_sources[0x0c]	26783	1			T1	30		T3	2		T4	9
valid_sources[0x0d]	27137	1			T1	11		T3	6		T4	4
valid_sources[0x0e]	27847	1			T2	1		T3	10		T4	4
valid_sources[0x0f]	27462	1			T1	15		T3	3		T5	4
valid_sources[0x10]	26985	1			T1	17		T3	2		T4	7
valid_sources[0x11]	27258	1			T1	50		T3	7		T4	3
valid_sources[0x12]	28062	1			T1	24		T3	9		T5	3
valid_sources[0x13]	28512	1			T1	13		T3	6		T4	9
valid_sources[0x14]	26493	1			T1	8		T2	1		T3	6
valid_sources[0x15]	27200	1			T1	29		T3	5		T4	4
valid_sources[0x16]	27106	1			T1	22		T3	9		T4	2
valid_sources[0x17]	27519	1			T2	1		T3	6		T4	2
valid_sources[0x18]	26734	1			T1	7		T2	1		T3	6
valid_sources[0x19]	27944	1			T1	33		T2	1		T3	7
valid_sources[0x1a]	27274	1			T1	24		T3	6		T4	3
valid_sources[0x1b]	27153	1			T1	19		T3	14		T4	3
valid_sources[0x1c]	27714	1			T1	70		T3	8		T4	9
valid_sources[0x1d]	27080	1			T1	23		T3	3		T4	5
valid_sources[0x1e]	27766	1			T1	25		T4	3		T5	2
valid_sources[0x1f]	27410	1			T1	4		T3	10		T4	13
valid_sources[0x20]	26939	1			T1	59		T3	11		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25891

1

T1

32

T3

19

T4

7

values[0x0]

all_enables

biggest_size

192616

1

T1

195

T3

14

T4

7

values[0x1]

all_enables

biggest_size

25537

1

T1

23

T2

1

T3

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1490513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236574

1

T1

240

T2

3

T3

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	586992	1			T1	557		T2	8		T3	155
values[0x0]	553698	1			T1	582		T2	2		T3	22
values[0x1]	586397	1			T1	583		T2	5		T3	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1152416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

574671

1

T1

558

T2

7

T3

126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27077	1			T1	2		T3	3		T4	11
valid_sources[0x01]	27843	1			T3	3		T4	4		T5	2
valid_sources[0x02]	27593	1			T1	8		T3	3		T4	8
valid_sources[0x03]	27715	1			T1	43		T3	3		T4	7
valid_sources[0x04]	26988	1			T1	12		T3	6		T4	4
valid_sources[0x05]	26759	1			T1	16		T3	5		T4	7
valid_sources[0x06]	26643	1			T1	3		T3	7		T4	3
valid_sources[0x07]	27215	1			T1	37		T3	9		T4	9
valid_sources[0x08]	26913	1			T1	8		T2	2		T3	12
valid_sources[0x09]	27296	1			T1	3		T3	7		T4	6
valid_sources[0x0a]	26588	1			T3	6		T4	4		T6	5
valid_sources[0x0b]	26640	1			T1	22		T3	5		T4	1
valid_sources[0x0c]	26601	1			T1	8		T2	1		T3	4
valid_sources[0x0d]	26680	1			T3	5		T4	4		T5	2
valid_sources[0x0e]	26454	1			T1	66		T3	6		T4	3
valid_sources[0x0f]	27420	1			T3	4		T4	5		T7	2
valid_sources[0x10]	26577	1			T1	47		T3	7		T4	5
valid_sources[0x11]	27270	1			T1	17		T2	1		T3	9
valid_sources[0x12]	26999	1			T1	57		T3	5		T4	5
valid_sources[0x13]	26709	1			T1	58		T2	1		T3	7
valid_sources[0x14]	26637	1			T1	12		T3	3		T4	2
valid_sources[0x15]	27162	1			T1	34		T3	6		T4	7
valid_sources[0x16]	26670	1			T1	6		T3	8		T4	10
valid_sources[0x17]	26705	1			T1	25		T3	4		T4	4
valid_sources[0x18]	26694	1			T1	17		T3	3		T4	6
valid_sources[0x19]	27695	1			T1	19		T3	3		T4	9
valid_sources[0x1a]	26663	1			T1	71		T2	1		T3	5
valid_sources[0x1b]	27068	1			T1	7		T2	1		T3	5
valid_sources[0x1c]	26673	1			T1	9		T2	1		T3	1
valid_sources[0x1d]	26361	1			T1	23		T3	6		T4	4
valid_sources[0x1e]	27348	1			T1	81		T3	6		T4	5
valid_sources[0x1f]	26346	1			T1	10		T3	7		T4	6
valid_sources[0x20]	27834	1			T1	81		T3	5		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24858

1

T1

28

T2

2

T3

13

values[0x0]

all_enables

biggest_size

186787

1

T1

188

T3

9

T4

8

values[0x1]

all_enables

biggest_size

24929

1

T1

24

T2

1

T3

18