Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21000	21000	0	0
GntImpliesReady_A	2147483647	7668688	0	0
GntImpliesValid_A	2147483647	7668688	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7668688	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	449538889	0	0
ReadyAndValidImplyGrant_A	2147483647	7668688	0	0
ReqAndReadyImplyGrant_A	2147483647	7668688	0	0
ReqImpliesValid_A	2147483647	33776155	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40503	0	21000
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7668688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	234792	233256	0	0
T2	33144	31728	0	0
T3	5507976	5504976	0	0
T4	4858752	4851888	0	0
T5	2782848	2782032	0	0
T6	842088	840456	0	0
T7	252648	251064	0	0
T8	143376	142440	0	0
T9	6301968	6301848	0	0
T10	278472	277872	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21000	21000	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	234792	233256	0	0
T2	33144	31728	0	0
T3	5507976	5504976	0	0
T4	4858752	4851888	0	0
T5	2782848	2782032	0	0
T6	842088	840456	0	0
T7	252648	251064	0	0
T8	143376	142440	0	0
T9	6301968	6301848	0	0
T10	278472	277872	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	234792	233256	0	0
T2	33144	31728	0	0
T3	5507976	5504976	0	0
T4	4858752	4851888	0	0
T5	2782848	2782032	0	0
T6	842088	840456	0	0
T7	252648	251064	0	0
T8	143376	142440	0	0
T9	6301968	6301848	0	0
T10	278472	277872	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	449538889	0	0
T1	234792	6711	0	0
T2	33144	601	0	0
T3	5507976	322412	0	0
T4	4858752	281569	0	0
T5	2782848	145920	0	0
T6	842088	45102	0	0
T7	252648	5251	0	0
T8	143376	2595	0	0
T9	6301968	2128205	0	0
T10	278472	13243	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33776155	0	0
T1	234792	6094	0	0
T2	33144	435	0	0
T3	5507976	37167	0	0
T4	4858752	78671	0	0
T5	2782848	23709	0	0
T6	842088	3399	0	0
T7	252648	4981	0	0
T8	143376	2267	0	0
T9	6301968	382655	0	0
T10	278472	1172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40503	0	21000
T1	19566	16	0	2
T2	2762	0	0	2
T3	458998	5	0	2
T4	404896	3	0	2
T5	231904	41	0	2
T6	70174	0	0	2
T7	21054	13	0	2
T8	11948	6	0	2
T9	525164	0	0	2
T10	23206	0	0	2
T12	0	4	0	0
T13	0	16	0	0
T14	0	131	0	0
T15	0	19	0	0
T16	0	13	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	234792	233256	0	0
T2	33144	31728	0	0
T3	5507976	5504976	0	0
T4	4858752	4851888	0	0
T5	2782848	2782032	0	0
T6	842088	840456	0	0
T7	252648	251064	0	0
T8	143376	142440	0	0
T9	6301968	6301848	0	0
T10	278472	277872	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7668688	0	0
T1	234792	5130	0	0
T2	33144	393	0	0
T3	5507976	17189	0	0
T4	4858752	20525	0	0
T5	2782848	9413	0	0
T6	842088	1870	0	0
T7	252648	4376	0	0
T8	143376	2229	0	0
T9	6301968	6266	0	0
T10	278472	475	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	845801	0	0
GntImpliesValid_A	412346693	845801	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	845801	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	11982234	0	0
ReadyAndValidImplyGrant_A	412346693	845801	0	0
ReqAndReadyImplyGrant_A	412346693	845801	0	0
ReqImpliesValid_A	412346693	2437596	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	845801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	11982234	0	0
T1	9783	417	0	0
T2	1381	41	0	0
T3	229499	12974	0	0
T4	202448	13473	0	0
T5	115952	6691	0	0
T6	35087	1424	0	0
T7	10527	388	0	0
T8	5974	208	0	0
T9	262582	222450	0	0
T10	11603	411	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2437596	0	0
T1	9783	730	0	0
T2	1381	54	0	0
T3	229499	2865	0	0
T4	202448	3040	0	0
T5	115952	1190	0	0
T6	35087	242	0	0
T7	10527	555	0	0
T8	5974	213	0	0
T9	262582	25036	0	0
T10	11603	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	845801	0	0
T1	9783	573	0	0
T2	1381	47	0	0
T3	229499	1862	0	0
T4	202448	1941	0	0
T5	115952	887	0	0
T6	35087	196	0	0
T7	10527	471	0	0
T8	5974	210	0	0
T9	262582	681	0	0
T10	11603	54	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	866294	0	0
GntImpliesValid_A	412346693	866294	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	866294	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	12043873	0	0
ReadyAndValidImplyGrant_A	412346693	866294	0	0
ReqAndReadyImplyGrant_A	412346693	866294	0	0
ReqImpliesValid_A	412346693	2422327	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	866294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	12043873	0	0
T1	9783	429	0	0
T2	1381	35	0	0
T3	229499	13597	0	0
T4	202448	15016	0	0
T5	115952	6604	0	0
T6	35087	1534	0	0
T7	10527	420	0	0
T8	5974	237	0	0
T9	262582	194609	0	0
T10	11603	486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2422327	0	0
T1	9783	738	0	0
T2	1381	52	0	0
T3	229499	2831	0	0
T4	202448	3400	0	0
T5	115952	1229	0	0
T6	35087	229	0	0
T7	10527	553	0	0
T8	5974	254	0	0
T9	262582	19576	0	0
T10	11603	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	866294	0	0
T1	9783	583	0	0
T2	1381	43	0	0
T3	229499	1844	0	0
T4	202448	1990	0	0
T5	115952	877	0	0
T6	35087	212	0	0
T7	10527	486	0	0
T8	5974	245	0	0
T9	262582	655	0	0
T10	11603	63	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	216231	0	0
GntImpliesValid_A	412346693	216231	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	216231	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3022257	0	0
ReadyAndValidImplyGrant_A	412346693	216231	0	0
ReqAndReadyImplyGrant_A	412346693	216231	0	0
ReqImpliesValid_A	412346693	574270	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	216231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3022257	0	0
T1	9783	144	0	0
T2	1381	11	0	0
T3	229499	3165	0	0
T4	202448	2479	0	0
T5	115952	1634	0	0
T6	35087	343	0	0
T7	10527	140	0	0
T8	5974	68	0	0
T9	262582	52980	0	0
T10	11603	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	574270	0	0
T1	9783	155	0	0
T2	1381	10	0	0
T3	229499	512	0	0
T4	202448	385	0	0
T5	115952	231	0	0
T6	35087	44	0	0
T7	10527	155	0	0
T8	5974	69	0	0
T9	262582	2971	0	0
T10	11603	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216231	0	0
T1	9783	149	0	0
T2	1381	10	0	0
T3	229499	426	0	0
T4	202448	318	0	0
T5	115952	221	0	0
T6	35087	44	0	0
T7	10527	147	0	0
T8	5974	68	0	0
T9	262582	167	0	0
T10	11603	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	210087	0	0
GntImpliesValid_A	412346693	210087	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	210087	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3008275	0	0
ReadyAndValidImplyGrant_A	412346693	210087	0	0
ReqAndReadyImplyGrant_A	412346693	210087	0	0
ReqImpliesValid_A	412346693	541751	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	210087	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3008275	0	0
T1	9783	131	0	0
T2	1381	25	0	0
T3	229499	3225	0	0
T4	202448	1965	0	0
T5	115952	1561	0	0
T6	35087	441	0	0
T7	10527	109	0	0
T8	5974	64	0	0
T9	262582	60815	0	0
T10	11603	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	541751	0	0
T1	9783	138	0	0
T2	1381	28	0	0
T3	229499	515	0	0
T4	202448	296	0	0
T5	115952	229	0	0
T6	35087	62	0	0
T7	10527	122	0	0
T8	5974	65	0	0
T9	262582	3101	0	0
T10	11603	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210087	0	0
T1	9783	134	0	0
T2	1381	26	0	0
T3	229499	415	0	0
T4	202448	252	0	0
T5	115952	197	0	0
T6	35087	54	0	0
T7	10527	115	0	0
T8	5974	64	0	0
T9	262582	192	0	0
T10	11603	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	202192	0	0
GntImpliesValid_A	412346693	202192	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	202192	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	5315208	0	0
ReadyAndValidImplyGrant_A	412346693	202192	0	0
ReqAndReadyImplyGrant_A	412346693	202192	0	0
ReqImpliesValid_A	412346693	1144968	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	202192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	5315208	0	0
T1	9783	745	0	0
T2	1381	100	0	0
T3	229499	11145	0	0
T4	202448	3439	0	0
T5	115952	1060	0	0
T6	35087	979	0	0
T7	10527	700	0	0
T8	5974	204	0	0
T9	262582	54337	0	0
T10	11603	126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	1144968	0	0
T1	9783	259	0	0
T2	1381	16	0	0
T3	229499	1029	0	0
T4	202448	3068	0	0
T5	115952	210	0	0
T6	35087	62	0	0
T7	10527	212	0	0
T8	5974	56	0	0
T9	262582	2050	0	0
T10	11603	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	202192	0	0
T1	9783	135	0	0
T2	1381	9	0	0
T3	229499	472	0	0
T4	202448	739	0	0
T5	115952	201	0	0
T6	35087	62	0	0
T7	10527	138	0	0
T8	5974	50	0	0
T9	262582	212	0	0
T10	11603	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	203114	0	0
GntImpliesValid_A	412346693	203114	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	203114	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	4771687	0	0
ReadyAndValidImplyGrant_A	412346693	203114	0	0
ReqAndReadyImplyGrant_A	412346693	203114	0	0
ReqImpliesValid_A	412346693	1031889	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	203114	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	4771687	0	0
T1	9783	979	0	0
T2	1381	112	0	0
T3	229499	6694	0	0
T4	202448	10812	0	0
T5	115952	998	0	0
T6	35087	2099	0	0
T7	10527	462	0	0
T8	5974	382	0	0
T9	262582	97087	0	0
T10	11603	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	1031889	0	0
T1	9783	281	0	0
T2	1381	9	0	0
T3	229499	855	0	0
T4	202448	1047	0	0
T5	115952	215	0	0
T6	35087	53	0	0
T7	10527	184	0	0
T8	5974	76	0	0
T9	262582	8285	0	0
T10	11603	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	203114	0	0
T1	9783	147	0	0
T2	1381	9	0	0
T3	229499	497	0	0
T4	202448	320	0	0
T5	115952	196	0	0
T6	35087	53	0	0
T7	10527	97	0	0
T8	5974	70	0	0
T9	262582	179	0	0
T10	11603	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	210845	0	0
GntImpliesValid_A	412346693	210845	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	210845	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	4714880	0	0
ReadyAndValidImplyGrant_A	412346693	210845	0	0
ReqAndReadyImplyGrant_A	412346693	210845	0	0
ReqImpliesValid_A	412346693	1056662	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	210845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	4714880	0	0
T1	9783	1035	0	0
T2	1381	58	0	0
T3	229499	6375	0	0
T4	202448	4555	0	0
T5	115952	1259	0	0
T6	35087	529	0	0
T7	10527	687	0	0
T8	5974	335	0	0
T9	262582	67087	0	0
T10	11603	124	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	1056662	0	0
T1	9783	327	0	0
T2	1381	22	0	0
T3	229499	706	0	0
T4	202448	524	0	0
T5	115952	219	0	0
T6	35087	35	0	0
T7	10527	220	0	0
T8	5974	83	0	0
T9	262582	1316	0	0
T10	11603	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	210845	0	0
T1	9783	135	0	0
T2	1381	10	0	0
T3	229499	467	0	0
T4	202448	300	0	0
T5	115952	213	0	0
T6	35087	35	0	0
T7	10527	123	0	0
T8	5974	80	0	0
T9	262582	179	0	0
T10	11603	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	208273	0	0
GntImpliesValid_A	412346693	208273	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	208273	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	5354691	0	0
ReadyAndValidImplyGrant_A	412346693	208273	0	0
ReqAndReadyImplyGrant_A	412346693	208273	0	0
ReqImpliesValid_A	412346693	1258981	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	208273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	5354691	0	0
T1	9783	974	0	0
T2	1381	57	0	0
T3	229499	5678	0	0
T4	202448	8943	0	0
T5	115952	1724	0	0
T6	35087	881	0	0
T7	10527	690	0	0
T8	5974	247	0	0
T9	262582	105368	0	0
T10	11603	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	1258981	0	0
T1	9783	243	0	0
T2	1381	9	0	0
T3	229499	622	0	0
T4	202448	10808	0	0
T5	115952	236	0	0
T6	35087	66	0	0
T7	10527	231	0	0
T8	5974	57	0	0
T9	262582	10279	0	0
T10	11603	23	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208273	0	0
T1	9783	160	0	0
T2	1381	9	0	0
T3	229499	469	0	0
T4	202448	2142	0	0
T5	115952	221	0	0
T6	35087	61	0	0
T7	10527	122	0	0
T8	5974	53	0	0
T9	262582	162	0	0
T10	11603	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	215498	0	0
GntImpliesValid_A	412346693	215498	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	215498	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3021906	0	0
ReadyAndValidImplyGrant_A	412346693	215498	0	0
ReqAndReadyImplyGrant_A	412346693	215498	0	0
ReqImpliesValid_A	412346693	556799	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	215498	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3021906	0	0
T1	9783	121	0	0
T2	1381	14	0	0
T3	229499	3559	0	0
T4	202448	3047	0	0
T5	115952	1462	0	0
T6	35087	243	0	0
T7	10527	106	0	0
T8	5974	70	0	0
T9	262582	58395	0	0
T10	11603	110	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	556799	0	0
T1	9783	138	0	0
T2	1381	13	0	0
T3	229499	626	0	0
T4	202448	584	0	0
T5	115952	214	0	0
T6	35087	38	0	0
T7	10527	123	0	0
T8	5974	69	0	0
T9	262582	3167	0	0
T10	11603	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215498	0	0
T1	9783	129	0	0
T2	1381	13	0	0
T3	229499	487	0	0
T4	202448	392	0	0
T5	115952	186	0	0
T6	35087	38	0	0
T7	10527	114	0	0
T8	5974	69	0	0
T9	262582	183	0	0
T10	11603	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	207485	0	0
GntImpliesValid_A	412346693	207485	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	207485	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2993211	0	0
ReadyAndValidImplyGrant_A	412346693	207485	0	0
ReqAndReadyImplyGrant_A	412346693	207485	0	0
ReqImpliesValid_A	412346693	529704	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	207485	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2993211	0	0
T1	9783	153	0	0
T2	1381	8	0	0
T3	229499	3352	0	0
T4	202448	2441	0	0
T5	115952	1828	0	0
T6	35087	438	0	0
T7	10527	110	0	0
T8	5974	55	0	0
T9	262582	55224	0	0
T10	11603	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	529704	0	0
T1	9783	166	0	0
T2	1381	7	0	0
T3	229499	525	0	0
T4	202448	386	0	0
T5	115952	283	0	0
T6	35087	69	0	0
T7	10527	113	0	0
T8	5974	54	0	0
T9	262582	4482	0	0
T10	11603	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	207485	0	0
T1	9783	159	0	0
T2	1381	7	0	0
T3	229499	427	0	0
T4	202448	309	0	0
T5	115952	227	0	0
T6	35087	62	0	0
T7	10527	111	0	0
T8	5974	54	0	0
T9	262582	167	0	0
T10	11603	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	209592	0	0
GntImpliesValid_A	412346693	209592	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	209592	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2935600	0	0
ReadyAndValidImplyGrant_A	412346693	209592	0	0
ReqAndReadyImplyGrant_A	412346693	209592	0	0
ReqImpliesValid_A	412346693	558502	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	209592	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2935600	0	0
T1	9783	117	0	0
T2	1381	14	0	0
T3	229499	3348	0	0
T4	202448	3135	0	0
T5	115952	1753	0	0
T6	35087	525	0	0
T7	10527	97	0	0
T8	5974	69	0	0
T9	262582	55325	0	0
T10	11603	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	558502	0	0
T1	9783	138	0	0
T2	1381	15	0	0
T3	229499	540	0	0
T4	202448	5350	0	0
T5	115952	254	0	0
T6	35087	61	0	0
T7	10527	100	0	0
T8	5974	70	0	0
T9	262582	1272	0	0
T10	11603	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	209592	0	0
T1	9783	127	0	0
T2	1381	14	0	0
T3	229499	450	0	0
T4	202448	841	0	0
T5	115952	242	0	0
T6	35087	61	0	0
T7	10527	98	0	0
T8	5974	69	0	0
T9	262582	151	0	0
T10	11603	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	214635	0	0
GntImpliesValid_A	412346693	214635	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	214635	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3014719	0	0
ReadyAndValidImplyGrant_A	412346693	214635	0	0
ReqAndReadyImplyGrant_A	412346693	214635	0	0
ReqImpliesValid_A	412346693	546869	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	214635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3014719	0	0
T1	9783	122	0	0
T2	1381	11	0	0
T3	229499	3306	0	0
T4	202448	2239	0	0
T5	115952	1615	0	0
T6	35087	488	0	0
T7	10527	106	0	0
T8	5974	59	0	0
T9	262582	59216	0	0
T10	11603	149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	546869	0	0
T1	9783	143	0	0
T2	1381	10	0	0
T3	229499	513	0	0
T4	202448	352	0	0
T5	115952	209	0	0
T6	35087	72	0	0
T7	10527	117	0	0
T8	5974	58	0	0
T9	262582	2286	0	0
T10	11603	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	214635	0	0
T1	9783	132	0	0
T2	1381	10	0	0
T3	229499	443	0	0
T4	202448	299	0	0
T5	115952	200	0	0
T6	35087	70	0	0
T7	10527	111	0	0
T8	5974	58	0	0
T9	262582	175	0	0
T10	11603	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	228133	0	0
GntImpliesValid_A	412346693	228133	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	228133	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3057356	0	0
ReadyAndValidImplyGrant_A	412346693	228133	0	0
ReqAndReadyImplyGrant_A	412346693	228133	0	0
ReqImpliesValid_A	412346693	599532	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	228133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3057356	0	0
T1	9783	121	0	0
T2	1381	10	0	0
T3	229499	3285	0	0
T4	202448	5902	0	0
T5	115952	1678	0	0
T6	35087	298	0	0
T7	10527	112	0	0
T8	5974	63	0	0
T9	262582	51587	0	0
T10	11603	93	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	599532	0	0
T1	9783	132	0	0
T2	1381	9	0	0
T3	229499	568	0	0
T4	202448	2173	0	0
T5	115952	233	0	0
T6	35087	42	0	0
T7	10527	117	0	0
T8	5974	62	0	0
T9	262582	1551	0	0
T10	11603	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	228133	0	0
T1	9783	126	0	0
T2	1381	9	0	0
T3	229499	439	0	0
T4	202448	857	0	0
T5	115952	218	0	0
T6	35087	40	0	0
T7	10527	114	0	0
T8	5974	62	0	0
T9	262582	160	0	0
T10	11603	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	208301	0	0
GntImpliesValid_A	412346693	208301	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	208301	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3000105	0	0
ReadyAndValidImplyGrant_A	412346693	208301	0	0
ReqAndReadyImplyGrant_A	412346693	208301	0	0
ReqImpliesValid_A	412346693	519302	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	208301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3000105	0	0
T1	9783	146	0	0
T2	1381	9	0	0
T3	229499	3795	0	0
T4	202448	3204	0	0
T5	115952	1906	0	0
T6	35087	387	0	0
T7	10527	133	0	0
T8	5974	60	0	0
T9	262582	60930	0	0
T10	11603	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	519302	0	0
T1	9783	163	0	0
T2	1381	8	0	0
T3	229499	551	0	0
T4	202448	4873	0	0
T5	115952	257	0	0
T6	35087	51	0	0
T7	10527	136	0	0
T8	5974	63	0	0
T9	262582	4381	0	0
T10	11603	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	208301	0	0
T1	9783	154	0	0
T2	1381	8	0	0
T3	229499	463	0	0
T4	202448	797	0	0
T5	115952	233	0	0
T6	35087	51	0	0
T7	10527	134	0	0
T8	5974	61	0	0
T9	262582	191	0	0
T10	11603	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	213005	0	0
GntImpliesValid_A	412346693	213005	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	213005	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3067545	0	0
ReadyAndValidImplyGrant_A	412346693	213005	0	0
ReqAndReadyImplyGrant_A	412346693	213005	0	0
ReqImpliesValid_A	412346693	541978	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	213005	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3067545	0	0
T1	9783	124	0	0
T2	1381	9	0	0
T3	229499	3455	0	0
T4	202448	2095	0	0
T5	115952	1816	0	0
T6	35087	469	0	0
T7	10527	100	0	0
T8	5974	58	0	0
T9	262582	70032	0	0
T10	11603	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	541978	0	0
T1	9783	129	0	0
T2	1381	8	0	0
T3	229499	551	0	0
T4	202448	359	0	0
T5	115952	235	0	0
T6	35087	57	0	0
T7	10527	105	0	0
T8	5974	57	0	0
T9	262582	4159	0	0
T10	11603	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	213005	0	0
T1	9783	126	0	0
T2	1381	8	0	0
T3	229499	460	0	0
T4	202448	269	0	0
T5	115952	230	0	0
T6	35087	57	0	0
T7	10527	102	0	0
T8	5974	57	0	0
T9	262582	196	0	0
T10	11603	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	212352	0	0
GntImpliesValid_A	412346693	212352	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	212352	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2997203	0	0
ReadyAndValidImplyGrant_A	412346693	212352	0	0
ReqAndReadyImplyGrant_A	412346693	212352	0	0
ReqImpliesValid_A	412346693	558804	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	212352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2997203	0	0
T1	9783	140	0	0
T2	1381	12	0	0
T3	229499	3255	0	0
T4	202448	2317	0	0
T5	115952	1859	0	0
T6	35087	515	0	0
T7	10527	129	0	0
T8	5974	67	0	0
T9	262582	60104	0	0
T10	11603	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	558804	0	0
T1	9783	151	0	0
T2	1381	13	0	0
T3	229499	493	0	0
T4	202448	412	0	0
T5	115952	253	0	0
T6	35087	72	0	0
T7	10527	156	0	0
T8	5974	66	0	0
T9	262582	5220	0	0
T10	11603	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212352	0	0
T1	9783	145	0	0
T2	1381	12	0	0
T3	229499	428	0	0
T4	202448	326	0	0
T5	115952	235	0	0
T6	35087	66	0	0
T7	10527	142	0	0
T8	5974	66	0	0
T9	262582	184	0	0
T10	11603	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	221894	0	0
GntImpliesValid_A	412346693	221894	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	221894	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	3010447	0	0
ReadyAndValidImplyGrant_A	412346693	221894	0	0
ReqAndReadyImplyGrant_A	412346693	221894	0	0
ReqImpliesValid_A	412346693	539340	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	221894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	3010447	0	0
T1	9783	127	0	0
T2	1381	19	0	0
T3	229499	4771	0	0
T4	202448	2629	0	0
T5	115952	2044	0	0
T6	35087	394	0	0
T7	10527	198	0	0
T8	5974	64	0	0
T9	262582	54135	0	0
T10	11603	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	539340	0	0
T1	9783	138	0	0
T2	1381	20	0	0
T3	229499	840	0	0
T4	202448	415	0	0
T5	115952	279	0	0
T6	35087	49	0	0
T7	10527	223	0	0
T8	5974	63	0	0
T9	262582	2779	0	0
T10	11603	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	221894	0	0
T1	9783	132	0	0
T2	1381	19	0	0
T3	229499	659	0	0
T4	202448	353	0	0
T5	115952	257	0	0
T6	35087	49	0	0
T7	10527	210	0	0
T8	5974	63	0	0
T9	262582	165	0	0
T10	11603	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	205812	0	0
GntImpliesValid_A	412346693	205812	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	205812	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2988783	0	0
ReadyAndValidImplyGrant_A	412346693	205812	0	0
ReqAndReadyImplyGrant_A	412346693	205812	0	0
ReqImpliesValid_A	412346693	528196	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	205812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2988783	0	0
T1	9783	140	0	0
T2	1381	9	0	0
T3	229499	6790	0	0
T4	202448	2438	0	0
T5	115952	1444	0	0
T6	35087	343	0	0
T7	10527	104	0	0
T8	5974	61	0	0
T9	262582	52558	0	0
T10	11603	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	528196	0	0
T1	9783	165	0	0
T2	1381	8	0	0
T3	229499	2366	0	0
T4	202448	549	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	105	0	0
T8	5974	60	0	0
T9	262582	1977	0	0
T10	11603	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	205812	0	0
T1	9783	152	0	0
T2	1381	8	0	0
T3	229499	954	0	0
T4	202448	372	0	0
T5	115952	203	0	0
T6	35087	45	0	0
T7	10527	104	0	0
T8	5974	60	0	0
T9	262582	160	0	0
T10	11603	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	216262	0	0
GntImpliesValid_A	412346693	216262	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	216262	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2964938	0	0
ReadyAndValidImplyGrant_A	412346693	216262	0	0
ReqAndReadyImplyGrant_A	412346693	216262	0	0
ReqImpliesValid_A	412346693	560128	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	216262	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2964938	0	0
T1	9783	136	0	0
T2	1381	11	0	0
T3	229499	3364	0	0
T4	202448	4694	0	0
T5	115952	1428	0	0
T6	35087	331	0	0
T7	10527	129	0	0
T8	5974	55	0	0
T9	262582	52726	0	0
T10	11603	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	560128	0	0
T1	9783	145	0	0
T2	1381	10	0	0
T3	229499	584	0	0
T4	202448	9837	0	0
T5	115952	204	0	0
T6	35087	46	0	0
T7	10527	132	0	0
T8	5974	54	0	0
T9	262582	3653	0	0
T10	11603	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	216262	0	0
T1	9783	140	0	0
T2	1381	10	0	0
T3	229499	431	0	0
T4	202448	1352	0	0
T5	115952	188	0	0
T6	35087	46	0	0
T7	10527	130	0	0
T8	5974	54	0	0
T9	262582	186	0	0
T10	11603	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	212873	0	0
GntImpliesValid_A	412346693	212873	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	212873	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2965851	0	0
ReadyAndValidImplyGrant_A	412346693	212873	0	0
ReqAndReadyImplyGrant_A	412346693	212873	0	0
ReqImpliesValid_A	412346693	568517	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	212873	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2965851	0	0
T1	9783	138	0	0
T2	1381	9	0	0
T3	229499	3012	0	0
T4	202448	4826	0	0
T5	115952	1799	0	0
T6	35087	506	0	0
T7	10527	99	0	0
T8	5974	63	0	0
T9	262582	57531	0	0
T10	11603	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	568517	0	0
T1	9783	151	0	0
T2	1381	12	0	0
T3	229499	469	0	0
T4	202448	2879	0	0
T5	115952	257	0	0
T6	35087	59	0	0
T7	10527	104	0	0
T8	5974	62	0	0
T9	262582	3959	0	0
T10	11603	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	212873	0	0
T1	9783	144	0	0
T2	1381	10	0	0
T3	229499	417	0	0
T4	202448	783	0	0
T5	115952	232	0	0
T6	35087	59	0	0
T7	10527	101	0	0
T8	5974	62	0	0
T9	262582	170	0	0
T10	11603	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	215656	0	0
GntImpliesValid_A	412346693	215656	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	215656	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2942731	0	0
ReadyAndValidImplyGrant_A	412346693	215656	0	0
ReqAndReadyImplyGrant_A	412346693	215656	0	0
ReqImpliesValid_A	412346693	556897	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	215656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2942731	0	0
T1	9783	135	0	0
T2	1381	13	0	0
T3	229499	3465	0	0
T4	202448	3240	0	0
T5	115952	1806	0	0
T6	35087	545	0	0
T7	10527	126	0	0
T8	5974	48	0	0
T9	262582	58610	0	0
T10	11603	98	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	556897	0	0
T1	9783	144	0	0
T2	1381	12	0	0
T3	229499	519	0	0
T4	202448	2494	0	0
T5	115952	261	0	0
T6	35087	62	0	0
T7	10527	137	0	0
T8	5974	49	0	0
T9	262582	2574	0	0
T10	11603	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	215656	0	0
T1	9783	139	0	0
T2	1381	12	0	0
T3	229499	446	0	0
T4	202448	788	0	0
T5	115952	240	0	0
T6	35087	62	0	0
T7	10527	131	0	0
T8	5974	48	0	0
T9	262582	175	0	0
T10	11603	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	211769	0	0
GntImpliesValid_A	412346693	211769	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	211769	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	2978942	0	0
ReadyAndValidImplyGrant_A	412346693	211769	0	0
ReqAndReadyImplyGrant_A	412346693	211769	0	0
ReqImpliesValid_A	412346693	560712	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	0	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	211769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2978942	0	0
T1	9783	135	0	0
T2	1381	12	0	0
T3	229499	3487	0	0
T4	202448	2332	0	0
T5	115952	1661	0	0
T6	35087	302	0	0
T7	10527	104	0	0
T8	5974	56	0	0
T9	262582	64823	0	0
T10	11603	120	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	560712	0	0
T1	9783	156	0	0
T2	1381	11	0	0
T3	229499	533	0	0
T4	202448	415	0	0
T5	115952	206	0	0
T6	35087	56	0	0
T7	10527	115	0	0
T8	5974	57	0	0
T9	262582	2702	0	0
T10	11603	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	875

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	211769	0	0
T1	9783	145	0	0
T2	1381	11	0	0
T3	229499	455	0	0
T4	202448	322	0	0
T5	115952	201	0	0
T6	35087	45	0	0
T7	10527	109	0	0
T8	5974	56	0	0
T9	262582	188	0	0
T10	11603	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	864758	0	0
GntImpliesValid_A	412346693	864758	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	864758	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	11216094	0	0
ReadyAndValidImplyGrant_A	412346693	864758	0	0
ReqAndReadyImplyGrant_A	412346693	864758	0	0
ReqImpliesValid_A	412346693	2321611	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	16974	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	864758	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	11216094	0	0
T1	9783	1	0	0
T2	1381	1	0	0
T3	229499	11850	0	0
T4	202448	12157	0	0
T5	115952	9525	0	0
T6	35087	1238	0	0
T7	10527	1	0	0
T8	5974	1	0	0
T9	262582	224684	0	0
T10	11603	302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	2321611	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	2619	0	0
T4	202448	2777	0	0
T5	115952	5089	0	0
T6	35087	209	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	20526	0	0
T10	11603	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	16974	0	875
T1	9783	6	0	1
T2	1381	0	0	1
T3	229499	0	0	1
T4	202448	0	0	1
T5	115952	7	0	1
T6	35087	0	0	1
T7	10527	6	0	1
T8	5974	2	0	1
T9	262582	0	0	1
T10	11603	0	0	1
T12	0	1	0	0
T13	0	6	0	0
T14	0	123	0	0
T15	0	10	0	0
T16	0	13	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	864758	0	0
T1	9783	576	0	0
T2	1381	36	0	0
T3	229499	1921	0	0
T4	202448	1884	0	0
T5	115952	1653	0	0
T6	35087	199	0	0
T7	10527	473	0	0
T8	5974	288	0	0
T9	262582	681	0	0
T10	11603	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412346693	412236247	0	0
CheckNGreaterZero_A	875	875	0	0
GntImpliesReady_A	412346693	847826	0	0
GntImpliesValid_A	412346693	847826	0	0
GrantKnown_A	412346693	412236247	0	0
IdxKnown_A	412346693	412236247	0	0
IndexIsCorrect_A	412346693	847826	0	0
LockArbDecision_A	412346693	0	0	0
NoReadyValidNoGrant_A	412346693	346170353	0	0
ReadyAndValidImplyGrant_A	412346693	847826	0	0
ReqAndReadyImplyGrant_A	412346693	847826	0	0
ReqImpliesValid_A	412346693	13260820	0	0
ReqStaysHighUntilGranted0_M	412346693	0	0	0
RoundRobin_A	412346693	23529	0	875
ValidKnown_A	412346693	412236247	0	0
gen_data_port_assertion.DataFlow_A	412346693	847826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	875	875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	346170353	0	0
T1	9783	1	0	0
T2	1381	1	0	0
T3	229499	195465	0	0
T4	202448	164191	0	0
T5	115952	90765	0	0
T6	35087	29850	0	0
T7	10527	1	0	0
T8	5974	1	0	0
T9	262582	237592	0	0
T10	11603	10170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	13260820	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	14935	0	0
T4	202448	22248	0	0
T5	115952	11513	0	0
T6	35087	1618	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	245353	0	0
T10	11603	413	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	23529	0	875
T1	9783	10	0	1
T2	1381	0	0	1
T3	229499	5	0	1
T4	202448	3	0	1
T5	115952	34	0	1
T6	35087	0	0	1
T7	10527	7	0	1
T8	5974	4	0	1
T9	262582	0	0	1
T10	11603	0	0	1
T12	0	3	0	0
T13	0	10	0	0
T14	0	8	0	0
T15	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	412236247	0	0
T1	9783	9719	0	0
T2	1381	1322	0	0
T3	229499	229374	0	0
T4	202448	202162	0	0
T5	115952	115918	0	0
T6	35087	35019	0	0
T7	10527	10461	0	0
T8	5974	5935	0	0
T9	262582	262577	0	0
T10	11603	11578	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412346693	847826	0	0
T1	9783	588	0	0
T2	1381	43	0	0
T3	229499	1857	0	0
T4	202448	2579	0	0
T5	115952	1655	0	0
T6	35087	203	0	0
T7	10527	493	0	0
T8	5974	262	0	0
T9	262582	707	0	0
T10	11603	49	0	0