Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1551377 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246610 1 T1 52 T2 10 T3 5


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 609746 1 T1 124 T2 37 T3 43
values[0x0] 577332 1 T1 125 T2 32 T3 6
values[0x1] 610909 1 T1 108 T2 42 T3 38


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1199267 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 598720 1 T1 120 T2 27 T3 29


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28466 1 T2 3 T3 4 T4 1
valid_sources[0x01] 28303 1 T1 22 T2 1 T5 24
valid_sources[0x02] 26738 1 T1 10 T2 3 T3 1
valid_sources[0x03] 27531 1 T2 4 T3 7 T5 8
valid_sources[0x04] 27486 1 T1 20 T3 3 T5 18
valid_sources[0x05] 28168 1 T2 2 T5 31 T6 74
valid_sources[0x06] 27701 1 T1 12 T3 3 T5 28
valid_sources[0x07] 28562 1 T5 17 T6 85 T7 18
valid_sources[0x08] 27771 1 T2 1 T4 4 T5 20
valid_sources[0x09] 27467 1 T1 16 T2 1 T5 17
valid_sources[0x0a] 27244 1 T1 18 T2 2 T5 8
valid_sources[0x0b] 26979 1 T2 4 T5 14 T6 70
valid_sources[0x0c] 28188 1 T2 12 T4 1 T5 7
valid_sources[0x0d] 28283 1 T1 27 T2 1 T4 18
valid_sources[0x0e] 27034 1 T1 16 T5 31 T6 81
valid_sources[0x0f] 28729 1 T2 3 T3 2 T5 16
valid_sources[0x10] 27785 1 T4 27 T5 27 T6 84
valid_sources[0x11] 28444 1 T5 26 T6 70 T7 5
valid_sources[0x12] 29232 1 T2 3 T5 22 T6 73
valid_sources[0x13] 27194 1 T1 11 T3 15 T5 19
valid_sources[0x14] 28564 1 T2 3 T3 1 T5 16
valid_sources[0x15] 27922 1 T2 1 T3 3 T5 16
valid_sources[0x16] 28774 1 T4 1 T5 17 T6 68
valid_sources[0x17] 27758 1 T3 2 T5 26 T6 75
valid_sources[0x18] 28214 1 T5 32 T6 77 T7 10
valid_sources[0x19] 27574 1 T2 1 T5 32 T6 59
valid_sources[0x1a] 28615 1 T4 8 T5 14 T6 76
valid_sources[0x1b] 28377 1 T2 2 T3 5 T5 20
valid_sources[0x1c] 28076 1 T4 22 T5 11 T6 65
valid_sources[0x1d] 28308 1 T5 16 T6 75 T7 11
valid_sources[0x1e] 28338 1 T1 10 T2 1 T3 1
valid_sources[0x1f] 28731 1 T5 15 T6 66 T7 12
valid_sources[0x20] 26972 1 T1 13 T2 1 T5 20


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25760 1 T1 4 T2 3 T3 1
values[0x0] all_enables biggest_size 194790 1 T1 45 T2 7 T3 3
values[0x1] all_enables biggest_size 26060 1 T1 3 T3 1 T4 3


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1556989 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 253216 1 T1 50 T2 18 T3 7


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 620150 1 T1 113 T2 47 T3 34
values[0x0] 570159 1 T1 128 T2 37 T3 6
values[0x1] 619896 1 T1 105 T2 47 T3 29


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1194750 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 615455 1 T1 107 T2 46 T3 26


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28474 1 T2 6 T3 1 T4 6
valid_sources[0x01] 28437 1 T1 17 T2 2 T3 2
valid_sources[0x02] 27645 1 T1 12 T2 1 T3 2
valid_sources[0x03] 27650 1 T2 1 T3 1 T4 2
valid_sources[0x04] 28229 1 T1 27 T2 2 T4 2
valid_sources[0x05] 27970 1 T2 2 T4 1 T5 17
valid_sources[0x06] 27715 1 T1 19 T2 2 T3 2
valid_sources[0x07] 28327 1 T2 2 T3 1 T4 1
valid_sources[0x08] 28410 1 T2 1 T3 4 T4 5
valid_sources[0x09] 27885 1 T1 5 T2 4 T5 15
valid_sources[0x0a] 28420 1 T1 11 T3 3 T4 5
valid_sources[0x0b] 28232 1 T2 3 T3 2 T4 4
valid_sources[0x0c] 28195 1 T3 2 T4 2 T5 18
valid_sources[0x0d] 29154 1 T1 29 T2 2 T4 2
valid_sources[0x0e] 27501 1 T1 34 T2 3 T3 1
valid_sources[0x0f] 28465 1 T2 1 T4 1 T5 13
valid_sources[0x10] 27713 1 T2 3 T4 4 T5 21
valid_sources[0x11] 28881 1 T2 3 T3 5 T5 22
valid_sources[0x12] 28704 1 T2 2 T3 1 T4 4
valid_sources[0x13] 28332 1 T1 14 T2 2 T4 1
valid_sources[0x14] 28353 1 T3 1 T5 19 T6 57
valid_sources[0x15] 28866 1 T3 1 T5 18 T6 69
valid_sources[0x16] 28695 1 T2 1 T5 25 T6 67
valid_sources[0x17] 28113 1 T2 1 T4 8 T5 28
valid_sources[0x18] 27461 1 T2 6 T4 3 T5 21
valid_sources[0x19] 27960 1 T3 2 T4 1 T5 17
valid_sources[0x1a] 28507 1 T2 2 T3 2 T4 3
valid_sources[0x1b] 28218 1 T4 5 T5 25 T6 74
valid_sources[0x1c] 28491 1 T2 3 T4 1 T5 22
valid_sources[0x1d] 28433 1 T2 3 T4 2 T5 20
valid_sources[0x1e] 28225 1 T1 13 T2 1 T4 2
valid_sources[0x1f] 28125 1 T2 3 T3 1 T4 2
valid_sources[0x20] 27686 1 T1 20 T2 1 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26794 1 T1 4 T2 3 T3 5
values[0x0] all_enables biggest_size 199598 1 T1 41 T2 15 T3 1
values[0x1] all_enables biggest_size 26824 1 T1 5 T3 1 T5 16


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1558400 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 247600 1 T1 46 T2 21 T3 13


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 613631 1 T1 124 T2 40 T3 41
values[0x0] 579818 1 T1 103 T2 45 T3 7
values[0x1] 612551 1 T1 112 T2 52 T3 32


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1204874 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 601126 1 T1 129 T2 47 T3 31


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27439 1 T4 7 T5 20 T6 64
valid_sources[0x01] 29554 1 T1 27 T3 1 T4 4
valid_sources[0x02] 27228 1 T1 10 T2 13 T4 5
valid_sources[0x03] 27222 1 T3 2 T5 21 T6 73
valid_sources[0x04] 27510 1 T1 28 T2 1 T3 1
valid_sources[0x05] 28472 1 T3 1 T5 18 T6 72
valid_sources[0x06] 27390 1 T1 12 T5 25 T6 69
valid_sources[0x07] 28188 1 T3 2 T4 4 T5 20
valid_sources[0x08] 28309 1 T2 2 T3 4 T4 1
valid_sources[0x09] 27724 1 T1 6 T3 2 T5 21
valid_sources[0x0a] 28441 1 T1 11 T4 4 T5 19
valid_sources[0x0b] 27609 1 T3 1 T5 27 T6 73
valid_sources[0x0c] 29142 1 T3 1 T4 3 T5 19
valid_sources[0x0d] 29084 1 T1 23 T5 19 T6 69
valid_sources[0x0e] 28507 1 T1 20 T3 1 T5 21
valid_sources[0x0f] 28533 1 T2 4 T3 2 T4 3
valid_sources[0x10] 28007 1 T2 16 T3 1 T4 4
valid_sources[0x11] 28798 1 T2 2 T3 1 T5 35
valid_sources[0x12] 28368 1 T4 10 T5 25 T6 68
valid_sources[0x13] 28442 1 T1 6 T5 23 T6 58
valid_sources[0x14] 27797 1 T2 15 T3 4 T5 15
valid_sources[0x15] 28892 1 T4 1 T5 32 T6 73
valid_sources[0x16] 28635 1 T3 2 T4 6 T5 24
valid_sources[0x17] 27502 1 T2 4 T4 7 T5 23
valid_sources[0x18] 27760 1 T3 1 T4 1 T5 26
valid_sources[0x19] 28187 1 T3 1 T5 25 T6 72
valid_sources[0x1a] 28038 1 T3 3 T4 2 T5 23
valid_sources[0x1b] 28280 1 T3 1 T4 6 T5 26
valid_sources[0x1c] 27450 1 T2 7 T4 1 T5 29
valid_sources[0x1d] 27411 1 T2 4 T3 1 T4 9
valid_sources[0x1e] 28870 1 T1 7 T2 3 T5 27
valid_sources[0x1f] 27831 1 T3 2 T5 20 T6 73
valid_sources[0x20] 27719 1 T1 5 T2 6 T3 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26240 1 T1 5 T3 8 T4 3
values[0x0] all_enables biggest_size 195580 1 T1 33 T2 17 T3 2
values[0x1] all_enables biggest_size 25780 1 T1 8 T2 4 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%