Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21144	21144	0	0
GntImpliesReady_A	2147483647	7889352	0	0
GntImpliesValid_A	2147483647	7889352	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7889352	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	451601666	0	0
ReadyAndValidImplyGrant_A	2147483647	7889352	0	0
ReqAndReadyImplyGrant_A	2147483647	7889352	0	0
ReqImpliesValid_A	2147483647	34235185	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49429	0	21144
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7889352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	466056	465168	0	0
T2	5875584	5875056	0	0
T3	151920	151704	0	0
T4	9941400	9940992	0	0
T5	953256	951888	0	0
T6	14268144	14268072	0	0
T7	70992	70224	0	0
T8	32568	32352	0	0
T9	389280	387552	0	0
T10	1604856	1604400	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21144	21144	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	466056	465168	0	0
T2	5875584	5875056	0	0
T3	151920	151704	0	0
T4	9941400	9940992	0	0
T5	953256	951888	0	0
T6	14268144	14268072	0	0
T7	70992	70224	0	0
T8	32568	32352	0	0
T9	389280	387552	0	0
T10	1604856	1604400	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	466056	465168	0	0
T2	5875584	5875056	0	0
T3	151920	151704	0	0
T4	9941400	9940992	0	0
T5	953256	951888	0	0
T6	14268144	14268072	0	0
T7	70992	70224	0	0
T8	32568	32352	0	0
T9	389280	387552	0	0
T10	1604856	1604400	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	451601666	0	0
T1	466056	25610	0	0
T2	5875584	205799	0	0
T3	151920	2872	0	0
T4	9941400	532089	0	0
T5	953256	44318	0	0
T6	14268144	549340	0	0
T7	70992	1873	0	0
T8	32568	386	0	0
T9	389280	11704	0	0
T10	1604856	102755	0	0
T11	0	1916	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34235185	0	0
T1	466056	1705	0	0
T2	5875584	658	0	0
T3	151920	2940	0	0
T4	9941400	25419	0	0
T5	953256	35743	0	0
T6	14268144	37766	0	0
T7	70992	2087	0	0
T8	32568	371	0	0
T9	389280	10234	0	0
T10	1604856	17511	0	0
T11	0	971	0	0
T12	0	3924	0	0
T13	0	8821	0	0
T14	0	175	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49429	0	21144
T3	12660	6	0	2
T4	828450	0	0	2
T5	79438	0	0	2
T6	1189012	23	0	2
T7	5916	6	0	2
T8	2714	0	0	2
T9	32440	21	0	2
T10	133738	4	0	2
T11	25538	0	0	2
T12	13958	0	0	2
T14	0	7	0	0
T15	0	12	0	0
T16	0	1274	0	0
T17	0	13	0	0
T18	0	26	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	466056	465168	0	0
T2	5875584	5875056	0	0
T3	151920	151704	0	0
T4	9941400	9940992	0	0
T5	953256	951888	0	0
T6	14268144	14268072	0	0
T7	70992	70224	0	0
T8	32568	32352	0	0
T9	389280	387552	0	0
T10	1604856	1604400	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7889352	0	0
T1	466056	1038	0	0
T2	5875584	379	0	0
T3	151920	2702	0	0
T4	9941400	486	0	0
T5	953256	4079	0	0
T6	14268144	13790	0	0
T7	70992	1842	0	0
T8	32568	356	0	0
T9	389280	8615	0	0
T10	1604856	7850	0	0
T11	0	579	0	0
T12	0	1966	0	0
T13	0	977	0	0
T14	0	165	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	869282	0	0
GntImpliesValid_A	417025414	869282	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	869282	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	11707392	0	0
ReadyAndValidImplyGrant_A	417025414	869282	0	0
ReqAndReadyImplyGrant_A	417025414	869282	0	0
ReqImpliesValid_A	417025414	2470027	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	869282	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	11707392	0	0
T1	19419	941	0	0
T2	244816	222	0	0
T3	6330	235	0	0
T4	414225	11560	0	0
T5	39719	2268	0	0
T6	594506	4079	0	0
T7	2958	154	0	0
T8	1357	37	0	0
T9	16220	732	0	0
T10	66869	6549	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2470027	0	0
T1	19419	131	0	0
T2	244816	69	0	0
T3	6330	338	0	0
T4	414225	926	0	0
T5	39719	510	0	0
T6	594506	1424	0	0
T7	2958	257	0	0
T8	1357	44	0	0
T9	16220	1225	0	0
T10	66869	1669	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	869282	0	0
T1	19419	118	0	0
T2	244816	49	0	0
T3	6330	286	0	0
T4	414225	36	0	0
T5	39719	314	0	0
T6	594506	981	0	0
T7	2958	205	0	0
T8	1357	40	0	0
T9	16220	978	0	0
T10	66869	903	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	889787	0	0
GntImpliesValid_A	417025414	889787	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	889787	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	11890413	0	0
ReadyAndValidImplyGrant_A	417025414	889787	0	0
ReqAndReadyImplyGrant_A	417025414	889787	0	0
ReqImpliesValid_A	417025414	2545196	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	889787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	11890413	0	0
T1	19419	1017	0	0
T2	244816	220	0	0
T3	6330	242	0	0
T4	414225	13629	0	0
T5	39719	2506	0	0
T6	594506	3735	0	0
T7	2958	153	0	0
T8	1357	26	0	0
T9	16220	752	0	0
T10	66869	6059	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2545196	0	0
T1	19419	145	0	0
T2	244816	73	0	0
T3	6330	321	0	0
T4	414225	785	0	0
T5	39719	512	0	0
T6	594506	1304	0	0
T7	2958	260	0	0
T8	1357	35	0	0
T9	16220	1179	0	0
T10	66869	1629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	889787	0	0
T1	19419	121	0	0
T2	244816	47	0	0
T3	6330	281	0	0
T4	414225	41	0	0
T5	39719	326	0	0
T6	594506	917	0	0
T7	2958	206	0	0
T8	1357	30	0	0
T9	16220	965	0	0
T10	66869	844	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	225769	0	0
GntImpliesValid_A	417025414	225769	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	225769	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	3044058	0	0
ReadyAndValidImplyGrant_A	417025414	225769	0	0
ReqAndReadyImplyGrant_A	417025414	225769	0	0
ReqImpliesValid_A	417025414	613352	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	225769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	3044058	0	0
T1	19419	210	0	0
T2	244816	34	0	0
T3	6330	79	0	0
T4	414225	2525	0	0
T5	39719	723	0	0
T6	594506	1928	0	0
T7	2958	53	0	0
T8	1357	16	0	0
T9	16220	234	0	0
T10	66869	1514	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	613352	0	0
T1	19419	25	0	0
T2	244816	14	0	0
T3	6330	88	0	0
T4	414225	7	0	0
T5	39719	5836	0	0
T6	594506	1229	0	0
T7	2958	58	0	0
T8	1357	15	0	0
T9	16220	269	0	0
T10	66869	296	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	225769	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	7	0	0
T5	39719	585	0	0
T6	594506	556	0	0
T7	2958	55	0	0
T8	1357	15	0	0
T9	16220	251	0	0
T10	66869	205	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	219998	0	0
GntImpliesValid_A	417025414	219998	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	219998	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2919256	0	0
ReadyAndValidImplyGrant_A	417025414	219998	0	0
ReqAndReadyImplyGrant_A	417025414	219998	0	0
ReqImpliesValid_A	417025414	572810	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	219998	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2919256	0	0
T1	19419	195	0	0
T2	244816	20	0	0
T3	6330	78	0	0
T4	414225	4723	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	45	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	1810	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	572810	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	81	0	0
T4	414225	445	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	10	0	0
T9	16220	266	0	0
T10	66869	415	0	0
T11	0	34	0	0
T14	0	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	219998	0	0
T1	19419	30	0	0
T2	244816	7	0	0
T3	6330	79	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	46	0	0
T8	1357	10	0	0
T9	16220	257	0	0
T10	66869	256	0	0
T11	0	27	0	0
T14	0	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	221818	0	0
GntImpliesValid_A	417025414	221818	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	221818	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	4599975	0	0
ReadyAndValidImplyGrant_A	417025414	221818	0	0
ReqAndReadyImplyGrant_A	417025414	221818	0	0
ReqImpliesValid_A	417025414	1079850	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	221818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	4599975	0	0
T1	19419	440	0	0
T2	244816	106	0	0
T3	6330	264	0	0
T4	414225	2393	0	0
T5	39719	142	0	0
T6	594506	7796	0	0
T7	2958	186	0	0
T8	1357	41	0	0
T9	16220	1986	0	0
T10	66869	1271	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	1079850	0	0
T1	19419	37	0	0
T2	244816	21	0	0
T3	6330	95	0	0
T4	414225	287	0	0
T5	39719	7203	0	0
T6	594506	4205	0	0
T7	2958	54	0	0
T8	1357	15	0	0
T9	16220	456	0	0
T10	66869	287	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	221818	0	0
T1	19419	37	0	0
T2	244816	6	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	292	0	0
T6	594506	1556	0	0
T7	2958	44	0	0
T8	1357	13	0	0
T9	16220	235	0	0
T10	66869	229	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	224144	0	0
GntImpliesValid_A	417025414	224144	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	224144	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	4827217	0	0
ReadyAndValidImplyGrant_A	417025414	224144	0	0
ReqAndReadyImplyGrant_A	417025414	224144	0	0
ReqImpliesValid_A	417025414	1168244	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	224144	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	4827217	0	0
T1	19419	1220	0	0
T2	244816	102	0	0
T3	6330	270	0	0
T4	414225	2033	0	0
T5	39719	0	0	0
T6	594506	9314	0	0
T7	2958	183	0	0
T8	1357	36	0	0
T9	16220	1216	0	0
T10	66869	1560	0	0
T11	0	619	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	1168244	0	0
T1	19419	25	0	0
T2	244816	47	0	0
T3	6330	106	0	0
T4	414225	29	0	0
T5	39719	0	0	0
T6	594506	4256	0	0
T7	2958	73	0	0
T8	1357	8	0	0
T9	16220	456	0	0
T10	66869	319	0	0
T11	0	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	224144	0	0
T1	19419	25	0	0
T2	244816	8	0	0
T3	6330	81	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	480	0	0
T7	2958	49	0	0
T8	1357	8	0	0
T9	16220	265	0	0
T10	66869	237	0	0
T11	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	215940	0	0
GntImpliesValid_A	417025414	215940	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	215940	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	4980006	0	0
ReadyAndValidImplyGrant_A	417025414	215940	0	0
ReqAndReadyImplyGrant_A	417025414	215940	0	0
ReqImpliesValid_A	417025414	1171608	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	215940	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	4980006	0	0
T1	19419	301	0	0
T2	244816	169	0	0
T3	6330	331	0	0
T4	414225	2694	0	0
T5	39719	0	0	0
T6	594506	3812	0	0
T7	2958	197	0	0
T8	1357	29	0	0
T9	16220	1436	0	0
T10	66869	2769	0	0
T11	0	994	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	1171608	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	108	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	1873	0	0
T7	2958	72	0	0
T8	1357	9	0	0
T9	16220	428	0	0
T10	66869	426	0	0
T11	0	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	215940	0	0
T1	19419	31	0	0
T2	244816	11	0	0
T3	6330	74	0	0
T4	414225	12	0	0
T5	39719	0	0	0
T6	594506	514	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	236	0	0
T10	66869	222	0	0
T11	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	209318	0	0
GntImpliesValid_A	417025414	209318	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	209318	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	5415230	0	0
ReadyAndValidImplyGrant_A	417025414	209318	0	0
ReqAndReadyImplyGrant_A	417025414	209318	0	0
ReqImpliesValid_A	417025414	1097478	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	209318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	5415230	0	0
T1	19419	219	0	0
T2	244816	42	0	0
T3	6330	264	0	0
T4	414225	2295	0	0
T5	39719	0	0	0
T6	594506	4551	0	0
T7	2958	203	0	0
T8	1357	32	0	0
T9	16220	1991	0	0
T10	66869	1180	0	0
T11	0	303	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	1097478	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	83	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	2673	0	0
T7	2958	87	0	0
T8	1357	10	0	0
T9	16220	574	0	0
T10	66869	273	0	0
T11	0	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209318	0	0
T1	19419	21	0	0
T2	244816	8	0	0
T3	6330	57	0	0
T4	414225	11	0	0
T5	39719	0	0	0
T6	594506	1061	0	0
T7	2958	53	0	0
T8	1357	10	0	0
T9	16220	229	0	0
T10	66869	205	0	0
T11	0	30	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	216768	0	0
GntImpliesValid_A	417025414	216768	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	216768	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2955056	0	0
ReadyAndValidImplyGrant_A	417025414	216768	0	0
ReqAndReadyImplyGrant_A	417025414	216768	0	0
ReqImpliesValid_A	417025414	599132	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	216768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2955056	0	0
T1	19419	187	0	0
T2	244816	46	0	0
T3	6330	68	0	0
T4	414225	6070	0	0
T5	39719	1	0	0
T6	594506	1912	0	0
T7	2958	39	0	0
T8	1357	12	0	0
T9	16220	203	0	0
T10	66869	1548	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	599132	0	0
T1	19419	26	0	0
T2	244816	12	0	0
T3	6330	69	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	1284	0	0
T7	2958	42	0	0
T8	1357	11	0	0
T9	16220	212	0	0
T10	66869	304	0	0
T11	0	43	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216768	0	0
T1	19419	26	0	0
T2	244816	11	0	0
T3	6330	68	0	0
T4	414225	16	0	0
T5	39719	0	0	0
T6	594506	560	0	0
T7	2958	40	0	0
T8	1357	11	0	0
T9	16220	207	0	0
T10	66869	211	0	0
T11	0	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	209199	0	0
GntImpliesValid_A	417025414	209199	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	209199	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2904181	0	0
ReadyAndValidImplyGrant_A	417025414	209199	0	0
ReqAndReadyImplyGrant_A	417025414	209199	0	0
ReqImpliesValid_A	417025414	530235	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	209199	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2904181	0	0
T1	19419	251	0	0
T2	244816	46	0	0
T3	6330	76	0	0
T4	414225	5041	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	56	0	0
T8	1357	8	0	0
T9	16220	219	0	0
T10	66869	1672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	530235	0	0
T1	19419	43	0	0
T2	244816	11	0	0
T3	6330	81	0	0
T4	414225	319	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	61	0	0
T8	1357	7	0	0
T9	16220	254	0	0
T10	66869	289	0	0
T11	0	40	0	0
T12	0	1005	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	209199	0	0
T1	19419	33	0	0
T2	244816	10	0	0
T3	6330	78	0	0
T4	414225	15	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	7	0	0
T9	16220	236	0	0
T10	66869	215	0	0
T11	0	36	0	0
T12	0	503	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	223082	0	0
GntImpliesValid_A	417025414	223082	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	223082	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2962570	0	0
ReadyAndValidImplyGrant_A	417025414	223082	0	0
ReqAndReadyImplyGrant_A	417025414	223082	0	0
ReqImpliesValid_A	417025414	619999	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	223082	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2962570	0	0
T1	19419	207	0	0
T2	244816	49	0	0
T3	6330	85	0	0
T4	414225	6805	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	217	0	0
T10	66869	1508	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	619999	0	0
T1	19419	28	0	0
T2	244816	17	0	0
T3	6330	90	0	0
T4	414225	229	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	67	0	0
T8	1357	10	0	0
T9	16220	236	0	0
T10	66869	257	0	0
T11	0	66	0	0
T13	0	4010	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	223082	0	0
T1	19419	28	0	0
T2	244816	12	0	0
T3	6330	87	0	0
T4	414225	22	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	10	0	0
T9	16220	226	0	0
T10	66869	203	0	0
T11	0	47	0	0
T13	0	487	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	216638	0	0
GntImpliesValid_A	417025414	216638	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	216638	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2954001	0	0
ReadyAndValidImplyGrant_A	417025414	216638	0	0
ReqAndReadyImplyGrant_A	417025414	216638	0	0
ReqImpliesValid_A	417025414	610358	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	216638	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2954001	0	0
T1	19419	201	0	0
T2	244816	64	0	0
T3	6330	64	0	0
T4	414225	4721	0	0
T5	39719	1	0	0
T6	594506	1444	0	0
T7	2958	36	0	0
T8	1357	16	0	0
T9	16220	243	0	0
T10	66869	1563	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	610358	0	0
T1	19419	25	0	0
T2	244816	18	0	0
T3	6330	71	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	1146	0	0
T7	2958	45	0	0
T8	1357	17	0	0
T9	16220	272	0	0
T10	66869	300	0	0
T11	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	216638	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	67	0	0
T4	414225	14	0	0
T5	39719	0	0	0
T6	594506	454	0	0
T7	2958	40	0	0
T8	1357	16	0	0
T9	16220	257	0	0
T10	66869	226	0	0
T11	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	217670	0	0
GntImpliesValid_A	417025414	217670	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	217670	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2977208	0	0
ReadyAndValidImplyGrant_A	417025414	217670	0	0
ReqAndReadyImplyGrant_A	417025414	217670	0	0
ReqImpliesValid_A	417025414	564735	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	217670	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2977208	0	0
T1	19419	332	0	0
T2	244816	39	0	0
T3	6330	84	0	0
T4	414225	4451	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	51	0	0
T8	1357	12	0	0
T9	16220	223	0	0
T10	66869	1681	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	564735	0	0
T1	19419	44	0	0
T2	244816	10	0	0
T3	6330	89	0	0
T4	414225	149	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	11	0	0
T9	16220	266	0	0
T10	66869	338	0	0
T11	0	52	0	0
T14	0	70	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	217670	0	0
T1	19419	37	0	0
T2	244816	10	0	0
T3	6330	86	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	244	0	0
T10	66869	216	0	0
T11	0	44	0	0
T14	0	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	222766	0	0
GntImpliesValid_A	417025414	222766	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	222766	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2960926	0	0
ReadyAndValidImplyGrant_A	417025414	222766	0	0
ReqAndReadyImplyGrant_A	417025414	222766	0	0
ReqImpliesValid_A	417025414	581205	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	222766	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2960926	0	0
T1	19419	227	0	0
T2	244816	68	0	0
T3	6330	83	0	0
T4	414225	7536	0	0
T5	39719	1362	0	0
T6	594506	1504	0	0
T7	2958	52	0	0
T8	1357	10	0	0
T9	16220	247	0	0
T10	66869	1610	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	581205	0	0
T1	19419	25	0	0
T2	244816	23	0	0
T3	6330	84	0	0
T4	414225	588	0	0
T5	39719	9331	0	0
T6	594506	1083	0	0
T7	2958	55	0	0
T8	1357	9	0	0
T9	16220	264	0	0
T10	66869	282	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222766	0	0
T1	19419	25	0	0
T2	244816	15	0	0
T3	6330	83	0	0
T4	414225	23	0	0
T5	39719	957	0	0
T6	594506	480	0	0
T7	2958	53	0	0
T8	1357	9	0	0
T9	16220	255	0	0
T10	66869	206	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	222721	0	0
GntImpliesValid_A	417025414	222721	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	222721	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	3011420	0	0
ReadyAndValidImplyGrant_A	417025414	222721	0	0
ReqAndReadyImplyGrant_A	417025414	222721	0	0
ReqImpliesValid_A	417025414	597053	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	222721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	3011420	0	0
T1	19419	198	0	0
T2	244816	33	0	0
T3	6330	81	0	0
T4	414225	3435	0	0
T5	39719	837	0	0
T6	594506	1785	0	0
T7	2958	50	0	0
T8	1357	7	0	0
T9	16220	219	0	0
T10	66869	1617	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	597053	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	86	0	0
T4	414225	9	0	0
T5	39719	4221	0	0
T6	594506	1292	0	0
T7	2958	63	0	0
T8	1357	6	0	0
T9	16220	252	0	0
T10	66869	346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	222721	0	0
T1	19419	30	0	0
T2	244816	5	0	0
T3	6330	83	0	0
T4	414225	9	0	0
T5	39719	457	0	0
T6	594506	527	0	0
T7	2958	56	0	0
T8	1357	6	0	0
T9	16220	235	0	0
T10	66869	223	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	218768	0	0
GntImpliesValid_A	417025414	218768	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	218768	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2922853	0	0
ReadyAndValidImplyGrant_A	417025414	218768	0	0
ReqAndReadyImplyGrant_A	417025414	218768	0	0
ReqImpliesValid_A	417025414	593398	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	218768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2922853	0	0
T1	19419	261	0	0
T2	244816	46	0	0
T3	6330	89	0	0
T4	414225	2893	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	57	0	0
T8	1357	14	0	0
T9	16220	230	0	0
T10	66869	1555	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	593398	0	0
T1	19419	33	0	0
T2	244816	17	0	0
T3	6330	98	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	60	0	0
T8	1357	13	0	0
T9	16220	257	0	0
T10	66869	293	0	0
T11	0	37	0	0
T12	0	1951	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	218768	0	0
T1	19419	33	0	0
T2	244816	9	0	0
T3	6330	93	0	0
T4	414225	9	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	58	0	0
T8	1357	13	0	0
T9	16220	243	0	0
T10	66869	209	0	0
T11	0	35	0	0
T12	0	977	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	242637	0	0
GntImpliesValid_A	417025414	242637	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	242637	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	3000646	0	0
ReadyAndValidImplyGrant_A	417025414	242637	0	0
ReqAndReadyImplyGrant_A	417025414	242637	0	0
ReqImpliesValid_A	417025414	607842	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	242637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	3000646	0	0
T1	19419	159	0	0
T2	244816	49	0	0
T3	6330	111	0	0
T4	414225	6143	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	56	0	0
T8	1357	8	0	0
T9	16220	204	0	0
T10	66869	1593	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	607842	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	124	0	0
T4	414225	744	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	9	0	0
T9	16220	227	0	0
T10	66869	316	0	0
T11	0	113	0	0
T12	0	968	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	242637	0	0
T1	19419	24	0	0
T2	244816	8	0	0
T3	6330	117	0	0
T4	414225	17	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	55	0	0
T8	1357	8	0	0
T9	16220	215	0	0
T10	66869	222	0	0
T11	0	49	0	0
T12	0	486	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	220518	0	0
GntImpliesValid_A	417025414	220518	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	220518	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2948215	0	0
ReadyAndValidImplyGrant_A	417025414	220518	0	0
ReqAndReadyImplyGrant_A	417025414	220518	0	0
ReqImpliesValid_A	417025414	580350	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	220518	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2948215	0	0
T1	19419	212	0	0
T2	244816	39	0	0
T3	6330	73	0	0
T4	414225	3787	0	0
T5	39719	1	0	0
T6	594506	6387	0	0
T7	2958	45	0	0
T8	1357	13	0	0
T9	16220	211	0	0
T10	66869	1690	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	580350	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	4494	0	0
T7	2958	48	0	0
T8	1357	16	0	0
T9	16220	240	0	0
T10	66869	333	0	0
T11	0	60	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	220518	0	0
T1	19419	29	0	0
T2	244816	7	0	0
T3	6330	72	0	0
T4	414225	13	0	0
T5	39719	0	0	0
T6	594506	1963	0	0
T7	2958	46	0	0
T8	1357	14	0	0
T9	16220	225	0	0
T10	66869	225	0	0
T11	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	214114	0	0
GntImpliesValid_A	417025414	214114	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	214114	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2938792	0	0
ReadyAndValidImplyGrant_A	417025414	214114	0	0
ReqAndReadyImplyGrant_A	417025414	214114	0	0
ReqImpliesValid_A	417025414	569257	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	214114	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2938792	0	0
T1	19419	192	0	0
T2	244816	70	0	0
T3	6330	74	0	0
T4	414225	2643	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	51	0	0
T8	1357	10	0	0
T9	16220	230	0	0
T10	66869	1580	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	569257	0	0
T1	19419	26	0	0
T2	244816	18	0	0
T3	6330	75	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	52	0	0
T8	1357	9	0	0
T9	16220	251	0	0
T10	66869	296	0	0
T11	0	46	0	0
T14	0	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	214114	0	0
T1	19419	26	0	0
T2	244816	14	0	0
T3	6330	74	0	0
T4	414225	8	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	51	0	0
T8	1357	9	0	0
T9	16220	240	0	0
T10	66869	214	0	0
T11	0	25	0	0
T14	0	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	208214	0	0
GntImpliesValid_A	417025414	208214	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	208214	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2905251	0	0
ReadyAndValidImplyGrant_A	417025414	208214	0	0
ReqAndReadyImplyGrant_A	417025414	208214	0	0
ReqImpliesValid_A	417025414	547995	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	208214	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2905251	0	0
T1	19419	275	0	0
T2	244816	57	0	0
T3	6330	75	0	0
T4	414225	6661	0	0
T5	39719	1	0	0
T6	594506	1	0	0
T7	2958	47	0	0
T8	1357	10	0	0
T9	16220	222	0	0
T10	66869	1701	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	547995	0	0
T1	19419	36	0	0
T2	244816	33	0	0
T3	6330	82	0	0
T4	414225	1655	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	50	0	0
T8	1357	9	0	0
T9	16220	241	0	0
T10	66869	291	0	0
T11	0	60	0	0
T13	0	4811	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	208214	0	0
T1	19419	36	0	0
T2	244816	17	0	0
T3	6330	78	0	0
T4	414225	21	0	0
T5	39719	0	0	0
T6	594506	0	0	0
T7	2958	48	0	0
T8	1357	9	0	0
T9	16220	231	0	0
T10	66869	233	0	0
T11	0	38	0	0
T13	0	490	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T5,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	212680	0	0
GntImpliesValid_A	417025414	212680	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	212680	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2947684	0	0
ReadyAndValidImplyGrant_A	417025414	212680	0	0
ReqAndReadyImplyGrant_A	417025414	212680	0	0
ReqImpliesValid_A	417025414	563870	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	212680	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2947684	0	0
T1	19419	259	0	0
T2	244816	27	0	0
T3	6330	80	0	0
T4	414225	5201	0	0
T5	39719	712	0	0
T6	594506	1	0	0
T7	2958	50	0	0
T8	1357	12	0	0
T9	16220	235	0	0
T10	66869	1415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	563870	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	81	0	0
T4	414225	12	0	0
T5	39719	5006	0	0
T6	594506	0	0	0
T7	2958	59	0	0
T8	1357	11	0	0
T9	16220	264	0	0
T10	66869	262	0	0
T11	0	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212680	0	0
T1	19419	26	0	0
T2	244816	7	0	0
T3	6330	80	0	0
T4	414225	12	0	0
T5	39719	495	0	0
T6	594506	0	0	0
T7	2958	54	0	0
T8	1357	11	0	0
T9	16220	249	0	0
T10	66869	199	0	0
T11	0	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	212693	0	0
GntImpliesValid_A	417025414	212693	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	212693	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	2950966	0	0
ReadyAndValidImplyGrant_A	417025414	212693	0	0
ReqAndReadyImplyGrant_A	417025414	212693	0	0
ReqImpliesValid_A	417025414	574731	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	0	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	212693	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2950966	0	0
T1	19419	289	0	0
T2	244816	48	0	0
T3	6330	64	0	0
T4	414225	6055	0	0
T5	39719	1	0	0
T6	594506	1463	0	0
T7	2958	53	0	0
T8	1357	13	0	0
T9	16220	203	0	0
T10	66869	1739	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	574731	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	69	0	0
T4	414225	490	0	0
T5	39719	0	0	0
T6	594506	1126	0	0
T7	2958	58	0	0
T8	1357	12	0	0
T9	16220	220	0	0
T10	66869	326	0	0
T11	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	881

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	212693	0	0
T1	19419	36	0	0
T2	244816	12	0	0
T3	6330	66	0	0
T4	414225	18	0	0
T5	39719	0	0	0
T6	594506	461	0	0
T7	2958	55	0	0
T8	1357	12	0	0
T9	16220	211	0	0
T10	66869	231	0	0
T11	0	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	867986	0	0
GntImpliesValid_A	417025414	867986	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	867986	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	11205489	0	0
ReadyAndValidImplyGrant_A	417025414	867986	0	0
ReqAndReadyImplyGrant_A	417025414	867986	0	0
ReqImpliesValid_A	417025414	2232082	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	17726	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	867986	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	11205489	0	0
T1	19419	809	0	0
T2	244816	156	0	0
T3	6330	1	0	0
T4	414225	22277	0	0
T5	39719	2040	0	0
T6	594506	4922	0	0
T7	2958	1	0	0
T8	1357	1	0	0
T9	16220	1	0	0
T10	66869	5121	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	2232082	0	0
T1	19419	130	0	0
T2	244816	52	0	0
T3	6330	292	0	0
T4	414225	1750	0	0
T5	39719	466	0	0
T6	594506	3079	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	1351	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	17726	0	881
T3	6330	5	0	1
T4	414225	0	0	1
T5	39719	0	0	1
T6	594506	11	0	1
T7	2958	3	0	1
T8	1357	0	0	1
T9	16220	13	0	1
T10	66869	1	0	1
T11	12769	0	0	1
T12	6979	0	0	1
T14	0	4	0	0
T15	0	12	0	0
T16	0	812	0	0
T17	0	6	0	0
T18	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	867986	0	0
T1	19419	120	0	0
T2	244816	44	0	0
T3	6330	292	0	0
T4	414225	70	0	0
T5	39719	317	0	0
T6	594506	1676	0	0
T7	2958	206	0	0
T8	1357	48	0	0
T9	16220	964	0	0
T10	66869	837	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417025414	416904614	0	0
CheckNGreaterZero_A	881	881	0	0
GntImpliesReady_A	417025414	886842	0	0
GntImpliesValid_A	417025414	886842	0	0
GrantKnown_A	417025414	416904614	0	0
IdxKnown_A	417025414	416904614	0	0
IndexIsCorrect_A	417025414	886842	0	0
LockArbDecision_A	417025414	0	0	0
NoReadyValidNoGrant_A	417025414	349672861	0	0
ReadyAndValidImplyGrant_A	417025414	886842	0	0
ReqAndReadyImplyGrant_A	417025414	886842	0	0
ReqImpliesValid_A	417025414	13144378	0	0
ReqStaysHighUntilGranted0_M	417025414	0	0	0
RoundRobin_A	417025414	31703	0	881
ValidKnown_A	417025414	416904614	0	0
gen_data_port_assertion.DataFlow_A	417025414	886842	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	881	881	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	349672861	0	0
T1	19419	17008	0	0
T2	244816	204047	0	0
T3	6330	1	0	0
T4	414225	396518	0	0
T5	39719	33716	0	0
T6	594506	494699	0	0
T7	2958	1	0	0
T8	1357	1	0	0
T9	16220	1	0	0
T10	66869	52450	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	13144378	0	0
T1	19419	699	0	0
T2	244816	158	0	0
T3	6330	257	0	0
T4	414225	16912	0	0
T5	39719	2658	0	0
T6	594506	7298	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	6613	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	31703	0	881
T3	6330	1	0	1
T4	414225	0	0	1
T5	39719	0	0	1
T6	594506	12	0	1
T7	2958	3	0	1
T8	1357	0	0	1
T9	16220	8	0	1
T10	66869	3	0	1
T11	12769	0	0	1
T12	6979	0	0	1
T14	0	3	0	0
T16	0	462	0	0
T17	0	7	0	0
T18	0	13	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	416904614	0	0
T1	19419	19382	0	0
T2	244816	244794	0	0
T3	6330	6321	0	0
T4	414225	414208	0	0
T5	39719	39662	0	0
T6	594506	594503	0	0
T7	2958	2926	0	0
T8	1357	1348	0	0
T9	16220	16148	0	0
T10	66869	66850	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417025414	886842	0	0
T1	19419	96	0	0
T2	244816	39	0	0
T3	6330	257	0	0
T4	414225	50	0	0
T5	39719	336	0	0
T6	594506	1604	0	0
T7	2958	199	0	0
T8	1357	27	0	0
T9	16220	961	0	0
T10	66869	879	0	0