Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1545559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246118

1

T1

7

T2

686

T3

301

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	607219	1			T1	29		T2	1708		T3	632
values[0x0]	576939	1			T1	4		T2	1679		T3	669
values[0x1]	607519	1			T1	38		T2	1633		T3	647

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1194717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

596960

1

T1

22

T2

1664

T3

653

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28238	1			T1	1		T2	69		T3	23
valid_sources[0x01]	27688	1			T2	74		T3	19		T4	3
valid_sources[0x02]	28251	1			T1	1		T2	91		T3	52
valid_sources[0x03]	27589	1			T2	88		T3	22		T4	1
valid_sources[0x04]	28999	1			T1	1		T2	81		T3	27
valid_sources[0x05]	28457	1			T1	1		T2	76		T3	26
valid_sources[0x06]	28028	1			T1	2		T2	76		T3	25
valid_sources[0x07]	28050	1			T1	3		T2	78		T3	25
valid_sources[0x08]	28542	1			T1	1		T2	85		T3	36
valid_sources[0x09]	28964	1			T2	67		T3	32		T5	29
valid_sources[0x0a]	27886	1			T2	66		T3	33		T4	2
valid_sources[0x0b]	27896	1			T2	88		T3	52		T4	1
valid_sources[0x0c]	27187	1			T2	68		T3	26		T4	1
valid_sources[0x0d]	28393	1			T1	5		T2	95		T3	37
valid_sources[0x0e]	27855	1			T1	3		T2	79		T3	42
valid_sources[0x0f]	28139	1			T1	1		T2	94		T3	24
valid_sources[0x10]	28220	1			T1	2		T2	72		T3	30
valid_sources[0x11]	27047	1			T1	1		T2	68		T3	26
valid_sources[0x12]	27333	1			T1	1		T2	89		T3	33
valid_sources[0x13]	28438	1			T2	73		T3	38		T4	3
valid_sources[0x14]	27481	1			T2	87		T3	29		T4	1
valid_sources[0x15]	27478	1			T2	70		T3	23		T4	1
valid_sources[0x16]	27481	1			T1	3		T2	70		T3	44
valid_sources[0x17]	26781	1			T1	5		T2	70		T3	31
valid_sources[0x18]	27791	1			T1	1		T2	74		T3	28
valid_sources[0x19]	27394	1			T2	71		T3	17		T5	19
valid_sources[0x1a]	26860	1			T2	73		T3	34		T4	2
valid_sources[0x1b]	27566	1			T2	74		T3	33		T5	27
valid_sources[0x1c]	28023	1			T2	74		T3	27		T5	11
valid_sources[0x1d]	28243	1			T2	71		T3	19		T4	4
valid_sources[0x1e]	27898	1			T2	78		T3	35		T4	4
valid_sources[0x1f]	28042	1			T1	1		T2	73		T3	18
valid_sources[0x20]	27130	1			T2	77		T3	22		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25579

1

T1

2

T2

65

T3

28

values[0x0]

all_enables

biggest_size

194768

1

T1

1

T2

549

T3

241

values[0x1]

all_enables

biggest_size

25771

1

T1

4

T2

72

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1555930	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

254493

1

T1

8

T2

672

T3

303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	618609	1			T1	35		T2	1688		T3	657
values[0x0]	573442	1			T1	4		T2	1592		T3	682
values[0x1]	618372	1			T1	41		T2	1579		T3	686

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1195473	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

614950

1

T1

32

T2

1628

T3

693

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28729	1			T1	2		T2	70		T3	18
valid_sources[0x01]	28367	1			T1	1		T2	83		T3	25
valid_sources[0x02]	28929	1			T2	66		T3	44		T4	3
valid_sources[0x03]	28813	1			T1	1		T2	62		T3	21
valid_sources[0x04]	27946	1			T1	3		T2	53		T3	23
valid_sources[0x05]	28214	1			T1	2		T2	48		T3	42
valid_sources[0x06]	28464	1			T1	3		T2	74		T3	21
valid_sources[0x07]	28614	1			T1	1		T2	69		T3	31
valid_sources[0x08]	28727	1			T1	1		T2	76		T3	31
valid_sources[0x09]	28155	1			T1	2		T2	84		T3	37
valid_sources[0x0a]	27658	1			T1	2		T2	74		T3	23
valid_sources[0x0b]	27242	1			T1	1		T2	94		T3	21
valid_sources[0x0c]	27919	1			T1	2		T2	53		T3	14
valid_sources[0x0d]	28062	1			T1	1		T2	69		T3	27
valid_sources[0x0e]	27945	1			T1	2		T2	68		T3	39
valid_sources[0x0f]	28498	1			T2	79		T3	27		T4	3
valid_sources[0x10]	28220	1			T1	2		T2	82		T3	38
valid_sources[0x11]	27883	1			T1	1		T2	55		T3	39
valid_sources[0x12]	28439	1			T2	80		T3	20		T4	3
valid_sources[0x13]	28568	1			T1	1		T2	78		T3	41
valid_sources[0x14]	28017	1			T1	2		T2	73		T3	39
valid_sources[0x15]	27773	1			T1	3		T2	54		T3	22
valid_sources[0x16]	28341	1			T1	1		T2	84		T3	39
valid_sources[0x17]	28372	1			T1	1		T2	56		T3	49
valid_sources[0x18]	28071	1			T1	2		T2	81		T3	24
valid_sources[0x19]	28507	1			T1	3		T2	65		T3	37
valid_sources[0x1a]	27953	1			T1	1		T2	84		T3	22
valid_sources[0x1b]	28212	1			T1	1		T2	83		T3	24
valid_sources[0x1c]	28595	1			T1	1		T2	62		T3	40
valid_sources[0x1d]	28894	1			T2	82		T3	41		T4	3
valid_sources[0x1e]	28347	1			T2	78		T3	25		T4	2
valid_sources[0x1f]	27988	1			T1	2		T2	66		T3	33
valid_sources[0x20]	27702	1			T1	3		T2	73		T3	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26425

1

T1

2

T2

64

T3

21

values[0x0]

all_enables

biggest_size

201166

1

T1

2

T2

547

T3

251

values[0x1]

all_enables

biggest_size

26902

1

T1

4

T2

61

T3

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1559599	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248869

1

T1

5

T2

644

T3

269

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	613614	1			T1	32		T2	1565		T3	677
values[0x0]	582993	1			T1	4		T2	1638		T3	681
values[0x1]	611861	1			T1	38		T2	1593		T3	681

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603468

1

T1

33

T2

1544

T3

654

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28419	1			T2	78		T3	23		T4	13
valid_sources[0x01]	28620	1			T1	2		T2	67		T3	39
valid_sources[0x02]	28373	1			T1	1		T2	72		T3	37
valid_sources[0x03]	28391	1			T1	1		T2	64		T3	32
valid_sources[0x04]	29105	1			T2	81		T3	32		T4	21
valid_sources[0x05]	28661	1			T1	1		T2	72		T3	33
valid_sources[0x06]	28301	1			T2	71		T3	37		T4	5
valid_sources[0x07]	28165	1			T2	88		T3	26		T5	27
valid_sources[0x08]	28485	1			T1	3		T2	74		T3	26
valid_sources[0x09]	28919	1			T2	84		T3	32		T5	21
valid_sources[0x0a]	27881	1			T1	1		T2	68		T3	15
valid_sources[0x0b]	28279	1			T1	1		T2	54		T3	31
valid_sources[0x0c]	27593	1			T1	2		T2	91		T3	41
valid_sources[0x0d]	28618	1			T1	3		T2	83		T3	34
valid_sources[0x0e]	27784	1			T1	1		T2	84		T3	23
valid_sources[0x0f]	28414	1			T1	2		T2	74		T3	47
valid_sources[0x10]	28371	1			T1	1		T2	75		T3	27
valid_sources[0x11]	27718	1			T1	1		T2	63		T3	38
valid_sources[0x12]	28225	1			T1	3		T2	62		T3	37
valid_sources[0x13]	28156	1			T1	1		T2	63		T3	30
valid_sources[0x14]	27641	1			T1	1		T2	79		T3	26
valid_sources[0x15]	27357	1			T1	1		T2	68		T3	35
valid_sources[0x16]	28655	1			T1	3		T2	68		T3	40
valid_sources[0x17]	28402	1			T1	1		T2	68		T3	31
valid_sources[0x18]	27596	1			T2	81		T3	26		T4	9
valid_sources[0x19]	28457	1			T1	1		T2	66		T3	27
valid_sources[0x1a]	28207	1			T1	1		T2	73		T3	43
valid_sources[0x1b]	28581	1			T1	1		T2	80		T3	34
valid_sources[0x1c]	28133	1			T1	1		T2	82		T3	36
valid_sources[0x1d]	28814	1			T1	1		T2	78		T3	31
valid_sources[0x1e]	27766	1			T1	3		T2	64		T3	20
valid_sources[0x1f]	27514	1			T1	1		T2	79		T3	42
valid_sources[0x20]	27505	1			T1	2		T2	89		T3	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25905

1

T1

3

T2

50

T3

33

values[0x0]

all_enables

biggest_size

197135

1

T1

1

T2

534

T3

204

values[0x1]

all_enables

biggest_size

25829

1

T1

1

T2

60

T3

32