Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21048	21048	0	0
GntImpliesReady_A	2147483647	7441709	0	0
GntImpliesValid_A	2147483647	7441709	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7441709	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	426101000	0	0
ReadyAndValidImplyGrant_A	2147483647	7441709	0	0
ReqAndReadyImplyGrant_A	2147483647	7441709	0	0
ReqImpliesValid_A	2147483647	32098337	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	37411	0	21048
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7441709	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	853200	852072	0	0
T2	18792576	18792360	0	0
T3	1289448	1287864	0	0
T4	54936	54192	0	0
T5	137160	135432	0	0
T6	3947232	3941064	0	0
T7	16652592	16650576	0	0
T8	1834200	1833552	0	0
T9	13370928	13369392	0	0
T10	1965264	1961832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21048	21048	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	853200	852072	0	0
T2	18792576	18792360	0	0
T3	1289448	1287864	0	0
T4	54936	54192	0	0
T5	137160	135432	0	0
T6	3947232	3941064	0	0
T7	16652592	16650576	0	0
T8	1834200	1833552	0	0
T9	13370928	13369392	0	0
T10	1965264	1961832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	853200	852072	0	0
T2	18792576	18792360	0	0
T3	1289448	1287864	0	0
T4	54936	54192	0	0
T5	137160	135432	0	0
T6	3947232	3941064	0	0
T7	16652592	16650576	0	0
T8	1834200	1833552	0	0
T9	13370928	13369392	0	0
T10	1965264	1961832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426101000	0	0
T1	853200	48289	0	0
T2	18792576	714739	0	0
T3	1289448	59929	0	0
T4	54936	741	0	0
T5	137160	3697	0	0
T6	3947232	212392	0	0
T7	16652592	587683	0	0
T8	1834200	95343	0	0
T9	13370928	785779	0	0
T10	1965264	125745	0	0
T11	0	5461	0	0
T12	0	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32098337	0	0
T1	853200	5367	0	0
T2	18792576	47015	0	0
T3	1289448	42561	0	0
T4	54936	557	0	0
T5	137160	3391	0	0
T6	3947232	73617	0	0
T7	16652592	3615	0	0
T8	1834200	8272	0	0
T9	13370928	133330	0	0
T10	1965264	18318	0	0
T11	0	2555	0	0
T12	0	5033	0	0
T13	0	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37411	0	21048
T1	35550	1	0	1
T2	783024	23	0	1
T3	53727	0	0	1
T4	2289	0	0	1
T5	11430	19	0	2
T6	328936	0	0	2
T7	1387716	0	0	2
T8	152850	0	0	2
T9	1114244	4	0	2
T10	163772	0	0	2
T11	52000	0	0	1
T12	12482	482	0	1
T13	1764	0	0	1
T14	0	1	0	0
T15	0	52	0	0
T16	0	32	0	0
T17	0	26	0	0
T18	0	306	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	25	0	0
T23	0	6	0	0
T24	0	8	0	0
T25	541282	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	853200	852072	0	0
T2	18792576	18792360	0	0
T3	1289448	1287864	0	0
T4	54936	54192	0	0
T5	137160	135432	0	0
T6	3947232	3941064	0	0
T7	16652592	16650576	0	0
T8	1834200	1833552	0	0
T9	13370928	13369392	0	0
T10	1965264	1961832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7441709	0	0
T1	853200	2575	0	0
T2	18792576	14670	0	0
T3	1289448	6012	0	0
T4	54936	456	0	0
T5	137160	2843	0	0
T6	3947232	14998	0	0
T7	16652592	2175	0	0
T8	1834200	4311	0	0
T9	13370928	51431	0	0
T10	1965264	8118	0	0
T11	0	1849	0	0
T12	0	1991	0	0
T13	0	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	831490	0	0
GntImpliesValid_A	394058916	831490	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	831490	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	10958011	0	0
ReadyAndValidImplyGrant_A	394058916	831490	0	0
ReqAndReadyImplyGrant_A	394058916	831490	0	0
ReqImpliesValid_A	394058916	2262077	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	831490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	10958011	0	0
T1	35550	1974	0	0
T2	783024	4238	0	0
T3	53727	3826	0	0
T4	2289	43	0	0
T5	5715	221	0	0
T6	164468	10182	0	0
T7	693858	1075	0	0
T8	76425	3403	0	0
T9	557122	38683	0	0
T10	81886	5886	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2262077	0	0
T1	35550	526	0	0
T2	783024	1461	0	0
T3	53727	9088	0	0
T4	2289	72	0	0
T5	5715	390	0	0
T6	164468	18677	0	0
T7	693858	368	0	0
T8	76425	541	0	0
T9	557122	7513	0	0
T10	81886	1408	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831490	0	0
T1	35550	282	0	0
T2	783024	1065	0	0
T3	53727	1208	0	0
T4	2289	57	0	0
T5	5715	305	0	0
T6	164468	2767	0	0
T7	693858	258	0	0
T8	76425	473	0	0
T9	557122	5145	0	0
T10	81886	899	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	831201	0	0
GntImpliesValid_A	394058916	831201	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	831201	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	11106170	0	0
ReadyAndValidImplyGrant_A	394058916	831201	0	0
ReqAndReadyImplyGrant_A	394058916	831201	0	0
ReqImpliesValid_A	394058916	2340232	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	831201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	11106170	0	0
T1	35550	2014	0	0
T2	783024	6252	0	0
T3	53727	3534	0	0
T4	2289	36	0	0
T5	5715	218	0	0
T6	164468	10532	0	0
T7	693858	1141	0	0
T8	76425	3316	0	0
T9	557122	45483	0	0
T10	81886	6565	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2340232	0	0
T1	35550	373	0	0
T2	783024	3242	0	0
T3	53727	790	0	0
T4	2289	41	0	0
T5	5715	363	0	0
T6	164468	4457	0	0
T7	693858	356	0	0
T8	76425	464	0	0
T9	557122	17117	0	0
T10	81886	1691	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	831201	0	0
T1	35550	281	0	0
T2	783024	1710	0	0
T3	53727	461	0	0
T4	2289	38	0	0
T5	5715	290	0	0
T6	164468	2002	0	0
T7	693858	257	0	0
T8	76425	443	0	0
T9	557122	6749	0	0
T10	81886	897	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	211128	0	0
GntImpliesValid_A	394058916	211128	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	211128	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2742274	0	0
ReadyAndValidImplyGrant_A	394058916	211128	0	0
ReqAndReadyImplyGrant_A	394058916	211128	0	0
ReqImpliesValid_A	394058916	538001	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	211128	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2742274	0	0
T1	35550	676	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	13	0	0
T5	5715	96	0	0
T6	164468	1136	0	0
T7	693858	239	0	0
T8	76425	891	0	0
T9	557122	15544	0	0
T10	81886	1761	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	538001	0	0
T1	35550	102	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	111	0	0
T6	164468	167	0	0
T7	693858	70	0	0
T8	76425	128	0	0
T9	557122	7564	0	0
T10	81886	346	0	0
T11	0	152	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	211128	0	0
T1	35550	83	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	103	0	0
T6	164468	151	0	0
T7	693858	54	0	0
T8	76425	115	0	0
T9	557122	2401	0	0
T10	81886	226	0	0
T11	0	116	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	200458	0	0
GntImpliesValid_A	394058916	200458	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	200458	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2742443	0	0
ReadyAndValidImplyGrant_A	394058916	200458	0	0
ReqAndReadyImplyGrant_A	394058916	200458	0	0
ReqImpliesValid_A	394058916	551314	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	200458	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2742443	0	0
T1	35550	447	0	0
T2	783024	1939	0	0
T3	53727	836	0	0
T4	2289	13	0	0
T5	5715	72	0	0
T6	164468	1014	0	0
T7	693858	287	0	0
T8	76425	805	0	0
T9	557122	6963	0	0
T10	81886	1891	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	551314	0	0
T1	35550	83	0	0
T2	783024	1182	0	0
T3	53727	10010	0	0
T4	2289	12	0	0
T5	5715	77	0	0
T6	164468	163	0	0
T7	693858	77	0	0
T8	76425	113	0	0
T9	557122	1081	0	0
T10	81886	336	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200458	0	0
T1	35550	70	0	0
T2	783024	553	0	0
T3	53727	956	0	0
T4	2289	12	0	0
T5	5715	74	0	0
T6	164468	144	0	0
T7	693858	67	0	0
T8	76425	113	0	0
T9	557122	919	0	0
T10	81886	236	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	208656	0	0
GntImpliesValid_A	394058916	208656	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	208656	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	4878615	0	0
ReadyAndValidImplyGrant_A	394058916	208656	0	0
ReqAndReadyImplyGrant_A	394058916	208656	0	0
ReqImpliesValid_A	394058916	1238201	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	208656	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	4878615	0	0
T1	35550	1449	0	0
T2	783024	20743	0	0
T3	53727	0	0	0
T4	2289	270	0	0
T5	5715	361	0	0
T6	164468	2153	0	0
T7	693858	1592	0	0
T8	76425	1492	0	0
T9	557122	9934	0	0
T10	81886	2449	0	0
T11	0	928	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	1238201	0	0
T1	35550	156	0	0
T2	783024	9552	0	0
T3	53727	0	0	0
T4	2289	99	0	0
T5	5715	109	0	0
T6	164468	215	0	0
T7	693858	114	0	0
T8	76425	118	0	0
T9	557122	1045	0	0
T10	81886	399	0	0
T11	0	156	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	208656	0	0
T1	35550	78	0	0
T2	783024	924	0	0
T3	53727	0	0	0
T4	2289	24	0	0
T5	5715	62	0	0
T6	164468	142	0	0
T7	693858	64	0	0
T8	76425	106	0	0
T9	557122	938	0	0
T10	81886	215	0	0
T11	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	210059	0	0
GntImpliesValid_A	394058916	210059	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	210059	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	4852471	0	0
ReadyAndValidImplyGrant_A	394058916	210059	0	0
ReqAndReadyImplyGrant_A	394058916	210059	0	0
ReqImpliesValid_A	394058916	1326182	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	210059	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	4852471	0	0
T1	35550	645	0	0
T2	783024	5919	0	0
T3	53727	0	0	0
T4	2289	53	0	0
T5	5715	530	0	0
T6	164468	2372	0	0
T7	693858	787	0	0
T8	76425	1517	0	0
T9	557122	6749	0	0
T10	81886	2272	0	0
T11	0	1461	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	1326182	0	0
T1	35550	87	0	0
T2	783024	3524	0	0
T3	53727	0	0	0
T4	2289	16	0	0
T5	5715	131	0	0
T6	164468	4591	0	0
T7	693858	111	0	0
T8	76425	151	0	0
T9	557122	1812	0	0
T10	81886	330	0	0
T11	0	198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210059	0	0
T1	35550	47	0	0
T2	783024	857	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	71	0	0
T6	164468	578	0	0
T7	693858	69	0	0
T8	76425	144	0	0
T9	557122	1472	0	0
T10	81886	209	0	0
T11	0	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	202176	0	0
GntImpliesValid_A	394058916	202176	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	202176	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	4473111	0	0
ReadyAndValidImplyGrant_A	394058916	202176	0	0
ReqAndReadyImplyGrant_A	394058916	202176	0	0
ReqImpliesValid_A	394058916	1046518	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	202176	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	4473111	0	0
T1	35550	593	0	0
T2	783024	3464	0	0
T3	53727	0	0	0
T4	2289	49	0	0
T5	5715	528	0	0
T6	164468	1794	0	0
T7	693858	395	0	0
T8	76425	867	0	0
T9	557122	6083	0	0
T10	81886	4300	0	0
T11	0	1231	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	1046518	0	0
T1	35550	88	0	0
T2	783024	1826	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	203	0	0
T6	164468	162	0	0
T7	693858	50	0	0
T8	76425	122	0	0
T9	557122	1760	0	0
T10	81886	420	0	0
T11	0	168	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202176	0	0
T1	35550	70	0	0
T2	783024	476	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	107	0	0
T6	164468	132	0	0
T7	693858	43	0	0
T8	76425	111	0	0
T9	557122	1322	0	0
T10	81886	197	0	0
T11	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	201805	0	0
GntImpliesValid_A	394058916	201805	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	201805	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	4573825	0	0
ReadyAndValidImplyGrant_A	394058916	201805	0	0
ReqAndReadyImplyGrant_A	394058916	201805	0	0
ReqImpliesValid_A	394058916	1015631	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	201805	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	4573825	0	0
T1	35550	789	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	81	0	0
T5	5715	574	0	0
T6	164468	3461	0	0
T7	693858	867	0	0
T8	76425	1286	0	0
T9	557122	11775	0	0
T10	81886	2640	0	0
T11	0	1841	0	0
T12	0	36	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	1015631	0	0
T1	35550	137	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	186	0	0
T6	164468	320	0	0
T7	693858	107	0	0
T8	76425	116	0	0
T9	557122	6604	0	0
T10	81886	358	0	0
T11	0	116	0	0
T12	0	1975	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201805	0	0
T1	35550	80	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	80	0	0
T6	164468	164	0	0
T7	693858	51	0	0
T8	76425	114	0	0
T9	557122	2453	0	0
T10	81886	250	0	0
T11	0	97	0	0
T12	0	446	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	209858	0	0
GntImpliesValid_A	394058916	209858	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	209858	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2774782	0	0
ReadyAndValidImplyGrant_A	394058916	209858	0	0
ReqAndReadyImplyGrant_A	394058916	209858	0	0
ReqImpliesValid_A	394058916	567889	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	209858	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2774782	0	0
T1	35550	495	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	18	0	0
T5	5715	78	0	0
T6	164468	2303	0	0
T7	693858	241	0	0
T8	76425	809	0	0
T9	557122	13177	0	0
T10	81886	1686	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	567889	0	0
T1	35550	90	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	87	0	0
T6	164468	5182	0	0
T7	693858	68	0	0
T8	76425	115	0	0
T9	557122	4598	0	0
T10	81886	252	0	0
T11	0	131	0	0
T12	0	1029	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209858	0	0
T1	35550	69	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	17	0	0
T5	5715	82	0	0
T6	164468	718	0	0
T7	693858	64	0	0
T8	76425	109	0	0
T9	557122	1884	0	0
T10	81886	217	0	0
T11	0	116	0	0
T12	0	529	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	210343	0	0
GntImpliesValid_A	394058916	210343	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	210343	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2771180	0	0
ReadyAndValidImplyGrant_A	394058916	210343	0	0
ReqAndReadyImplyGrant_A	394058916	210343	0	0
ReqImpliesValid_A	394058916	533006	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	210343	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2771180	0	0
T1	35550	463	0	0
T2	783024	1349	0	0
T3	53727	1394	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	1269	0	0
T7	693858	229	0	0
T8	76425	897	0	0
T9	557122	12886	0	0
T10	81886	1608	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	533006	0	0
T1	35550	63	0	0
T2	783024	1142	0	0
T3	53727	1895	0	0
T4	2289	11	0	0
T5	5715	89	0	0
T6	164468	193	0	0
T7	693858	66	0	0
T8	76425	129	0	0
T9	557122	3552	0	0
T10	81886	356	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	210343	0	0
T1	35550	60	0	0
T2	783024	436	0	0
T3	53727	510	0	0
T4	2289	11	0	0
T5	5715	86	0	0
T6	164468	161	0	0
T7	693858	56	0	0
T8	76425	129	0	0
T9	557122	1830	0	0
T10	81886	239	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	209655	0	0
GntImpliesValid_A	394058916	209655	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	209655	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2769426	0	0
ReadyAndValidImplyGrant_A	394058916	209655	0	0
ReqAndReadyImplyGrant_A	394058916	209655	0	0
ReqImpliesValid_A	394058916	558845	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	209655	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2769426	0	0
T1	35550	496	0	0
T2	783024	3397	0	0
T3	53727	505	0	0
T4	2289	12	0	0
T5	5715	78	0	0
T6	164468	3283	0	0
T7	693858	243	0	0
T8	76425	826	0	0
T9	557122	9914	0	0
T10	81886	1633	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	558845	0	0
T1	35550	69	0	0
T2	783024	2396	0	0
T3	53727	5604	0	0
T4	2289	13	0	0
T5	5715	91	0	0
T6	164468	2913	0	0
T7	693858	77	0	0
T8	76425	115	0	0
T9	557122	2487	0	0
T10	81886	276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	209655	0	0
T1	35550	65	0	0
T2	783024	1036	0	0
T3	53727	533	0	0
T4	2289	12	0	0
T5	5715	84	0	0
T6	164468	623	0	0
T7	693858	60	0	0
T8	76425	115	0	0
T9	557122	1337	0	0
T10	81886	200	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	203533	0	0
GntImpliesValid_A	394058916	203533	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	203533	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2743030	0	0
ReadyAndValidImplyGrant_A	394058916	203533	0	0
ReqAndReadyImplyGrant_A	394058916	203533	0	0
ReqImpliesValid_A	394058916	516256	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	203533	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2743030	0	0
T1	35550	592	0	0
T2	783024	3095	0	0
T3	53727	1	0	0
T4	2289	14	0	0
T5	5715	73	0	0
T6	164468	4629	0	0
T7	693858	248	0	0
T8	76425	957	0	0
T9	557122	7193	0	0
T10	81886	1784	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	516256	0	0
T1	35550	83	0	0
T2	783024	2260	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	80	0	0
T6	164468	3239	0	0
T7	693858	67	0	0
T8	76425	120	0	0
T9	557122	1010	0	0
T10	81886	330	0	0
T11	0	187	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	203533	0	0
T1	35550	67	0	0
T2	783024	943	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	76	0	0
T6	164468	776	0	0
T7	693858	57	0	0
T8	76425	119	0	0
T9	557122	892	0	0
T10	81886	232	0	0
T11	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	200352	0	0
GntImpliesValid_A	394058916	200352	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	200352	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2787257	0	0
ReadyAndValidImplyGrant_A	394058916	200352	0	0
ReqAndReadyImplyGrant_A	394058916	200352	0	0
ReqImpliesValid_A	394058916	524153	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	200352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2787257	0	0
T1	35550	358	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	15	0	0
T5	5715	78	0	0
T6	164468	1144	0	0
T7	693858	260	0	0
T8	76425	1012	0	0
T9	557122	7338	0	0
T10	81886	1772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	524153	0	0
T1	35550	53	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	16	0	0
T5	5715	83	0	0
T6	164468	166	0	0
T7	693858	57	0	0
T8	76425	137	0	0
T9	557122	1043	0	0
T10	81886	382	0	0
T11	0	153	0	0
T12	0	994	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	200352	0	0
T1	35550	45	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	80	0	0
T6	164468	143	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	949	0	0
T10	81886	244	0	0
T11	0	115	0	0
T12	0	498	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	195830	0	0
GntImpliesValid_A	394058916	195830	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	195830	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2733210	0	0
ReadyAndValidImplyGrant_A	394058916	195830	0	0
ReqAndReadyImplyGrant_A	394058916	195830	0	0
ReqImpliesValid_A	394058916	502687	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	195830	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2733210	0	0
T1	35550	527	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	14	0	0
T5	5715	87	0	0
T6	164468	2058	0	0
T7	693858	208	0	0
T8	76425	1118	0	0
T9	557122	6416	0	0
T10	81886	1897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	502687	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	104	0	0
T6	164468	5317	0	0
T7	693858	57	0	0
T8	76425	150	0	0
T9	557122	923	0	0
T10	81886	399	0	0
T11	0	144	0	0
T12	0	1035	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	195830	0	0
T1	35550	79	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	95	0	0
T6	164468	680	0	0
T7	693858	54	0	0
T8	76425	150	0	0
T9	557122	879	0	0
T10	81886	250	0	0
T11	0	111	0	0
T12	0	518	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	201512	0	0
GntImpliesValid_A	394058916	201512	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	201512	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2799561	0	0
ReadyAndValidImplyGrant_A	394058916	201512	0	0
ReqAndReadyImplyGrant_A	394058916	201512	0	0
ReqImpliesValid_A	394058916	545959	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	201512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2799561	0	0
T1	35550	494	0	0
T2	783024	3175	0	0
T3	53727	1	0	0
T4	2289	13	0	0
T5	5715	83	0	0
T6	164468	3098	0	0
T7	693858	239	0	0
T8	76425	910	0	0
T9	557122	6596	0	0
T10	81886	1736	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	545959	0	0
T1	35550	85	0	0
T2	783024	2350	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	92	0	0
T6	164468	8617	0	0
T7	693858	78	0	0
T8	76425	139	0	0
T9	557122	1009	0	0
T10	81886	331	0	0
T11	0	160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	201512	0	0
T1	35550	68	0	0
T2	783024	970	0	0
T3	53727	0	0	0
T4	2289	12	0	0
T5	5715	87	0	0
T6	164468	1089	0	0
T7	693858	57	0	0
T8	76425	126	0	0
T9	557122	896	0	0
T10	81886	229	0	0
T11	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	216883	0	0
GntImpliesValid_A	394058916	216883	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	216883	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2803351	0	0
ReadyAndValidImplyGrant_A	394058916	216883	0	0
ReqAndReadyImplyGrant_A	394058916	216883	0	0
ReqImpliesValid_A	394058916	579636	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	216883	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2803351	0	0
T1	35550	590	0	0
T2	783024	1	0	0
T3	53727	881	0	0
T4	2289	11	0	0
T5	5715	78	0	0
T6	164468	1182	0	0
T7	693858	279	0	0
T8	76425	757	0	0
T9	557122	15098	0	0
T10	81886	1677	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	579636	0	0
T1	35550	98	0	0
T2	783024	0	0	0
T3	53727	1811	0	0
T4	2289	10	0	0
T5	5715	81	0	0
T6	164468	141	0	0
T7	693858	67	0	0
T8	76425	101	0	0
T9	557122	6679	0	0
T10	81886	270	0	0
T11	0	156	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	216883	0	0
T1	35550	78	0	0
T2	783024	0	0	0
T3	53727	464	0	0
T4	2289	10	0	0
T5	5715	79	0	0
T6	164468	138	0	0
T7	693858	63	0	0
T8	76425	99	0	0
T9	557122	2280	0	0
T10	81886	227	0	0
T11	0	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	222490	0	0
GntImpliesValid_A	394058916	222490	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	222490	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2854902	0	0
ReadyAndValidImplyGrant_A	394058916	222490	0	0
ReqAndReadyImplyGrant_A	394058916	222490	0	0
ReqImpliesValid_A	394058916	561520	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	222490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2854902	0	0
T1	35550	892	0	0
T2	783024	1831	0	0
T3	53727	1	0	0
T4	2289	11	0	0
T5	5715	100	0	0
T6	164468	1348	0	0
T7	693858	274	0	0
T8	76425	984	0	0
T9	557122	16005	0	0
T10	81886	1545	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	561520	0	0
T1	35550	164	0	0
T2	783024	1270	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	111	0	0
T6	164468	203	0	0
T7	693858	77	0	0
T8	76425	141	0	0
T9	557122	7748	0	0
T10	81886	286	0	0
T11	0	235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	222490	0	0
T1	35550	122	0	0
T2	783024	536	0	0
T3	53727	0	0	0
T4	2289	10	0	0
T5	5715	105	0	0
T6	164468	174	0	0
T7	693858	65	0	0
T8	76425	124	0	0
T9	557122	2495	0	0
T10	81886	212	0	0
T11	0	181	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	204955	0	0
GntImpliesValid_A	394058916	204955	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	204955	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2807887	0	0
ReadyAndValidImplyGrant_A	394058916	204955	0	0
ReqAndReadyImplyGrant_A	394058916	204955	0	0
ReqImpliesValid_A	394058916	535975	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	204955	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2807887	0	0
T1	35550	631	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	12	0	0
T5	5715	72	0	0
T6	164468	1011	0	0
T7	693858	278	0	0
T8	76425	810	0	0
T9	557122	12133	0	0
T10	81886	1853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	535975	0	0
T1	35550	120	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	77	0	0
T6	164468	158	0	0
T7	693858	64	0	0
T8	76425	114	0	0
T9	557122	3279	0	0
T10	81886	311	0	0
T11	0	133	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	204955	0	0
T1	35550	89	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	11	0	0
T5	5715	74	0	0
T6	164468	140	0	0
T7	693858	55	0	0
T8	76425	104	0	0
T9	557122	1898	0	0
T10	81886	232	0	0
T11	0	110	0	0
T13	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	199565	0	0
GntImpliesValid_A	394058916	199565	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	199565	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2760420	0	0
ReadyAndValidImplyGrant_A	394058916	199565	0	0
ReqAndReadyImplyGrant_A	394058916	199565	0	0
ReqImpliesValid_A	394058916	512303	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	199565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2760420	0	0
T1	35550	421	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	15	0	0
T5	5715	74	0	0
T6	164468	1367	0	0
T7	693858	210	0	0
T8	76425	830	0	0
T9	557122	6853	0	0
T10	81886	1756	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	512303	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	83	0	0
T6	164468	179	0	0
T7	693858	52	0	0
T8	76425	118	0	0
T9	557122	1032	0	0
T10	81886	325	0	0
T11	0	157	0	0
T13	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	199565	0	0
T1	35550	65	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	14	0	0
T5	5715	78	0	0
T6	164468	169	0	0
T7	693858	47	0	0
T8	76425	118	0	0
T9	557122	910	0	0
T10	81886	236	0	0
T11	0	116	0	0
T13	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	202731	0	0
GntImpliesValid_A	394058916	202731	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	202731	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2813357	0	0
ReadyAndValidImplyGrant_A	394058916	202731	0	0
ReqAndReadyImplyGrant_A	394058916	202731	0	0
ReqImpliesValid_A	394058916	514323	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	202731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2813357	0	0
T1	35550	547	0	0
T2	783024	1306	0	0
T3	53727	1	0	0
T4	2289	10	0	0
T5	5715	70	0	0
T6	164468	1173	0	0
T7	693858	251	0	0
T8	76425	870	0	0
T9	557122	7453	0	0
T10	81886	1980	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	514323	0	0
T1	35550	67	0	0
T2	783024	1098	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	85	0	0
T6	164468	205	0	0
T7	693858	64	0	0
T8	76425	124	0	0
T9	557122	1061	0	0
T10	81886	306	0	0
T11	0	162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	202731	0	0
T1	35550	67	0	0
T2	783024	411	0	0
T3	53727	0	0	0
T4	2289	9	0	0
T5	5715	77	0	0
T6	164468	155	0	0
T7	693858	59	0	0
T8	76425	113	0	0
T9	557122	956	0	0
T10	81886	246	0	0
T11	0	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	206195	0	0
GntImpliesValid_A	394058916	206195	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	206195	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2797729	0	0
ReadyAndValidImplyGrant_A	394058916	206195	0	0
ReqAndReadyImplyGrant_A	394058916	206195	0	0
ReqImpliesValid_A	394058916	561056	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	206195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2797729	0	0
T1	35550	436	0	0
T2	783024	3500	0	0
T3	53727	1352	0	0
T4	2289	12	0	0
T5	5715	70	0	0
T6	164468	1753	0	0
T7	693858	220	0	0
T8	76425	922	0	0
T9	557122	9685	0	0
T10	81886	1654	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	561056	0	0
T1	35550	85	0	0
T2	783024	2492	0	0
T3	53727	9233	0	0
T4	2289	11	0	0
T5	5715	77	0	0
T6	164468	352	0	0
T7	693858	60	0	0
T8	76425	125	0	0
T9	557122	3315	0	0
T10	81886	346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	206195	0	0
T1	35550	69	0	0
T2	783024	1091	0	0
T3	53727	958	0	0
T4	2289	11	0	0
T5	5715	73	0	0
T6	164468	241	0	0
T7	693858	56	0	0
T8	76425	125	0	0
T9	557122	1378	0	0
T10	81886	229	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	205961	0	0
GntImpliesValid_A	394058916	205961	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	205961	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	2724161	0	0
ReadyAndValidImplyGrant_A	394058916	205961	0	0
ReqAndReadyImplyGrant_A	394058916	205961	0	0
ReqImpliesValid_A	394058916	525273	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	0	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	205961	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2724161	0	0
T1	35550	470	0	0
T2	783024	1	0	0
T3	53727	1	0	0
T4	2289	12	0	0
T5	5715	70	0	0
T6	164468	6402	0	0
T7	693858	184	0	0
T8	76425	905	0	0
T9	557122	9988	0	0
T10	81886	1584	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	525273	0	0
T1	35550	86	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	15	0	0
T5	5715	81	0	0
T6	164468	5560	0	0
T7	693858	59	0	0
T8	76425	122	0	0
T9	557122	2728	0	0
T10	81886	341	0	0
T11	0	147	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	877

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	205961	0	0
T1	35550	63	0	0
T2	783024	0	0	0
T3	53727	0	0	0
T4	2289	13	0	0
T5	5715	75	0	0
T6	164468	1189	0	0
T7	693858	48	0	0
T8	76425	120	0	0
T9	557122	1372	0	0
T10	81886	233	0	0
T11	0	109	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	834039	0	0
GntImpliesValid_A	394058916	834039	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	834039	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	10331100	0	0
ReadyAndValidImplyGrant_A	394058916	834039	0	0
ReqAndReadyImplyGrant_A	394058916	834039	0	0
ReqImpliesValid_A	394058916	2156888	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	19355	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	834039	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	10331100	0	0
T1	35550	1874	0	0
T2	783024	3278	0	0
T3	53727	2973	0	0
T4	2289	1	0	0
T5	5715	1	0	0
T6	164468	7747	0	0
T7	693858	903	0	0
T8	76425	3495	0	0
T9	557122	33492	0	0
T10	81886	5705	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	2156888	0	0
T1	35550	498	0	0
T2	783024	1247	0	0
T3	53727	751	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1823	0	0
T7	693858	336	0	0
T8	76425	593	0	0
T9	557122	7383	0	0
T10	81886	1528	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	19355	0	877
T5	5715	10	0	1
T6	164468	0	0	1
T7	693858	0	0	1
T8	76425	0	0	1
T9	557122	1	0	1
T10	81886	0	0	1
T11	52000	0	0	1
T12	12482	0	0	1
T13	1764	0	0	1
T16	0	12	0	0
T17	0	14	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	25	0	0
T23	0	6	0	0
T24	0	8	0	0
T25	541282	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	834039	0	0
T1	35550	307	0	0
T2	783024	991	0	0
T3	53727	454	0	0
T4	2289	59	0	0
T5	5715	298	0	0
T6	164468	1257	0	0
T7	693858	271	0	0
T8	76425	510	0	0
T9	557122	5115	0	0
T10	81886	906	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394058916	393937833	0	0
CheckNGreaterZero_A	877	877	0	0
GntImpliesReady_A	394058916	820834	0	0
GntImpliesValid_A	394058916	820834	0	0
GrantKnown_A	394058916	393937833	0	0
IdxKnown_A	394058916	393937833	0	0
IndexIsCorrect_A	394058916	820834	0	0
LockArbDecision_A	394058916	0	0	0
NoReadyValidNoGrant_A	394058916	330502727	0	0
ReadyAndValidImplyGrant_A	394058916	820834	0	0
ReqAndReadyImplyGrant_A	394058916	820834	0	0
ReqImpliesValid_A	394058916	12084412	0	0
ReqStaysHighUntilGranted0_M	394058916	0	0	0
RoundRobin_A	394058916	18056	0	877
ValidKnown_A	394058916	393937833	0	0
gen_data_port_assertion.DataFlow_A	394058916	820834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	877	877	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	330502727	0	0
T1	35550	30416	0	0
T2	783024	651245	0	0
T3	53727	44617	0	0
T4	2289	1	0	0
T5	5715	1	0	0
T6	164468	139981	0	0
T7	693858	577033	0	0
T8	76425	65664	0	0
T9	557122	470338	0	0
T10	81886	68111	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	12084412	0	0
T1	35550	2110	0	0
T2	783024	11973	0	0
T3	53727	3379	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	10617	0	0
T7	693858	1113	0	0
T8	76425	4176	0	0
T9	557122	40987	0	0
T10	81886	6991	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	18056	0	877
T1	35550	1	0	1
T2	783024	23	0	1
T3	53727	0	0	1
T4	2289	0	0	1
T5	5715	9	0	1
T6	164468	0	0	1
T7	693858	0	0	1
T8	76425	0	0	1
T9	557122	3	0	1
T10	81886	0	0	1
T12	0	482	0	0
T14	0	1	0	0
T15	0	52	0	0
T16	0	20	0	0
T17	0	12	0	0
T18	0	306	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	393937833	0	0
T1	35550	35503	0	0
T2	783024	783015	0	0
T3	53727	53661	0	0
T4	2289	2258	0	0
T5	5715	5643	0	0
T6	164468	164211	0	0
T7	693858	693774	0	0
T8	76425	76398	0	0
T9	557122	557058	0	0
T10	81886	81743	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394058916	820834	0	0
T1	35550	271	0	0
T2	783024	2671	0	0
T3	53727	468	0	0
T4	2289	46	0	0
T5	5715	302	0	0
T6	164468	1265	0	0
T7	693858	243	0	0
T8	76425	505	0	0
T9	557122	4961	0	0
T10	81886	857	0	0