Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1463910	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

232365

1

T1

132

T2

67

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	574823	1			T1	322		T2	171		T3	60
values[0x0]	546144	1			T1	301		T2	154		T3	68
values[0x1]	575308	1			T1	304		T2	169		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1131244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

565031

1

T1

309

T2

165

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26832	1			T1	34		T2	7		T4	18
valid_sources[0x01]	27055	1			T2	10		T3	2		T4	16
valid_sources[0x02]	26946	1			T1	47		T2	1		T3	2
valid_sources[0x03]	26299	1			T2	5		T3	1		T4	19
valid_sources[0x04]	26012	1			T2	12		T3	4		T4	19
valid_sources[0x05]	26042	1			T1	15		T2	12		T3	3
valid_sources[0x06]	26180	1			T1	30		T2	9		T3	5
valid_sources[0x07]	25786	1			T1	20		T2	14		T3	4
valid_sources[0x08]	28085	1			T2	10		T3	4		T4	27
valid_sources[0x09]	26367	1			T1	20		T2	4		T3	3
valid_sources[0x0a]	26458	1			T1	54		T2	11		T4	29
valid_sources[0x0b]	27069	1			T2	4		T3	1		T4	23
valid_sources[0x0c]	26826	1			T1	12		T2	9		T3	3
valid_sources[0x0d]	25983	1			T1	10		T2	8		T3	1
valid_sources[0x0e]	26151	1			T1	5		T2	7		T3	6
valid_sources[0x0f]	26962	1			T1	23		T2	4		T3	3
valid_sources[0x10]	26076	1			T1	6		T2	8		T3	2
valid_sources[0x11]	27504	1			T1	33		T2	9		T3	1
valid_sources[0x12]	25644	1			T2	5		T3	1		T4	22
valid_sources[0x13]	26342	1			T1	24		T2	5		T3	2
valid_sources[0x14]	27229	1			T1	40		T2	8		T3	3
valid_sources[0x15]	27699	1			T2	8		T3	2		T4	19
valid_sources[0x16]	26569	1			T1	6		T2	12		T3	1
valid_sources[0x17]	26703	1			T1	31		T2	14		T3	6
valid_sources[0x18]	26837	1			T2	3		T3	1		T4	22
valid_sources[0x19]	25378	1			T2	5		T3	2		T4	24
valid_sources[0x1a]	26132	1			T2	8		T3	8		T4	22
valid_sources[0x1b]	27635	1			T2	14		T3	1		T4	21
valid_sources[0x1c]	26394	1			T1	17		T2	16		T3	2
valid_sources[0x1d]	25703	1			T1	59		T2	6		T3	2
valid_sources[0x1e]	26460	1			T1	3		T2	11		T3	1
valid_sources[0x1f]	26275	1			T1	10		T2	5		T3	5
valid_sources[0x20]	27569	1			T1	8		T2	7		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24358

1

T1

9

T2

8

T3

3

values[0x0]

all_enables

biggest_size

183848

1

T1

113

T2

54

T3

18

values[0x1]

all_enables

biggest_size

24159

1

T1

10

T2

5

T4

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1482252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240688

1

T1

126

T2

65

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	588182	1			T1	311		T2	183		T3	41
values[0x0]	544083	1			T1	298		T2	146		T3	30
values[0x1]	590675	1			T1	329		T2	176		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1137877	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585063

1

T1

324

T2

166

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27240	1			T1	24		T2	18		T4	8
valid_sources[0x01]	27241	1			T1	4		T2	1		T4	19
valid_sources[0x02]	27877	1			T1	18		T2	9		T4	17
valid_sources[0x03]	27212	1			T1	1		T2	5		T4	16
valid_sources[0x04]	26688	1			T1	5		T2	15		T3	12
valid_sources[0x05]	27034	1			T1	20		T2	11		T4	23
valid_sources[0x06]	27440	1			T1	12		T2	14		T3	5
valid_sources[0x07]	25760	1			T1	17		T2	5		T3	2
valid_sources[0x08]	27139	1			T2	7		T4	21		T5	51
valid_sources[0x09]	27108	1			T1	8		T2	5		T4	12
valid_sources[0x0a]	26968	1			T1	19		T2	12		T4	16
valid_sources[0x0b]	26621	1			T1	22		T2	10		T3	2
valid_sources[0x0c]	26483	1			T1	15		T2	18		T3	3
valid_sources[0x0d]	27172	1			T1	6		T2	1		T4	16
valid_sources[0x0e]	27304	1			T1	21		T4	25		T5	42
valid_sources[0x0f]	26723	1			T1	41		T2	14		T4	14
valid_sources[0x10]	26726	1			T1	7		T2	8		T4	13
valid_sources[0x11]	26779	1			T1	19		T2	9		T3	15
valid_sources[0x12]	27108	1			T1	15		T2	2		T4	11
valid_sources[0x13]	26879	1			T1	23		T2	7		T4	16
valid_sources[0x14]	26366	1			T1	8		T2	25		T3	1
valid_sources[0x15]	26734	1			T1	13		T2	10		T4	8
valid_sources[0x16]	26642	1			T1	4		T2	13		T3	3
valid_sources[0x17]	26364	1			T1	4		T2	4		T4	20
valid_sources[0x18]	26387	1			T1	33		T2	7		T4	15
valid_sources[0x19]	26074	1			T1	17		T4	11		T5	39
valid_sources[0x1a]	26511	1			T1	17		T2	9		T3	5
valid_sources[0x1b]	27205	1			T1	17		T2	6		T3	1
valid_sources[0x1c]	26430	1			T1	22		T2	10		T4	11
valid_sources[0x1d]	27522	1			T1	22		T4	10		T5	38
valid_sources[0x1e]	27158	1			T1	23		T2	7		T4	12
valid_sources[0x1f]	27130	1			T1	3		T2	6		T4	18
valid_sources[0x20]	26550	1			T1	8		T2	10		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25209

1

T1

13

T2

10

T3

1

values[0x0]

all_enables

biggest_size

190261

1

T1

100

T2

51

T3

9

values[0x1]

all_enables

biggest_size

25218

1

T1

13

T2

4

T3

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1476548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

235690

1

T1

109

T2

61

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	580473	1			T1	254		T2	161		T3	49
values[0x0]	552003	1			T1	242		T2	151		T3	49
values[0x1]	579762	1			T1	277		T2	159		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1141697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

570541

1

T1

253

T2

163

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26370	1			T1	9		T2	6		T3	5
valid_sources[0x01]	26651	1			T1	15		T2	6		T4	12
valid_sources[0x02]	27497	1			T1	11		T2	7		T4	8
valid_sources[0x03]	27010	1			T1	13		T2	8		T3	5
valid_sources[0x04]	26484	1			T1	13		T2	3		T4	5
valid_sources[0x05]	27586	1			T1	9		T2	3		T3	11
valid_sources[0x06]	26424	1			T1	16		T2	15		T3	9
valid_sources[0x07]	25492	1			T1	9		T4	13		T5	58
valid_sources[0x08]	27010	1			T1	13		T2	4		T4	19
valid_sources[0x09]	26753	1			T1	15		T2	9		T3	2
valid_sources[0x0a]	26197	1			T1	12		T2	9		T3	3
valid_sources[0x0b]	26694	1			T1	15		T2	9		T4	18
valid_sources[0x0c]	27119	1			T1	13		T2	3		T4	12
valid_sources[0x0d]	26215	1			T1	10		T2	12		T3	6
valid_sources[0x0e]	26997	1			T1	12		T2	10		T4	20
valid_sources[0x0f]	27170	1			T1	16		T2	12		T4	7
valid_sources[0x10]	26908	1			T1	14		T2	5		T4	9
valid_sources[0x11]	27747	1			T1	10		T2	16		T3	6
valid_sources[0x12]	27415	1			T1	17		T2	8		T3	2
valid_sources[0x13]	26818	1			T1	16		T2	11		T3	3
valid_sources[0x14]	27026	1			T1	16		T2	5		T4	18
valid_sources[0x15]	26949	1			T1	11		T2	19		T4	19
valid_sources[0x16]	27183	1			T1	8		T2	1		T4	12
valid_sources[0x17]	26176	1			T1	9		T2	4		T3	21
valid_sources[0x18]	26718	1			T1	11		T2	7		T3	3
valid_sources[0x19]	26283	1			T1	9		T2	3		T3	1
valid_sources[0x1a]	26132	1			T1	9		T2	6		T4	21
valid_sources[0x1b]	26390	1			T1	12		T2	7		T3	5
valid_sources[0x1c]	26630	1			T1	4		T2	7		T4	18
valid_sources[0x1d]	26437	1			T1	12		T2	15		T4	11
valid_sources[0x1e]	26812	1			T1	11		T2	11		T3	4
valid_sources[0x1f]	27081	1			T1	8		T2	8		T3	4
valid_sources[0x20]	26922	1			T1	14		T2	16		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24781

1

T1

13

T2

6

T3

3

values[0x0]

all_enables

biggest_size

186530

1

T1

83

T2

51

T3

13

values[0x1]

all_enables

biggest_size

24379

1

T1

13

T2

4

T3

3