Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21072	21072	0	0
GntImpliesReady_A	2147483647	7185338	0	0
GntImpliesValid_A	2147483647	7185338	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7185338	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	436726893	0	0
ReadyAndValidImplyGrant_A	2147483647	7185338	0	0
ReqAndReadyImplyGrant_A	2147483647	7185338	0	0
ReqImpliesValid_A	2147483647	32771906	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38635	0	21072
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7185338	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99840	99384	0	0
T2	54000	53040	0	0
T3	216864	216168	0	0
T4	569448	567456	0	0
T5	1497432	1495824	0	0
T6	9422568	9422112	0	0
T7	1650528	1648848	0	0
T8	187104	186072	0	0
T9	1687272	1673592	0	0
T10	103800	103512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21072	21072	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99840	99384	0	0
T2	54000	53040	0	0
T3	216864	216168	0	0
T4	569448	567456	0	0
T5	1497432	1495824	0	0
T6	9422568	9422112	0	0
T7	1650528	1648848	0	0
T8	187104	186072	0	0
T9	1687272	1673592	0	0
T10	103800	103512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99840	99384	0	0
T2	54000	53040	0	0
T3	216864	216168	0	0
T4	569448	567456	0	0
T5	1497432	1495824	0	0
T6	9422568	9422112	0	0
T7	1650528	1648848	0	0
T8	187104	186072	0	0
T9	1687272	1673592	0	0
T10	103800	103512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	436726893	0	0
T1	99840	2853	0	0
T2	54000	209	0	0
T3	216864	10823	0	0
T4	569448	31813	0	0
T5	1497432	86068	0	0
T6	9422568	331803	0	0
T7	1650528	108096	0	0
T8	187104	5095	0	0
T9	1687272	48452	0	0
T10	103800	2874	0	0
T11	0	622667	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32771906	0	0
T1	99840	3036	0	0
T2	54000	2511	0	0
T3	216864	798	0	0
T4	569448	3049	0	0
T5	1497432	9331	0	0
T6	9422568	2171	0	0
T7	1650528	16644	0	0
T8	187104	5295	0	0
T9	1687272	41294	0	0
T10	103800	3202	0	0
T11	0	117403	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38635	0	21072
T1	8320	11	0	2
T2	4500	0	0	2
T3	18072	0	0	2
T4	47454	0	0	2
T5	124786	0	0	2
T6	785214	0	0	2
T7	137544	1	0	2
T8	15592	28	0	2
T9	140606	104	0	2
T10	8650	10	0	2
T11	0	2	0	0
T12	0	202	0	0
T13	0	1316	0	0
T14	0	2471	0	0
T15	0	19	0	0
T16	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	99840	99384	0	0
T2	54000	53040	0	0
T3	216864	216168	0	0
T4	569448	567456	0	0
T5	1497432	1495824	0	0
T6	9422568	9422112	0	0
T7	1650528	1648848	0	0
T8	187104	186072	0	0
T9	1687272	1673592	0	0
T10	103800	103512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7185338	0	0
T1	99840	2637	0	0
T2	54000	1470	0	0
T3	216864	430	0	0
T4	569448	1569	0	0
T5	1497432	4250	0	0
T6	9422568	1342	0	0
T7	1650528	7568	0	0
T8	187104	4513	0	0
T9	1687272	36968	0	0
T10	103800	2778	0	0
T11	0	3197	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	804172	0	0
GntImpliesValid_A	398648573	804172	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	804172	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	11823091	0	0
ReadyAndValidImplyGrant_A	398648573	804172	0	0
ReqAndReadyImplyGrant_A	398648573	804172	0	0
ReqImpliesValid_A	398648573	2324586	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	804172	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	11823091	0	0
T1	4160	216	0	0
T2	2250	92	0	0
T3	9036	298	0	0
T4	23727	1234	0	0
T5	62393	4107	0	0
T6	392607	547	0	0
T7	68772	6032	0	0
T8	7796	349	0	0
T9	70303	3388	0	0
T10	4325	228	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2324586	0	0
T1	4160	395	0	0
T2	2250	163	0	0
T3	9036	49	0	0
T4	23727	196	0	0
T5	62393	917	0	0
T6	392607	158	0	0
T7	68772	1442	0	0
T8	7796	600	0	0
T9	70303	4771	0	0
T10	4325	387	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	804172	0	0
T1	4160	305	0	0
T2	2250	127	0	0
T3	9036	39	0	0
T4	23727	169	0	0
T5	62393	524	0	0
T6	392607	124	0	0
T7	68772	798	0	0
T8	7796	474	0	0
T9	70303	4076	0	0
T10	4325	307	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	798630	0	0
GntImpliesValid_A	398648573	798630	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	798630	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	11667827	0	0
ReadyAndValidImplyGrant_A	398648573	798630	0	0
ReqAndReadyImplyGrant_A	398648573	798630	0	0
ReqImpliesValid_A	398648573	2300723	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	798630	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	11667827	0	0
T1	4160	231	0	0
T2	2250	93	0	0
T3	9036	311	0	0
T4	23727	1264	0	0
T5	62393	3292	0	0
T6	392607	557	0	0
T7	68772	5883	0	0
T8	7796	367	0	0
T9	70303	3366	0	0
T10	4325	220	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2300723	0	0
T1	4160	386	0	0
T2	2250	184	0	0
T3	9036	53	0	0
T4	23727	242	0	0
T5	62393	611	0	0
T6	392607	177	0	0
T7	68772	1353	0	0
T8	7796	644	0	0
T9	70303	4852	0	0
T10	4325	381	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	798630	0	0
T1	4160	308	0	0
T2	2250	138	0	0
T3	9036	48	0	0
T4	23727	169	0	0
T5	62393	460	0	0
T6	392607	136	0	0
T7	68772	800	0	0
T8	7796	505	0	0
T9	70303	4105	0	0
T10	4325	300	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	204531	0	0
GntImpliesValid_A	398648573	204531	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	204531	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2974396	0	0
ReadyAndValidImplyGrant_A	398648573	204531	0	0
ReqAndReadyImplyGrant_A	398648573	204531	0	0
ReqImpliesValid_A	398648573	582790	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	204531	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2974396	0	0
T1	4160	72	0	0
T2	2250	1	0	0
T3	9036	123	0	0
T4	23727	377	0	0
T5	62393	663	0	0
T6	392607	182	0	0
T7	68772	1671	0	0
T8	7796	118	0	0
T9	70303	992	0	0
T10	4325	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	582790	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	27	0	0
T4	23727	59	0	0
T5	62393	159	0	0
T6	392607	51	0	0
T7	68772	282	0	0
T8	7796	125	0	0
T9	70303	1066	0	0
T10	4325	77	0	0
T11	0	3308	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204531	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	49	0	0
T5	62393	100	0	0
T6	392607	48	0	0
T7	68772	216	0	0
T8	7796	121	0	0
T9	70303	1025	0	0
T10	4325	70	0	0
T11	0	177	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	189312	0	0
GntImpliesValid_A	398648573	189312	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	189312	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2922021	0	0
ReadyAndValidImplyGrant_A	398648573	189312	0	0
ReqAndReadyImplyGrant_A	398648573	189312	0	0
ReqImpliesValid_A	398648573	528691	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	189312	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2922021	0	0
T1	4160	72	0	0
T2	2250	1	0	0
T3	9036	81	0	0
T4	23727	388	0	0
T5	62393	750	0	0
T6	392607	108	0	0
T7	68772	1714	0	0
T8	7796	92	0	0
T9	70303	960	0	0
T10	4325	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	528691	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	24	0	0
T4	23727	54	0	0
T5	62393	140	0	0
T6	392607	30	0	0
T7	68772	343	0	0
T8	7796	103	0	0
T9	70303	1009	0	0
T10	4325	83	0	0
T11	0	3763	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	189312	0	0
T1	4160	75	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	45	0	0
T5	62393	107	0	0
T6	392607	27	0	0
T7	68772	218	0	0
T8	7796	97	0	0
T9	70303	981	0	0
T10	4325	78	0	0
T11	0	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	194651	0	0
GntImpliesValid_A	398648573	194651	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	194651	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	4484354	0	0
ReadyAndValidImplyGrant_A	398648573	194651	0	0
ReqAndReadyImplyGrant_A	398648573	194651	0	0
ReqImpliesValid_A	398648573	955931	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	194651	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	4484354	0	0
T1	4160	232	0	0
T2	2250	0	0	0
T3	9036	90	0	0
T4	23727	457	0	0
T5	62393	1396	0	0
T6	392607	236	0	0
T7	68772	2166	0	0
T8	7796	614	0	0
T9	70303	5204	0	0
T10	4325	281	0	0
T11	0	164671	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	955931	0	0
T1	4160	92	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	168	0	0
T6	392607	59	0	0
T7	68772	308	0	0
T8	7796	220	0	0
T9	70303	1362	0	0
T10	4325	127	0	0
T11	0	19077	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194651	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	12	0	0
T4	23727	39	0	0
T5	62393	126	0	0
T6	392607	46	0	0
T7	68772	228	0	0
T8	7796	140	0	0
T9	70303	969	0	0
T10	4325	84	0	0
T11	0	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	190339	0	0
GntImpliesValid_A	398648573	190339	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	190339	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	5307393	0	0
ReadyAndValidImplyGrant_A	398648573	190339	0	0
ReqAndReadyImplyGrant_A	398648573	190339	0	0
ReqImpliesValid_A	398648573	1089586	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	190339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	5307393	0	0
T1	4160	451	0	0
T2	2250	0	0	0
T3	9036	124	0	0
T4	23727	651	0	0
T5	62393	1594	0	0
T6	392607	275	0	0
T7	68772	3299	0	0
T8	7796	472	0	0
T9	70303	8564	0	0
T10	4325	266	0	0
T11	0	266828	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	1089586	0	0
T1	4160	127	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	111	0	0
T5	62393	179	0	0
T6	392607	49	0	0
T7	68772	448	0	0
T8	7796	179	0	0
T9	70303	1824	0	0
T10	4325	126	0	0
T11	0	32772	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	190339	0	0
T1	4160	65	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	51	0	0
T5	62393	111	0	0
T6	392607	39	0	0
T7	68772	210	0	0
T8	7796	114	0	0
T9	70303	999	0	0
T10	4325	77	0	0
T11	0	169	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	200717	0	0
GntImpliesValid_A	398648573	200717	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	200717	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	4909914	0	0
ReadyAndValidImplyGrant_A	398648573	200717	0	0
ReqAndReadyImplyGrant_A	398648573	200717	0	0
ReqImpliesValid_A	398648573	1025306	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	200717	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	4909914	0	0
T1	4160	275	0	0
T2	2250	0	0	0
T3	9036	97	0	0
T4	23727	415	0	0
T5	62393	1493	0	0
T6	392607	557	0	0
T7	68772	3336	0	0
T8	7796	706	0	0
T9	70303	7170	0	0
T10	4325	376	0	0
T11	0	114339	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	1025306	0	0
T1	4160	121	0	0
T2	2250	0	0	0
T3	9036	40	0	0
T4	23727	36	0	0
T5	62393	229	0	0
T6	392607	75	0	0
T7	68772	526	0	0
T8	7796	329	0	0
T9	70303	1485	0	0
T10	4325	140	0	0
T11	0	5069	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200717	0	0
T1	4160	79	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	36	0	0
T5	62393	111	0	0
T6	392607	42	0	0
T7	68772	223	0	0
T8	7796	144	0	0
T9	70303	1008	0	0
T10	4325	101	0	0
T11	0	168	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	194615	0	0
GntImpliesValid_A	398648573	194615	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	194615	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	4807382	0	0
ReadyAndValidImplyGrant_A	398648573	194615	0	0
ReqAndReadyImplyGrant_A	398648573	194615	0	0
ReqImpliesValid_A	398648573	1013278	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	194615	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	4807382	0	0
T1	4160	358	0	0
T2	2250	0	0	0
T3	9036	71	0	0
T4	23727	576	0	0
T5	62393	3715	0	0
T6	392607	168	0	0
T7	68772	2283	0	0
T8	7796	656	0	0
T9	70303	4936	0	0
T10	4325	341	0	0
T11	0	76829	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	1013278	0	0
T1	4160	139	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	49	0	0
T5	62393	430	0	0
T6	392607	38	0	0
T7	68772	363	0	0
T8	7796	202	0	0
T9	70303	1300	0	0
T10	4325	146	0	0
T11	0	3632	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	194615	0	0
T1	4160	93	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	40	0	0
T5	62393	138	0	0
T6	392607	38	0	0
T7	68772	240	0	0
T8	7796	120	0	0
T9	70303	970	0	0
T10	4325	92	0	0
T11	0	184	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	204089	0	0
GntImpliesValid_A	398648573	204089	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	204089	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2873232	0	0
ReadyAndValidImplyGrant_A	398648573	204089	0	0
ReqAndReadyImplyGrant_A	398648573	204089	0	0
ReqImpliesValid_A	398648573	529891	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	204089	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2873232	0	0
T1	4160	67	0	0
T2	2250	1	0	0
T3	9036	211	0	0
T4	23727	379	0	0
T5	62393	780	0	0
T6	392607	167	0	0
T7	68772	1544	0	0
T8	7796	97	0	0
T9	70303	930	0	0
T10	4325	78	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	529891	0	0
T1	4160	72	0	0
T2	2250	0	0	0
T3	9036	23	0	0
T4	23727	58	0	0
T5	62393	120	0	0
T6	392607	45	0	0
T7	68772	325	0	0
T8	7796	110	0	0
T9	70303	982	0	0
T10	4325	87	0	0
T11	0	2306	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	204089	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	50	0	0
T5	62393	103	0	0
T6	392607	42	0	0
T7	68772	207	0	0
T8	7796	103	0	0
T9	70303	952	0	0
T10	4325	82	0	0
T11	0	183	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	200782	0	0
GntImpliesValid_A	398648573	200782	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	200782	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2954498	0	0
ReadyAndValidImplyGrant_A	398648573	200782	0	0
ReqAndReadyImplyGrant_A	398648573	200782	0	0
ReqImpliesValid_A	398648573	571070	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	200782	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2954498	0	0
T1	4160	64	0	0
T2	2250	2	0	0
T3	9036	66	0	0
T4	23727	257	0	0
T5	62393	894	0	0
T6	392607	161	0	0
T7	68772	1626	0	0
T8	7796	112	0	0
T9	70303	942	0	0
T10	4325	63	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	571070	0	0
T1	4160	79	0	0
T2	2250	1007	0	0
T3	9036	6	0	0
T4	23727	43	0	0
T5	62393	144	0	0
T6	392607	40	0	0
T7	68772	271	0	0
T8	7796	131	0	0
T9	70303	990	0	0
T10	4325	66	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	200782	0	0
T1	4160	71	0	0
T2	2250	504	0	0
T3	9036	6	0	0
T4	23727	35	0	0
T5	62393	116	0	0
T6	392607	38	0	0
T7	68772	213	0	0
T8	7796	121	0	0
T9	70303	962	0	0
T10	4325	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	207546	0	0
GntImpliesValid_A	398648573	207546	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	207546	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2961152	0	0
ReadyAndValidImplyGrant_A	398648573	207546	0	0
ReqAndReadyImplyGrant_A	398648573	207546	0	0
ReqImpliesValid_A	398648573	583510	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	207546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2961152	0	0
T1	4160	76	0	0
T2	2250	1	0	0
T3	9036	185	0	0
T4	23727	370	0	0
T5	62393	779	0	0
T6	392607	182	0	0
T7	68772	1743	0	0
T8	7796	128	0	0
T9	70303	901	0	0
T10	4325	83	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	583510	0	0
T1	4160	85	0	0
T2	2250	0	0	0
T3	9036	25	0	0
T4	23727	68	0	0
T5	62393	127	0	0
T6	392607	61	0	0
T7	68772	337	0	0
T8	7796	135	0	0
T9	70303	954	0	0
T10	4325	90	0	0
T11	0	3857	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	207546	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	22	0	0
T4	23727	48	0	0
T5	62393	106	0	0
T6	392607	51	0	0
T7	68772	236	0	0
T8	7796	131	0	0
T9	70303	924	0	0
T10	4325	86	0	0
T11	0	180	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	196776	0	0
GntImpliesValid_A	398648573	196776	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	196776	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2907985	0	0
ReadyAndValidImplyGrant_A	398648573	196776	0	0
ReqAndReadyImplyGrant_A	398648573	196776	0	0
ReqImpliesValid_A	398648573	553738	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	196776	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2907985	0	0
T1	4160	75	0	0
T2	2250	1	0	0
T3	9036	81	0	0
T4	23727	422	0	0
T5	62393	749	0	0
T6	392607	141	0	0
T7	68772	1602	0	0
T8	7796	138	0	0
T9	70303	953	0	0
T10	4325	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	553738	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	73	0	0
T5	62393	154	0	0
T6	392607	31	0	0
T7	68772	318	0	0
T8	7796	155	0	0
T9	70303	997	0	0
T10	4325	81	0	0
T11	0	2674	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196776	0	0
T1	4160	77	0	0
T2	2250	0	0	0
T3	9036	11	0	0
T4	23727	54	0	0
T5	62393	114	0	0
T6	392607	31	0	0
T7	68772	220	0	0
T8	7796	146	0	0
T9	70303	971	0	0
T10	4325	75	0	0
T11	0	177	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	211185	0	0
GntImpliesValid_A	398648573	211185	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	211185	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2932024	0	0
ReadyAndValidImplyGrant_A	398648573	211185	0	0
ReqAndReadyImplyGrant_A	398648573	211185	0	0
ReqImpliesValid_A	398648573	600384	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	211185	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2932024	0	0
T1	4160	64	0	0
T2	2250	1	0	0
T3	9036	84	0	0
T4	23727	302	0	0
T5	62393	872	0	0
T6	392607	132	0	0
T7	68772	1380	0	0
T8	7796	125	0	0
T9	70303	1048	0	0
T10	4325	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	600384	0	0
T1	4160	73	0	0
T2	2250	0	0	0
T3	9036	18	0	0
T4	23727	47	0	0
T5	62393	125	0	0
T6	392607	34	0	0
T7	68772	269	0	0
T8	7796	138	0	0
T9	70303	1446	0	0
T10	4325	72	0	0
T11	0	2424	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	211185	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	114	0	0
T6	392607	33	0	0
T7	68772	183	0	0
T8	7796	131	0	0
T9	70303	1243	0	0
T10	4325	65	0	0
T11	0	142	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	193068	0	0
GntImpliesValid_A	398648573	193068	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	193068	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2988222	0	0
ReadyAndValidImplyGrant_A	398648573	193068	0	0
ReqAndReadyImplyGrant_A	398648573	193068	0	0
ReqImpliesValid_A	398648573	530208	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	193068	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2988222	0	0
T1	4160	77	0	0
T2	2250	1	0	0
T3	9036	129	0	0
T4	23727	396	0	0
T5	62393	899	0	0
T6	392607	128	0	0
T7	68772	1502	0	0
T8	7796	116	0	0
T9	70303	976	0	0
T10	4325	69	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	530208	0	0
T1	4160	84	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	59	0	0
T5	62393	144	0	0
T6	392607	47	0	0
T7	68772	234	0	0
T8	7796	127	0	0
T9	70303	1042	0	0
T10	4325	76	0	0
T11	0	4576	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193068	0	0
T1	4160	80	0	0
T2	2250	0	0	0
T3	9036	17	0	0
T4	23727	49	0	0
T5	62393	108	0	0
T6	392607	33	0	0
T7	68772	198	0	0
T8	7796	121	0	0
T9	70303	1005	0	0
T10	4325	72	0	0
T11	0	177	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	196088	0	0
GntImpliesValid_A	398648573	196088	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	196088	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2973734	0	0
ReadyAndValidImplyGrant_A	398648573	196088	0	0
ReqAndReadyImplyGrant_A	398648573	196088	0	0
ReqImpliesValid_A	398648573	556292	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	196088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2973734	0	0
T1	4160	75	0	0
T2	2250	1	0	0
T3	9036	102	0	0
T4	23727	307	0	0
T5	62393	749	0	0
T6	392607	108	0	0
T7	68772	1328	0	0
T8	7796	128	0	0
T9	70303	1279	0	0
T10	4325	82	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	556292	0	0
T1	4160	90	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	40	0	0
T5	62393	121	0	0
T6	392607	55	0	0
T7	68772	251	0	0
T8	7796	133	0	0
T9	70303	1647	0	0
T10	4325	89	0	0
T11	0	3997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	196088	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	13	0	0
T4	23727	38	0	0
T5	62393	105	0	0
T6	392607	33	0	0
T7	68772	196	0	0
T8	7796	130	0	0
T9	70303	1459	0	0
T10	4325	85	0	0
T11	0	191	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	191053	0	0
GntImpliesValid_A	398648573	191053	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	191053	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2888842	0	0
ReadyAndValidImplyGrant_A	398648573	191053	0	0
ReqAndReadyImplyGrant_A	398648573	191053	0	0
ReqImpliesValid_A	398648573	467742	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	191053	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2888842	0	0
T1	4160	69	0	0
T2	2250	1	0	0
T3	9036	168	0	0
T4	23727	356	0	0
T5	62393	920	0	0
T6	392607	166	0	0
T7	68772	1581	0	0
T8	7796	131	0	0
T9	70303	956	0	0
T10	4325	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	467742	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	52	0	0
T5	62393	170	0	0
T6	392607	44	0	0
T7	68772	324	0	0
T8	7796	148	0	0
T9	70303	1014	0	0
T10	4325	81	0	0
T11	0	2941	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	191053	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	21	0	0
T4	23727	48	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	220	0	0
T8	7796	139	0	0
T9	70303	981	0	0
T10	4325	77	0	0
T11	0	164	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	217290	0	0
GntImpliesValid_A	398648573	217290	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	217290	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	3008022	0	0
ReadyAndValidImplyGrant_A	398648573	217290	0	0
ReqAndReadyImplyGrant_A	398648573	217290	0	0
ReqImpliesValid_A	398648573	577456	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	217290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	3008022	0	0
T1	4160	68	0	0
T2	2250	1	0	0
T3	9036	71	0	0
T4	23727	564	0	0
T5	62393	1433	0	0
T6	392607	173	0	0
T7	68772	1682	0	0
T8	7796	129	0	0
T9	70303	1143	0	0
T10	4325	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	577456	0	0
T1	4160	71	0	0
T2	2250	0	0	0
T3	9036	25	0	0
T4	23727	88	0	0
T5	62393	252	0	0
T6	392607	53	0	0
T7	68772	313	0	0
T8	7796	142	0	0
T9	70303	1277	0	0
T10	4325	88	0	0
T11	0	7881	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	217290	0	0
T1	4160	69	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	71	0	0
T5	62393	187	0	0
T6	392607	46	0	0
T7	68772	218	0	0
T8	7796	135	0	0
T9	70303	1206	0	0
T10	4325	80	0	0
T11	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	193500	0	0
GntImpliesValid_A	398648573	193500	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	193500	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2902472	0	0
ReadyAndValidImplyGrant_A	398648573	193500	0	0
ReqAndReadyImplyGrant_A	398648573	193500	0	0
ReqImpliesValid_A	398648573	548398	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	193500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2902472	0	0
T1	4160	67	0	0
T2	2250	1	0	0
T3	9036	97	0	0
T4	23727	284	0	0
T5	62393	899	0	0
T6	392607	149	0	0
T7	68772	1536	0	0
T8	7796	127	0	0
T9	70303	931	0	0
T10	4325	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	548398	0	0
T1	4160	82	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	48	0	0
T5	62393	195	0	0
T6	392607	53	0	0
T7	68772	247	0	0
T8	7796	138	0	0
T9	70303	995	0	0
T10	4325	108	0	0
T11	0	6081	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193500	0	0
T1	4160	74	0	0
T2	2250	0	0	0
T3	9036	10	0	0
T4	23727	42	0	0
T5	62393	126	0	0
T6	392607	39	0	0
T7	68772	212	0	0
T8	7796	132	0	0
T9	70303	959	0	0
T10	4325	101	0	0
T11	0	213	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	202830	0	0
GntImpliesValid_A	398648573	202830	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	202830	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2969862	0	0
ReadyAndValidImplyGrant_A	398648573	202830	0	0
ReqAndReadyImplyGrant_A	398648573	202830	0	0
ReqImpliesValid_A	398648573	577193	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	202830	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2969862	0	0
T1	4160	59	0	0
T2	2250	6	0	0
T3	9036	74	0	0
T4	23727	277	0	0
T5	62393	888	0	0
T6	392607	175	0	0
T7	68772	1708	0	0
T8	7796	135	0	0
T9	70303	945	0	0
T10	4325	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	577193	0	0
T1	4160	62	0	0
T2	2250	917	0	0
T3	9036	11	0	0
T4	23727	48	0	0
T5	62393	164	0	0
T6	392607	59	0	0
T7	68772	280	0	0
T8	7796	140	0	0
T9	70303	983	0	0
T10	4325	65	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202830	0	0
T1	4160	60	0	0
T2	2250	461	0	0
T3	9036	11	0	0
T4	23727	40	0	0
T5	62393	115	0	0
T6	392607	45	0	0
T7	68772	219	0	0
T8	7796	137	0	0
T9	70303	960	0	0
T10	4325	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	193078	0	0
GntImpliesValid_A	398648573	193078	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	193078	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2939417	0	0
ReadyAndValidImplyGrant_A	398648573	193078	0	0
ReqAndReadyImplyGrant_A	398648573	193078	0	0
ReqImpliesValid_A	398648573	510196	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	193078	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2939417	0	0
T1	4160	63	0	0
T2	2250	1	0	0
T3	9036	115	0	0
T4	23727	329	0	0
T5	62393	668	0	0
T6	392607	150	0	0
T7	68772	1587	0	0
T8	7796	126	0	0
T9	70303	951	0	0
T10	4325	60	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	510196	0	0
T1	4160	64	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	44	0	0
T5	62393	132	0	0
T6	392607	50	0	0
T7	68772	284	0	0
T8	7796	143	0	0
T9	70303	995	0	0
T10	4325	65	0	0
T11	0	5394	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	193078	0	0
T1	4160	63	0	0
T2	2250	0	0	0
T3	9036	16	0	0
T4	23727	43	0	0
T5	62393	100	0	0
T6	392607	37	0	0
T7	68772	215	0	0
T8	7796	134	0	0
T9	70303	969	0	0
T10	4325	62	0	0
T11	0	188	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	202480	0	0
GntImpliesValid_A	398648573	202480	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	202480	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2950062	0	0
ReadyAndValidImplyGrant_A	398648573	202480	0	0
ReqAndReadyImplyGrant_A	398648573	202480	0	0
ReqImpliesValid_A	398648573	537627	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	202480	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2950062	0	0
T1	4160	53	0	0
T2	2250	1	0	0
T3	9036	54	0	0
T4	23727	409	0	0
T5	62393	810	0	0
T6	392607	196	0	0
T7	68772	1826	0	0
T8	7796	117	0	0
T9	70303	1005	0	0
T10	4325	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	537627	0	0
T1	4160	54	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	70	0	0
T5	62393	144	0	0
T6	392607	67	0	0
T7	68772	306	0	0
T8	7796	126	0	0
T9	70303	1063	0	0
T10	4325	86	0	0
T11	0	6899	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	202480	0	0
T1	4160	53	0	0
T2	2250	0	0	0
T3	9036	9	0	0
T4	23727	51	0	0
T5	62393	110	0	0
T6	392607	44	0	0
T7	68772	230	0	0
T8	7796	121	0	0
T9	70303	1030	0	0
T10	4325	82	0	0
T11	0	191	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	197508	0	0
GntImpliesValid_A	398648573	197508	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	197508	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	2880301	0	0
ReadyAndValidImplyGrant_A	398648573	197508	0	0
ReqAndReadyImplyGrant_A	398648573	197508	0	0
ReqImpliesValid_A	398648573	503933	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	0	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	197508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2880301	0	0
T1	4160	67	0	0
T2	2250	1	0	0
T3	9036	24	0	0
T4	23727	379	0	0
T5	62393	859	0	0
T6	392607	177	0	0
T7	68772	1454	0	0
T8	7796	110	0	0
T9	70303	903	0	0
T10	4325	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	503933	0	0
T1	4160	70	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	46	0	0
T5	62393	217	0	0
T6	392607	41	0	0
T7	68772	342	0	0
T8	7796	129	0	0
T9	70303	947	0	0
T10	4325	86	0	0
T11	0	752	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	878

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	197508	0	0
T1	4160	68	0	0
T2	2250	0	0	0
T3	9036	3	0	0
T4	23727	43	0	0
T5	62393	111	0	0
T6	392607	36	0	0
T7	68772	211	0	0
T8	7796	119	0	0
T9	70303	921	0	0
T10	4325	79	0	0
T11	0	161	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	799900	0	0
GntImpliesValid_A	398648573	799900	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	799900	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	11169777	0	0
ReadyAndValidImplyGrant_A	398648573	799900	0	0
ReqAndReadyImplyGrant_A	398648573	799900	0	0
ReqImpliesValid_A	398648573	2212328	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	14301	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	799900	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	11169777	0	0
T1	4160	1	0	0
T2	2250	1	0	0
T3	9036	313	0	0
T4	23727	1066	0	0
T5	62393	3321	0	0
T6	392607	469	0	0
T7	68772	4775	0	0
T8	7796	1	0	0
T9	70303	8	0	0
T10	4325	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	2212328	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	56	0	0
T4	23727	207	0	0
T5	62393	674	0	0
T6	392607	194	0	0
T7	68772	1335	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	14301	0	878
T1	4160	3	0	1
T2	2250	0	0	1
T3	9036	0	0	1
T4	23727	0	0	1
T5	62393	0	0	1
T6	392607	0	0	1
T7	68772	1	0	1
T8	7796	16	0	1
T9	70303	49	0	1
T10	4325	3	0	1
T12	0	32	0	0
T13	0	483	0	0
T14	0	460	0	0
T15	0	6	0	0
T16	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	799900	0	0
T1	4160	296	0	0
T2	2250	115	0	0
T3	9036	43	0	0
T4	23727	163	0	0
T5	62393	472	0	0
T6	392607	146	0	0
T7	68772	835	0	0
T8	7796	498	0	0
T9	70303	4134	0	0
T10	4325	276	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398648573	398537951	0	0
CheckNGreaterZero_A	878	878	0	0
GntImpliesReady_A	398648573	801198	0	0
GntImpliesValid_A	398648573	801198	0	0
GrantKnown_A	398648573	398537951	0	0
IdxKnown_A	398648573	398537951	0	0
IndexIsCorrect_A	398648573	801198	0	0
LockArbDecision_A	398648573	0	0	0
NoReadyValidNoGrant_A	398648573	335530913	0	0
ReadyAndValidImplyGrant_A	398648573	801198	0	0
ReqAndReadyImplyGrant_A	398648573	801198	0	0
ReqImpliesValid_A	398648573	13091049	0	0
ReqStaysHighUntilGranted0_M	398648573	0	0	0
RoundRobin_A	398648573	24334	0	878
ValidKnown_A	398648573	398537951	0	0
gen_data_port_assertion.DataFlow_A	398648573	801198	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	878	878	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	335530913	0	0
T1	4160	1	0	0
T2	2250	1	0	0
T3	9036	7854	0	0
T4	23727	20354	0	0
T5	62393	53538	0	0
T6	392607	326499	0	0
T7	68772	54838	0	0
T8	7796	1	0	0
T9	70303	1	0	0
T10	4325	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	13091049	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	299	0	0
T4	23727	1272	0	0
T5	62393	3615	0	0
T6	392607	660	0	0
T7	68772	6143	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	24334	0	878
T1	4160	8	0	1
T2	2250	0	0	1
T3	9036	0	0	1
T4	23727	0	0	1
T5	62393	0	0	1
T6	392607	0	0	1
T7	68772	0	0	1
T8	7796	12	0	1
T9	70303	55	0	1
T10	4325	7	0	1
T11	0	2	0	0
T12	0	170	0	0
T13	0	833	0	0
T14	0	2011	0	0
T15	0	13	0	0
T16	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	398537951	0	0
T1	4160	4141	0	0
T2	2250	2210	0	0
T3	9036	9007	0	0
T4	23727	23644	0	0
T5	62393	62326	0	0
T6	392607	392588	0	0
T7	68772	68702	0	0
T8	7796	7753	0	0
T9	70303	69733	0	0
T10	4325	4313	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398648573	801198	0	0
T1	4160	286	0	0
T2	2250	125	0	0
T3	9036	43	0	0
T4	23727	154	0	0
T5	62393	460	0	0
T6	392607	149	0	0
T7	68772	822	0	0
T8	7796	500	0	0
T9	70303	4159	0	0
T10	4325	319	0	0