Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1534975 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244356 1 T1 228 T2 19 T3 1


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 604304 1 T1 608 T2 52 T3 8
values[0x0] 571168 1 T1 552 T2 51 T4 50
values[0x1] 603859 1 T1 549 T2 43 T3 6


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1186819 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 592512 1 T1 559 T2 50 T3 4


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29296 1 T1 26 T2 4 T5 100
valid_sources[0x01] 27498 1 T1 28 T5 80 T6 4
valid_sources[0x02] 28826 1 T1 21 T5 48 T6 6
valid_sources[0x03] 27390 1 T1 30 T2 3 T5 88
valid_sources[0x04] 28620 1 T1 32 T2 3 T3 1
valid_sources[0x05] 27742 1 T1 30 T2 4 T3 1
valid_sources[0x06] 27419 1 T1 25 T2 1 T5 108
valid_sources[0x07] 28891 1 T1 21 T2 4 T5 119
valid_sources[0x08] 28125 1 T1 24 T4 2 T5 119
valid_sources[0x09] 27549 1 T1 22 T2 2 T5 124
valid_sources[0x0a] 26781 1 T1 24 T2 1 T4 4
valid_sources[0x0b] 28009 1 T1 26 T2 1 T5 85
valid_sources[0x0c] 27079 1 T1 28 T2 2 T5 102
valid_sources[0x0d] 26986 1 T1 25 T4 3 T5 41
valid_sources[0x0e] 27626 1 T1 29 T2 2 T5 151
valid_sources[0x0f] 27325 1 T1 26 T2 4 T4 10
valid_sources[0x10] 27926 1 T1 28 T2 5 T5 66
valid_sources[0x11] 27903 1 T1 24 T2 3 T3 1
valid_sources[0x12] 28446 1 T1 28 T2 5 T4 2
valid_sources[0x13] 28603 1 T1 17 T2 3 T5 89
valid_sources[0x14] 26904 1 T1 33 T2 3 T4 2
valid_sources[0x15] 28512 1 T1 27 T5 130 T6 5
valid_sources[0x16] 27577 1 T1 23 T2 2 T5 127
valid_sources[0x17] 27246 1 T1 27 T2 1 T4 3
valid_sources[0x18] 27398 1 T1 27 T2 3 T5 88
valid_sources[0x19] 27357 1 T1 27 T2 4 T4 2
valid_sources[0x1a] 28818 1 T1 31 T3 1 T4 4
valid_sources[0x1b] 28687 1 T1 30 T2 6 T3 1
valid_sources[0x1c] 27158 1 T1 22 T2 5 T4 5
valid_sources[0x1d] 27843 1 T1 29 T2 4 T3 2
valid_sources[0x1e] 28634 1 T1 26 T2 2 T4 5
valid_sources[0x1f] 28149 1 T1 43 T2 3 T5 129
valid_sources[0x20] 26945 1 T1 34 T2 3 T5 77


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25890 1 T1 24 T2 2 T3 1
values[0x0] all_enables biggest_size 192627 1 T1 176 T2 17 T4 18
values[0x1] all_enables biggest_size 25839 1 T1 28 T4 1 T5 98


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1549011 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 251760 1 T1 232 T2 16 T3 4


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 617838 1 T1 589 T2 37 T3 11
values[0x0] 566166 1 T1 594 T2 49 T3 2
values[0x1] 616767 1 T1 626 T2 38 T3 17


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1188194 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 612577 1 T1 590 T2 41 T3 13


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28528 1 T1 30 T2 1 T4 8
valid_sources[0x01] 28021 1 T1 25 T2 2 T3 1
valid_sources[0x02] 28759 1 T1 20 T2 6 T4 7
valid_sources[0x03] 27913 1 T1 28 T2 4 T4 4
valid_sources[0x04] 27991 1 T1 16 T4 1 T5 113
valid_sources[0x05] 27728 1 T1 17 T3 2 T4 2
valid_sources[0x06] 28071 1 T1 16 T2 2 T3 1
valid_sources[0x07] 28076 1 T1 20 T2 5 T3 1
valid_sources[0x08] 28310 1 T1 30 T4 3 T5 113
valid_sources[0x09] 28402 1 T1 52 T2 1 T4 2
valid_sources[0x0a] 28141 1 T1 32 T2 1 T3 2
valid_sources[0x0b] 28225 1 T1 45 T2 1 T3 1
valid_sources[0x0c] 28311 1 T1 18 T2 4 T3 1
valid_sources[0x0d] 27134 1 T1 21 T2 2 T5 53
valid_sources[0x0e] 28444 1 T1 18 T4 2 T5 99
valid_sources[0x0f] 28457 1 T1 29 T2 1 T3 1
valid_sources[0x10] 27342 1 T1 41 T2 2 T3 2
valid_sources[0x11] 27380 1 T1 45 T2 7 T4 15
valid_sources[0x12] 28085 1 T1 25 T2 3 T4 1
valid_sources[0x13] 28214 1 T1 25 T4 3 T5 101
valid_sources[0x14] 28017 1 T1 20 T4 1 T5 128
valid_sources[0x15] 27810 1 T1 21 T3 1 T5 164
valid_sources[0x16] 28577 1 T1 28 T4 2 T5 99
valid_sources[0x17] 28574 1 T1 36 T4 5 T5 133
valid_sources[0x18] 28064 1 T1 38 T2 1 T5 82
valid_sources[0x19] 27912 1 T1 23 T2 3 T3 1
valid_sources[0x1a] 28369 1 T1 35 T4 2 T5 67
valid_sources[0x1b] 28340 1 T1 25 T5 97 T6 10
valid_sources[0x1c] 28154 1 T1 37 T2 3 T4 7
valid_sources[0x1d] 27863 1 T1 21 T4 8 T5 109
valid_sources[0x1e] 28703 1 T1 38 T2 4 T3 2
valid_sources[0x1f] 28597 1 T1 37 T4 6 T5 148
valid_sources[0x20] 28048 1 T1 16 T4 9 T5 82


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26504 1 T1 21 T3 2 T4 7
values[0x0] all_enables biggest_size 198885 1 T1 182 T2 15 T3 1
values[0x1] all_enables biggest_size 26371 1 T1 29 T2 1 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1546331 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 245919 1 T1 241 T2 24 T3 2


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 608757 1 T1 593 T2 43 T3 7
values[0x0] 574236 1 T1 557 T2 51 T4 47
values[0x1] 609257 1 T1 582 T2 44 T3 5


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1194979 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 597271 1 T1 582 T2 48 T3 3


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28592 1 T1 22 T2 1 T4 2
valid_sources[0x01] 27404 1 T1 34 T2 2 T4 5
valid_sources[0x02] 28819 1 T1 24 T2 1 T4 3
valid_sources[0x03] 27174 1 T1 24 T2 2 T4 1
valid_sources[0x04] 27650 1 T1 22 T2 2 T4 4
valid_sources[0x05] 27606 1 T1 29 T2 2 T3 2
valid_sources[0x06] 28609 1 T1 27 T2 1 T4 2
valid_sources[0x07] 28669 1 T1 29 T4 1 T5 157
valid_sources[0x08] 27929 1 T1 16 T2 2 T4 4
valid_sources[0x09] 28108 1 T1 20 T2 3 T3 2
valid_sources[0x0a] 27660 1 T1 28 T2 1 T5 142
valid_sources[0x0b] 27708 1 T1 30 T2 2 T3 1
valid_sources[0x0c] 27683 1 T1 32 T2 2 T4 2
valid_sources[0x0d] 27789 1 T1 24 T2 1 T4 1
valid_sources[0x0e] 29127 1 T1 35 T2 2 T5 84
valid_sources[0x0f] 28711 1 T1 24 T2 3 T4 3
valid_sources[0x10] 27624 1 T1 29 T2 5 T4 4
valid_sources[0x11] 27945 1 T1 28 T2 2 T4 4
valid_sources[0x12] 28776 1 T1 26 T2 2 T4 4
valid_sources[0x13] 27784 1 T1 26 T2 2 T4 3
valid_sources[0x14] 27788 1 T1 37 T2 2 T5 90
valid_sources[0x15] 27809 1 T1 29 T2 2 T4 4
valid_sources[0x16] 28447 1 T1 21 T2 1 T4 3
valid_sources[0x17] 28344 1 T1 23 T2 1 T4 1
valid_sources[0x18] 27432 1 T1 21 T2 2 T4 5
valid_sources[0x19] 27704 1 T1 19 T2 3 T4 4
valid_sources[0x1a] 27920 1 T1 28 T2 3 T3 1
valid_sources[0x1b] 28434 1 T1 33 T2 2 T4 5
valid_sources[0x1c] 27391 1 T1 31 T2 2 T5 64
valid_sources[0x1d] 28622 1 T1 29 T2 2 T3 1
valid_sources[0x1e] 29050 1 T1 22 T2 3 T4 4
valid_sources[0x1f] 27516 1 T1 32 T2 3 T5 113
valid_sources[0x20] 27458 1 T1 24 T2 1 T4 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26099 1 T1 26 T2 1 T3 1
values[0x0] all_enables biggest_size 193896 1 T1 198 T2 18 T4 22
values[0x1] all_enables biggest_size 25924 1 T1 17 T2 5 T3 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%