Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8155878	0	0
GntImpliesValid_A	2147483647	8155878	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8155878	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	439028112	0	0
ReadyAndValidImplyGrant_A	2147483647	8155878	0	0
ReqAndReadyImplyGrant_A	2147483647	8155878	0	0
ReqImpliesValid_A	2147483647	34100433	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46181	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8155878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6010752	6010584	0	0
T2	6532896	6531720	0	0
T3	294192	277440	0	0
T4	123864	119112	0	0
T5	904320	884256	0	0
T6	1029384	1025736	0	0
T7	13904784	13904736	0	0
T8	22155696	22155144	0	0
T9	37512	30576	0	0
T16	8520	7440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T16	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6010752	6010584	0	0
T2	6532896	6531720	0	0
T3	294192	277440	0	0
T4	123864	119112	0	0
T5	904320	884256	0	0
T6	1029384	1025736	0	0
T7	13904784	13904736	0	0
T8	22155696	22155144	0	0
T9	37512	30576	0	0
T16	8520	7440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6010752	6010584	0	0
T2	6532896	6531720	0	0
T3	294192	277440	0	0
T4	123864	119112	0	0
T5	904320	884256	0	0
T6	1029384	1025736	0	0
T7	13904784	13904736	0	0
T8	22155696	22155144	0	0
T9	37512	30576	0	0
T16	8520	7440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	439028112	0	0
T1	5259408	224316	0	0
T2	6532896	228416	0	0
T3	294192	16324	0	0
T4	123864	5277	0	0
T5	904320	18411	0	0
T6	1029384	25995	0	0
T7	13904784	519067	0	0
T8	22155696	1435463	0	0
T9	37512	1788	0	0
T10	80004	3048	0	0
T11	0	2618	0	0
T13	0	10649	0	0
T14	0	8741	0	0
T16	8520	293	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34100433	0	0
T1	1753136	15358	0	0
T2	6532896	710	0	0
T3	294192	1696	0	0
T4	123864	5125	0	0
T5	904320	20452	0	0
T6	1029384	21007	0	0
T7	13904784	31297	0	0
T8	22155696	127664	0	0
T9	37512	201	0	0
T10	453356	7140	0	0
T11	0	9988	0	0
T12	0	4814	0	0
T13	0	32466	0	0
T14	0	3536	0	0
T16	8520	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46181	0	21600
T1	500896	33	0	2
T2	544408	0	0	2
T3	24516	0	0	2
T4	10322	0	0	2
T5	75360	123	0	2
T6	85782	54	0	2
T7	1158732	42	0	2
T8	1846308	0	0	2
T9	3126	0	0	2
T11	0	1	0	0
T12	0	74	0	0
T13	0	505	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	710	0	0	2
T17	0	54	0	0
T18	0	16	0	0
T19	0	1	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6010752	6010584	0	0
T2	6532896	6531720	0	0
T3	294192	277440	0	0
T4	123864	119112	0	0
T5	904320	884256	0	0
T6	1029384	1025736	0	0
T7	13904784	13904736	0	0
T8	22155696	22155144	0	0
T9	37512	30576	0	0
T16	8520	7440	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8155878	0	0
T1	1753136	5250	0	0
T2	6532896	408	0	0
T3	294192	759	0	0
T4	123864	509	0	0
T5	904320	18336	0	0
T6	1029384	19296	0	0
T7	13904784	11930	0	0
T8	22155696	2249	0	0
T9	37512	97	0	0
T10	453356	3099	0	0
T11	0	4809	0	0
T12	0	499	0	0
T13	0	19316	0	0
T14	0	1989	0	0
T16	8520	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	912711	0	0
GntImpliesValid_A	408240284	912711	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	912711	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	11540558	0	0
ReadyAndValidImplyGrant_A	408240284	912711	0	0
ReqAndReadyImplyGrant_A	408240284	912711	0	0
ReqImpliesValid_A	408240284	2445931	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	912711	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	11540558	0	0
T1	250448	1129	0	0
T2	272204	155	0	0
T3	12258	829	0	0
T4	5161	406	0	0
T5	37680	1607	0	0
T6	42891	1858	0	0
T7	579366	2936	0	0
T8	923154	63615	0	0
T9	1563	84	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2445931	0	0
T1	250448	414	0	0
T2	272204	50	0	0
T3	12258	192	0	0
T4	5161	93	0	0
T5	37680	2101	0	0
T6	42891	2438	0	0
T7	579366	1007	0	0
T8	923154	9809	0	0
T9	1563	8	0	0
T10	0	684	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	912711	0	0
T1	250448	274	0	0
T2	272204	35	0	0
T3	12258	128	0	0
T4	5161	54	0	0
T5	37680	1848	0	0
T6	42891	2147	0	0
T7	579366	728	0	0
T8	923154	220	0	0
T9	1563	8	0	0
T10	0	319	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	913015	0	0
GntImpliesValid_A	408240284	913015	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	913015	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	11463833	0	0
ReadyAndValidImplyGrant_A	408240284	913015	0	0
ReqAndReadyImplyGrant_A	408240284	913015	0	0
ReqImpliesValid_A	408240284	2446090	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	913015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	11463833	0	0
T1	250448	1102	0	0
T2	272204	164	0	0
T3	12258	787	0	0
T4	5161	301	0	0
T5	37680	1807	0	0
T6	42891	1827	0	0
T7	579366	5299	0	0
T8	923154	76781	0	0
T9	1563	102	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2446090	0	0
T1	250448	356	0	0
T2	272204	52	0	0
T3	12258	190	0	0
T4	5161	56	0	0
T5	37680	2616	0	0
T6	42891	2371	0	0
T7	579366	2851	0	0
T8	923154	9395	0	0
T9	1563	23	0	0
T10	0	655	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	913015	0	0
T1	250448	265	0	0
T2	272204	39	0	0
T3	12258	117	0	0
T4	5161	51	0	0
T5	37680	2205	0	0
T6	42891	2098	0	0
T7	579366	1446	0	0
T8	923154	239	0	0
T9	1563	14	0	0
T10	0	345	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T5,T6,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	228394	0	0
GntImpliesValid_A	408240284	228394	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	228394	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2821979	0	0
ReadyAndValidImplyGrant_A	408240284	228394	0	0
ReqAndReadyImplyGrant_A	408240284	228394	0	0
ReqImpliesValid_A	408240284	604809	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	228394	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2821979	0	0
T1	250448	1	0	0
T2	272204	53	0	0
T3	12258	94	0	0
T4	5161	2	0	0
T5	37680	431	0	0
T6	42891	506	0	0
T7	579366	1	0	0
T8	923154	22101	0	0
T9	1563	33	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	604809	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	476	0	0
T6	42891	538	0	0
T7	579366	0	0	0
T8	923154	1460	0	0
T9	1563	4	0	0
T10	26668	140	0	0
T11	0	232	0	0
T13	0	1628	0	0
T14	0	292	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	228394	0	0
T2	272204	14	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	447	0	0
T6	42891	521	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	179	0	0
T13	0	1041	0	0
T14	0	156	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	234358	0	0
GntImpliesValid_A	408240284	234358	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	234358	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2796925	0	0
ReadyAndValidImplyGrant_A	408240284	234358	0	0
ReqAndReadyImplyGrant_A	408240284	234358	0	0
ReqImpliesValid_A	408240284	616877	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	234358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2796925	0	0
T1	250448	1	0	0
T2	272204	73	0	0
T3	12258	148	0	0
T4	5161	2	0	0
T5	37680	359	0	0
T6	42891	519	0	0
T7	579366	4696	0	0
T8	923154	21176	0	0
T9	1563	4	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	616877	0	0
T2	272204	52	0	0
T3	12258	35	0	0
T4	5161	0	0	0
T5	37680	356	0	0
T6	42891	573	0	0
T7	579366	3322	0	0
T8	923154	575	0	0
T9	1563	0	0	0
T10	26668	174	0	0
T11	0	1671	0	0
T13	0	3346	0	0
T14	0	171	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	234358	0	0
T2	272204	22	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	351	0	0
T6	42891	545	0	0
T7	579366	1433	0	0
T8	923154	68	0	0
T9	1563	0	0	0
T10	26668	108	0	0
T11	0	617	0	0
T13	0	1917	0	0
T14	0	129	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	217635	0	0
GntImpliesValid_A	408240284	217635	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	217635	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	3888622	0	0
ReadyAndValidImplyGrant_A	408240284	217635	0	0
ReqAndReadyImplyGrant_A	408240284	217635	0	0
ReqImpliesValid_A	408240284	1127988	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	217635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	3888622	0	0
T1	250448	6355	0	0
T2	272204	159	0	0
T3	12258	1136	0	0
T4	5161	36	0	0
T5	37680	2629	0	0
T6	42891	2829	0	0
T7	579366	5754	0	0
T8	923154	10696	0	0
T9	1563	29	0	0
T10	0	964	0	0
T16	355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	1127988	0	0
T1	250448	3592	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	4436	0	0
T5	37680	504	0	0
T6	42891	737	0	0
T7	579366	2421	0	0
T8	923154	193	0	0
T9	1563	2	0	0
T10	0	129	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	217635	0	0
T1	250448	1009	0	0
T2	272204	8	0	0
T3	12258	13	0	0
T4	5161	287	0	0
T5	37680	377	0	0
T6	42891	532	0	0
T7	579366	538	0	0
T8	923154	60	0	0
T9	1563	2	0	0
T10	0	97	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	226790	0	0
GntImpliesValid_A	408240284	226790	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	226790	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	4723075	0	0
ReadyAndValidImplyGrant_A	408240284	226790	0	0
ReqAndReadyImplyGrant_A	408240284	226790	0	0
ReqImpliesValid_A	408240284	1358740	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	226790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	4723075	0	0
T2	272204	95	0	0
T3	12258	356	0	0
T4	5161	0	0	0
T5	37680	1725	0	0
T6	42891	3266	0	0
T7	579366	0	0	0
T8	923154	6953	0	0
T9	1563	24	0	0
T10	26668	568	0	0
T11	0	668	0	0
T13	0	1803	0	0
T14	0	3673	0	0
T16	355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	1358740	0	0
T2	272204	27	0	0
T3	12258	49	0	0
T4	5161	0	0	0
T5	37680	441	0	0
T6	42891	690	0	0
T7	579366	0	0	0
T8	923154	267	0	0
T9	1563	2	0	0
T10	26668	120	0	0
T11	0	169	0	0
T13	0	630	0	0
T14	0	463	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	226790	0	0
T2	272204	11	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	376	0	0
T6	42891	517	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	2	0	0
T10	26668	85	0	0
T11	0	149	0	0
T13	0	515	0	0
T14	0	153	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	232919	0	0
GntImpliesValid_A	408240284	232919	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	232919	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	4632180	0	0
ReadyAndValidImplyGrant_A	408240284	232919	0	0
ReqAndReadyImplyGrant_A	408240284	232919	0	0
ReqImpliesValid_A	408240284	1364081	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	232919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	4632180	0	0
T2	272204	165	0	0
T3	12258	429	0	0
T4	5161	0	0	0
T5	37680	1583	0	0
T6	42891	3248	0	0
T7	579366	0	0	0
T8	923154	9545	0	0
T9	1563	41	0	0
T10	26668	701	0	0
T11	0	1296	0	0
T13	0	4472	0	0
T14	0	1693	0	0
T16	355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	1364081	0	0
T2	272204	43	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	462	0	0
T6	42891	784	0	0
T7	579366	0	0	0
T8	923154	474	0	0
T9	1563	2	0	0
T10	26668	113	0	0
T11	0	187	0	0
T13	0	1990	0	0
T14	0	159	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232919	0	0
T2	272204	19	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	373	0	0
T6	42891	542	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	79	0	0
T11	0	155	0	0
T13	0	986	0	0
T14	0	125	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	220861	0	0
GntImpliesValid_A	408240284	220861	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	220861	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	5000962	0	0
ReadyAndValidImplyGrant_A	408240284	220861	0	0
ReqAndReadyImplyGrant_A	408240284	220861	0	0
ReqImpliesValid_A	408240284	1164665	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	220861	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	5000962	0	0
T2	272204	94	0	0
T3	12258	336	0	0
T4	5161	0	0	0
T5	37680	1601	0	0
T6	42891	4545	0	0
T7	579366	0	0	0
T8	923154	15664	0	0
T9	1563	93	0	0
T10	26668	815	0	0
T11	0	654	0	0
T13	0	4374	0	0
T14	0	3375	0	0
T16	355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	1164665	0	0
T2	272204	21	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	445	0	0
T6	42891	799	0	0
T7	579366	0	0	0
T8	923154	743	0	0
T9	1563	3	0	0
T10	26668	114	0	0
T11	0	157	0	0
T13	0	7858	0	0
T14	0	495	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220861	0	0
T2	272204	9	0	0
T3	12258	15	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	537	0	0
T7	579366	0	0	0
T8	923154	78	0	0
T9	1563	3	0	0
T10	26668	84	0	0
T11	0	147	0	0
T13	0	2575	0	0
T14	0	130	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T5,T6,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	229063	0	0
GntImpliesValid_A	408240284	229063	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	229063	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2855501	0	0
ReadyAndValidImplyGrant_A	408240284	229063	0	0
ReqAndReadyImplyGrant_A	408240284	229063	0	0
ReqImpliesValid_A	408240284	555842	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	229063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2855501	0	0
T1	250448	1	0	0
T2	272204	41	0	0
T3	12258	95	0	0
T4	5161	2	0	0
T5	37680	391	0	0
T6	42891	523	0	0
T7	579366	1	0	0
T8	923154	23310	0	0
T9	1563	60	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	555842	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	386	0	0
T6	42891	561	0	0
T7	579366	0	0	0
T8	923154	2203	0	0
T9	1563	7	0	0
T10	26668	113	0	0
T11	0	187	0	0
T13	0	2183	0	0
T14	0	218	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229063	0	0
T2	272204	8	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	382	0	0
T6	42891	541	0	0
T7	579366	0	0	0
T8	923154	74	0	0
T9	1563	7	0	0
T10	26668	79	0	0
T11	0	163	0	0
T13	0	1552	0	0
T14	0	133	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	223826	0	0
GntImpliesValid_A	408240284	223826	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	223826	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2894596	0	0
ReadyAndValidImplyGrant_A	408240284	223826	0	0
ReqAndReadyImplyGrant_A	408240284	223826	0	0
ReqImpliesValid_A	408240284	577722	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	223826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2894596	0	0
T1	250448	1	0	0
T2	272204	50	0	0
T3	12258	243	0	0
T4	5161	2	0	0
T5	37680	524	0	0
T6	42891	511	0	0
T7	579366	1	0	0
T8	923154	18344	0	0
T9	1563	29	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	577722	0	0
T2	272204	18	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	725	0	0
T6	42891	543	0	0
T7	579366	0	0	0
T8	923154	1510	0	0
T9	1563	6	0	0
T10	26668	153	0	0
T11	0	333	0	0
T13	0	468	0	0
T14	0	291	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	223826	0	0
T2	272204	12	0	0
T3	12258	23	0	0
T4	5161	0	0	0
T5	37680	618	0	0
T6	42891	526	0	0
T7	579366	0	0	0
T8	923154	63	0	0
T9	1563	6	0	0
T10	26668	96	0	0
T11	0	204	0	0
T13	0	458	0	0
T14	0	164	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	215803	0	0
GntImpliesValid_A	408240284	215803	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	215803	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2824159	0	0
ReadyAndValidImplyGrant_A	408240284	215803	0	0
ReqAndReadyImplyGrant_A	408240284	215803	0	0
ReqImpliesValid_A	408240284	547882	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	215803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2824159	0	0
T1	250448	1	0	0
T2	272204	47	0	0
T3	12258	142	0	0
T4	5161	2	0	0
T5	37680	386	0	0
T6	42891	546	0	0
T7	579366	1	0	0
T8	923154	29233	0	0
T9	1563	36	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	547882	0	0
T2	272204	8	0	0
T3	12258	27	0	0
T4	5161	0	0	0
T5	37680	394	0	0
T6	42891	570	0	0
T7	579366	0	0	0
T8	923154	422	0	0
T9	1563	4	0	0
T10	26668	118	0	0
T11	0	2870	0	0
T13	0	2659	0	0
T14	0	226	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	215803	0	0
T2	272204	8	0	0
T3	12258	21	0	0
T4	5161	0	0	0
T5	37680	384	0	0
T6	42891	557	0	0
T7	579366	0	0	0
T8	923154	84	0	0
T9	1563	4	0	0
T10	26668	93	0	0
T11	0	672	0	0
T13	0	1575	0	0
T14	0	138	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	219690	0	0
GntImpliesValid_A	408240284	219690	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	219690	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2803049	0	0
ReadyAndValidImplyGrant_A	408240284	219690	0	0
ReqAndReadyImplyGrant_A	408240284	219690	0	0
ReqImpliesValid_A	408240284	564955	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	219690	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2803049	0	0
T1	250448	1	0	0
T2	272204	32	0	0
T3	12258	58	0	0
T4	5161	2	0	0
T5	37680	369	0	0
T6	42891	528	0	0
T7	579366	1714	0	0
T8	923154	18745	0	0
T9	1563	27	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	564955	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	364	0	0
T6	42891	556	0	0
T7	579366	655	0	0
T8	923154	338	0	0
T9	1563	5	0	0
T10	26668	115	0	0
T11	0	209	0	0
T13	0	528	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	219690	0	0
T2	272204	12	0	0
T3	12258	7	0	0
T4	5161	0	0	0
T5	37680	360	0	0
T6	42891	541	0	0
T7	579366	437	0	0
T8	923154	63	0	0
T9	1563	3	0	0
T10	26668	91	0	0
T11	0	168	0	0
T13	0	510	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	220137	0	0
GntImpliesValid_A	408240284	220137	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	220137	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2848188	0	0
ReadyAndValidImplyGrant_A	408240284	220137	0	0
ReqAndReadyImplyGrant_A	408240284	220137	0	0
ReqImpliesValid_A	408240284	560233	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	220137	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2848188	0	0
T1	250448	1528	0	0
T2	272204	37	0	0
T3	12258	103	0	0
T4	5161	2	0	0
T5	37680	441	0	0
T6	42891	511	0	0
T7	579366	1	0	0
T8	923154	26475	0	0
T9	1563	4	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	560233	0	0
T1	250448	1213	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	1322	0	0
T6	42891	547	0	0
T7	579366	0	0	0
T8	923154	200	0	0
T9	1563	0	0	0
T10	0	133	0	0
T11	0	325	0	0
T13	0	2440	0	0
T14	0	241	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	220137	0	0
T1	250448	486	0	0
T2	272204	8	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	875	0	0
T6	42891	528	0	0
T7	579366	0	0	0
T8	923154	71	0	0
T9	1563	0	0	0
T10	0	88	0	0
T11	0	182	0	0
T13	0	1463	0	0
T14	0	156	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	227494	0	0
GntImpliesValid_A	408240284	227494	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	227494	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2848964	0	0
ReadyAndValidImplyGrant_A	408240284	227494	0	0
ReqAndReadyImplyGrant_A	408240284	227494	0	0
ReqImpliesValid_A	408240284	624099	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	227494	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2848964	0	0
T1	250448	1	0	0
T2	272204	60	0	0
T3	12258	53	0	0
T4	5161	2	0	0
T5	37680	384	0	0
T6	42891	550	0	0
T7	579366	1	0	0
T8	923154	16999	0	0
T9	1563	30	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	624099	0	0
T2	272204	20	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	379	0	0
T6	42891	562	0	0
T7	579366	0	0	0
T8	923154	186	0	0
T9	1563	2	0	0
T10	26668	140	0	0
T11	0	302	0	0
T13	0	490	0	0
T14	0	230	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	227494	0	0
T2	272204	14	0	0
T3	12258	6	0	0
T4	5161	0	0	0
T5	37680	375	0	0
T6	42891	555	0	0
T7	579366	0	0	0
T8	923154	54	0	0
T9	1563	2	0	0
T10	26668	103	0	0
T11	0	179	0	0
T13	0	471	0	0
T14	0	151	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T8
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T5,T6,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	232184	0	0
GntImpliesValid_A	408240284	232184	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	232184	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2856242	0	0
ReadyAndValidImplyGrant_A	408240284	232184	0	0
ReqAndReadyImplyGrant_A	408240284	232184	0	0
ReqImpliesValid_A	408240284	589296	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	232184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2856242	0	0
T1	250448	1	0	0
T2	272204	44	0	0
T3	12258	133	0	0
T4	5161	2	0	0
T5	37680	818	0	0
T6	42891	476	0	0
T7	579366	1	0	0
T8	923154	20631	0	0
T9	1563	22	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	589296	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	1049	0	0
T6	42891	512	0	0
T7	579366	0	0	0
T8	923154	1262	0	0
T9	1563	2	0	0
T10	26668	163	0	0
T11	0	174	0	0
T13	0	1580	0	0
T14	0	153	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232184	0	0
T2	272204	10	0	0
T3	12258	19	0	0
T4	5161	0	0	0
T5	37680	927	0	0
T6	42891	493	0	0
T7	579366	0	0	0
T8	923154	55	0	0
T9	1563	2	0	0
T10	26668	98	0	0
T11	0	153	0	0
T13	0	1040	0	0
T14	0	127	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	216719	0	0
GntImpliesValid_A	408240284	216719	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	216719	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2784805	0	0
ReadyAndValidImplyGrant_A	408240284	216719	0	0
ReqAndReadyImplyGrant_A	408240284	216719	0	0
ReqImpliesValid_A	408240284	564032	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	216719	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2784805	0	0
T1	250448	1	0	0
T2	272204	59	0	0
T3	12258	99	0	0
T4	5161	2	0	0
T5	37680	335	0	0
T6	42891	461	0	0
T7	579366	1823	0	0
T8	923154	25316	0	0
T9	1563	4	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	564032	0	0
T2	272204	26	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	499	0	0
T7	579366	1157	0	0
T8	923154	1153	0	0
T9	1563	0	0	0
T10	26668	131	0	0
T11	0	1545	0	0
T13	0	497	0	0
T14	0	238	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	216719	0	0
T2	272204	16	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	323	0	0
T6	42891	479	0	0
T7	579366	512	0	0
T8	923154	72	0	0
T9	1563	0	0	0
T10	26668	95	0	0
T11	0	753	0	0
T13	0	485	0	0
T14	0	157	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	248229	0	0
GntImpliesValid_A	408240284	248229	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	248229	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2918269	0	0
ReadyAndValidImplyGrant_A	408240284	248229	0	0
ReqAndReadyImplyGrant_A	408240284	248229	0	0
ReqImpliesValid_A	408240284	649650	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	248229	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2918269	0	0
T1	250448	1	0	0
T2	272204	25	0	0
T3	12258	134	0	0
T4	5161	2	0	0
T5	37680	786	0	0
T6	42891	625	0	0
T7	579366	3478	0	0
T8	923154	17590	0	0
T9	1563	33	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	649650	0	0
T2	272204	20	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	949	0	0
T6	42891	661	0	0
T7	579366	2327	0	0
T8	923154	2378	0	0
T9	1563	4	0	0
T10	26668	126	0	0
T11	0	244	0	0
T12	0	4814	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	248229	0	0
T2	272204	11	0	0
T3	12258	14	0	0
T4	5161	0	0	0
T5	37680	861	0	0
T6	42891	642	0	0
T7	579366	1050	0	0
T8	923154	60	0	0
T9	1563	4	0	0
T10	26668	76	0	0
T11	0	181	0	0
T12	0	499	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	232213	0	0
GntImpliesValid_A	408240284	232213	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	232213	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2885535	0	0
ReadyAndValidImplyGrant_A	408240284	232213	0	0
ReqAndReadyImplyGrant_A	408240284	232213	0	0
ReqImpliesValid_A	408240284	596752	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	232213	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2885535	0	0
T1	250448	1	0	0
T2	272204	40	0	0
T3	12258	76	0	0
T4	5161	2	0	0
T5	37680	379	0	0
T6	42891	524	0	0
T7	579366	1742	0	0
T8	923154	20470	0	0
T9	1563	20	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	596752	0	0
T2	272204	10	0	0
T3	12258	22	0	0
T4	5161	0	0	0
T5	37680	378	0	0
T6	42891	548	0	0
T7	579366	1090	0	0
T8	923154	1337	0	0
T9	1563	2	0	0
T10	26668	132	0	0
T11	0	335	0	0
T13	0	1172	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	232213	0	0
T2	272204	10	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	372	0	0
T6	42891	535	0	0
T7	579366	503	0	0
T8	923154	71	0	0
T9	1563	2	0	0
T10	26668	105	0	0
T11	0	214	0	0
T13	0	1004	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	229402	0	0
GntImpliesValid_A	408240284	229402	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	229402	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2825552	0	0
ReadyAndValidImplyGrant_A	408240284	229402	0	0
ReqAndReadyImplyGrant_A	408240284	229402	0	0
ReqImpliesValid_A	408240284	536335	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	229402	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2825552	0	0
T1	250448	1	0	0
T2	272204	67	0	0
T3	12258	105	0	0
T4	5161	2	0	0
T5	37680	373	0	0
T6	42891	528	0	0
T7	579366	1756	0	0
T8	923154	18835	0	0
T9	1563	6	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	536335	0	0
T2	272204	19	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	374	0	0
T6	42891	544	0	0
T7	579366	1124	0	0
T8	923154	2536	0	0
T9	1563	1	0	0
T10	26668	93	0	0
T11	0	383	0	0
T13	0	1594	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	229402	0	0
T2	272204	15	0	0
T3	12258	12	0	0
T4	5161	0	0	0
T5	37680	367	0	0
T6	42891	535	0	0
T7	579366	519	0	0
T8	923154	70	0	0
T9	1563	1	0	0
T10	26668	80	0	0
T11	0	202	0	0
T13	0	1045	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	225306	0	0
GntImpliesValid_A	408240284	225306	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	225306	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2849763	0	0
ReadyAndValidImplyGrant_A	408240284	225306	0	0
ReqAndReadyImplyGrant_A	408240284	225306	0	0
ReqImpliesValid_A	408240284	576098	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	225306	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2849763	0	0
T1	250448	1	0	0
T2	272204	50	0	0
T3	12258	103	0	0
T4	5161	2	0	0
T5	37680	335	0	0
T6	42891	535	0	0
T7	579366	1	0	0
T8	923154	22475	0	0
T9	1563	9	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	576098	0	0
T2	272204	12	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	325	0	0
T6	42891	567	0	0
T7	579366	0	0	0
T8	923154	492	0	0
T9	1563	2	0	0
T10	26668	130	0	0
T11	0	225	0	0
T13	0	548	0	0
T14	0	212	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	225306	0	0
T2	272204	11	0	0
T3	12258	11	0	0
T4	5161	0	0	0
T5	37680	324	0	0
T6	42891	550	0	0
T7	579366	0	0	0
T8	923154	68	0	0
T9	1563	2	0	0
T10	26668	92	0	0
T11	0	172	0	0
T13	0	533	0	0
T14	0	137	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	230200	0	0
GntImpliesValid_A	408240284	230200	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	230200	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2796293	0	0
ReadyAndValidImplyGrant_A	408240284	230200	0	0
ReqAndReadyImplyGrant_A	408240284	230200	0	0
ReqImpliesValid_A	408240284	577457	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	230200	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2796293	0	0
T1	250448	1	0	0
T2	272204	36	0	0
T3	12258	221	0	0
T4	5161	2	0	0
T5	37680	605	0	0
T6	42891	540	0	0
T7	579366	3392	0	0
T8	923154	23825	0	0
T9	1563	23	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	577457	0	0
T2	272204	7	0	0
T3	12258	39	0	0
T4	5161	0	0	0
T5	37680	715	0	0
T6	42891	574	0	0
T7	579366	2275	0	0
T8	923154	1588	0	0
T9	1563	7	0	0
T10	26668	138	0	0
T11	0	232	0	0
T13	0	1246	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	230200	0	0
T2	272204	7	0	0
T3	12258	24	0	0
T4	5161	0	0	0
T5	37680	654	0	0
T6	42891	556	0	0
T7	579366	998	0	0
T8	923154	71	0	0
T9	1563	4	0	0
T10	26668	83	0	0
T11	0	160	0	0
T13	0	1097	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	221434	0	0
GntImpliesValid_A	408240284	221434	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	221434	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	2815074	0	0
ReadyAndValidImplyGrant_A	408240284	221434	0	0
ReqAndReadyImplyGrant_A	408240284	221434	0	0
ReqImpliesValid_A	408240284	568739	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	0	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	221434	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2815074	0	0
T1	250448	1670	0	0
T2	272204	65	0	0
T3	12258	103	0	0
T4	5161	2	0	0
T5	37680	529	0	0
T6	42891	536	0	0
T7	579366	1	0	0
T8	923154	21996	0	0
T9	1563	4	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	568739	0	0
T1	250448	1265	0	0
T2	272204	18	0	0
T3	12258	16	0	0
T4	5161	0	0	0
T5	37680	944	0	0
T6	42891	562	0	0
T7	579366	0	0	0
T8	923154	1676	0	0
T9	1563	0	0	0
T10	0	139	0	0
T11	0	208	0	0
T13	0	1609	0	0
T14	0	147	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	221434	0	0
T1	250448	530	0	0
T2	272204	18	0	0
T3	12258	13	0	0
T4	5161	0	0	0
T5	37680	730	0	0
T6	42891	548	0	0
T7	579366	0	0	0
T8	923154	70	0	0
T9	1563	0	0	0
T10	0	87	0	0
T11	0	159	0	0
T13	0	1049	0	0
T14	0	133	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	901973	0	0
GntImpliesValid_A	408240284	901973	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	901973	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	10873375	0	0
ReadyAndValidImplyGrant_A	408240284	901973	0	0
ReqAndReadyImplyGrant_A	408240284	901973	0	0
ReqImpliesValid_A	408240284	2226969	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	20920	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	901973	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	10873375	0	0
T1	250448	4155	0	0
T2	272204	188	0	0
T3	12258	716	0	0
T4	5161	359	0	0
T5	37680	13	0	0
T6	42891	2	0	0
T7	579366	4403	0	0
T8	923154	64418	0	0
T9	1563	84	0	0
T16	355	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	2226969	0	0
T1	250448	3794	0	0
T2	272204	51	0	0
T3	12258	148	0	0
T4	5161	128	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	2752	0	0
T8	923154	6195	0	0
T9	1563	10	0	0
T10	0	547	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	20920	0	900
T1	250448	23	0	1
T2	272204	0	0	1
T3	12258	0	0	1
T4	5161	0	0	1
T5	37680	17	0	1
T6	42891	29	0	1
T7	579366	6	0	1
T8	923154	0	0	1
T9	1563	0	0	1
T13	0	481	0	0
T15	0	1	0	0
T16	355	0	0	1
T17	0	24	0	0
T18	0	16	0	0
T19	0	1	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	901973	0	0
T1	250448	1716	0	0
T2	272204	48	0	0
T3	12258	108	0	0
T4	5161	67	0	0
T5	37680	1906	0	0
T6	42891	2155	0	0
T7	579366	1550	0	0
T8	923154	195	0	0
T9	1563	10	0	0
T10	0	302	0	0
T16	355	0	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408240284	408113793	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	408240284	895522	0	0
GntImpliesValid_A	408240284	895522	0	0
GrantKnown_A	408240284	408113793	0	0
IdxKnown_A	408240284	408113793	0	0
IndexIsCorrect_A	408240284	895522	0	0
LockArbDecision_A	408240284	0	0	0
NoReadyValidNoGrant_A	408240284	341480613	0	0
ReadyAndValidImplyGrant_A	408240284	895522	0	0
ReqAndReadyImplyGrant_A	408240284	895522	0	0
ReqImpliesValid_A	408240284	12655191	0	0
ReqStaysHighUntilGranted0_M	408240284	0	0	0
RoundRobin_A	408240284	25261	0	900
ValidKnown_A	408240284	408113793	0	0
gen_data_port_assertion.DataFlow_A	408240284	895522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	341480613	0	0
T1	250448	208363	0	0
T2	272204	226617	0	0
T3	12258	9825	0	0
T4	5161	4143	0	0
T5	37680	1	0	0
T6	42891	1	0	0
T7	579366	482065	0	0
T8	923154	840270	0	0
T9	1563	987	0	0
T16	355	274	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	12655191	0	0
T1	250448	4724	0	0
T2	272204	196	0	0
T3	12258	786	0	0
T4	5161	412	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	10316	0	0
T8	923154	81272	0	0
T9	1563	105	0	0
T10	0	2640	0	0
T16	355	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	25261	0	900
T1	250448	10	0	1
T2	272204	0	0	1
T3	12258	0	0	1
T4	5161	0	0	1
T5	37680	106	0	1
T6	42891	25	0	1
T7	579366	36	0	1
T8	923154	0	0	1
T9	1563	0	0	1
T11	0	1	0	0
T12	0	74	0	0
T13	0	24	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	355	0	0	1
T17	0	30	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	408113793	0	0
T1	250448	250441	0	0
T2	272204	272155	0	0
T3	12258	11560	0	0
T4	5161	4963	0	0
T5	37680	36844	0	0
T6	42891	42739	0	0
T7	579366	579364	0	0
T8	923154	923131	0	0
T9	1563	1274	0	0
T16	355	310	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408240284	895522	0	0
T1	250448	970	0	0
T2	272204	43	0	0
T3	12258	108	0	0
T4	5161	50	0	0
T5	37680	2517	0	0
T6	42891	2116	0	0
T7	579366	2216	0	0
T8	923154	234	0	0
T9	1563	15	0	0
T10	0	321	0	0
T16	355	0	0	0