Unified Coverage Report :: Group :: tl_agent_pkg::pending_req_on_rst_cg

Group : tl_agent_pkg::pending_req_on_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

27 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1142

1

T5

13

T10

3

T11

7

values[0x1]

21

1

T11

1

T34

1

T207

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1148

1

T5

13

T10

3

T11

8

values[0x1]

15

1

T37

1

T170

2

T133

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1138

1

T5

13

T10

3

T11

8

values[0x1]

25

1

T84

2

T207

1

T24

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1146

1

T5

13

T10

3

T11

8

values[0x1]

17

1

T32

1

T33

1

T24

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1151

1

T5

13

T10

3

T11

8

values[0x1]

12

1

T24

1

T325

1

T326

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1142

1

T5

13

T10

3

T11

8

values[0x1]

21

1

T209

1

T122

1

T91

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1067

1

T5

13

T10

3

T11

6

values[0x1]

96

1

T11

2

T23

1

T79

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1147

1

T5

13

T10

3

T11

8

values[0x1]

16

1

T81

1

T207

1

T122

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1145

1

T5

12

T10

3

T11

8

values[0x1]

18

1

T5

1

T23

1

T79

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1142

1

T5

13

T10

3

T11

8

values[0x1]

21

1

T79

1

T33

1

T24

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1131

1

T5

13

T10

3

T11

8

values[0x1]

32

1

T79

2

T81

1

T33

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1139

1

T5

12

T10

3

T11

8

values[0x1]

24

1

T5

1

T32

1

T91

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1133

1

T5

13

T10

3

T11

8

values[0x1]

30

1

T81

1

T122

1

T107

3

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1135

1

T5

13

T10

3

T11

8

values[0x1]

28

1

T32

1

T81

1

T190

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1072

1

T5

12

T10

3

T11

8

values[0x1]

91

1

T5

1

T32

1

T81

6

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1143

1

T5

13

T10

3

T11

8

values[0x1]

20

1

T34

2

T190

1

T327

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

515

1

T5

6

T10

3

T11

3

values[0x1]

648

1

T5

7

T11

5

T23

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

582

1

T5

7

T10

3

T11

6

values[0x1]

581

1

T5

6

T11

2

T23

5

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1088

1

T5

13

T10

3

T11

8

values[0x1]

75

1

T79

2

T32

1

T81

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1146

1

T5

13

T10

3

T11

8

values[0x1]

17

1

T190

1

T201

1

T24

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

373

1

T5

4

T10

3

T11

1

values[0x1]

790

1

T5

9

T11

7

T23

8

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1138

1

T5

13

T10

3

T11

8

values[0x1]

25

1

T207

1

T25

1

T170

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1142

1

T5

13

T10

3

T11

7

values[0x1]

21

1

T11

1

T33

1

T207

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1134

1

T5

13

T10

3

T11

8

values[0x1]

29

1

T81

1

T201

1

T91

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1044

1

T5

11

T10

3

T11

7

values[0x1]

119

1

T5

2

T11

1

T79

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1139

1

T5

13

T10

3

T11

8

values[0x1]

24

1

T32

1

T122

1

T91

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1142

1

T5

13

T10

3

T11

8

values[0x1]

21

1

T79

1

T33

1

T207

1