Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1564374	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249153

1

T1

15

T2

178

T3

339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	615391	1			T1	59		T2	391		T3	806
values[0x0]	583643	1			T1	3		T2	428		T3	775
values[0x1]	614493	1			T1	52		T2	435		T3	782

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1209896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603631

1

T1

51

T2

411

T3

793

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29135	1			T1	1		T2	15		T3	30
valid_sources[0x01]	28374	1			T1	1		T2	18		T3	43
valid_sources[0x02]	29583	1			T1	1		T2	16		T3	39
valid_sources[0x03]	27841	1			T1	3		T2	33		T3	38
valid_sources[0x04]	28823	1			T2	16		T3	39		T5	6
valid_sources[0x05]	28471	1			T1	1		T2	31		T3	47
valid_sources[0x06]	28498	1			T1	2		T2	14		T3	34
valid_sources[0x07]	27789	1			T2	33		T3	41		T5	10
valid_sources[0x08]	27356	1			T1	2		T2	14		T3	37
valid_sources[0x09]	27608	1			T2	9		T3	36		T5	11
valid_sources[0x0a]	27840	1			T1	2		T2	16		T3	37
valid_sources[0x0b]	27197	1			T1	1		T2	14		T3	41
valid_sources[0x0c]	28418	1			T1	3		T2	31		T3	36
valid_sources[0x0d]	27906	1			T1	3		T2	31		T3	35
valid_sources[0x0e]	29554	1			T1	3		T2	17		T3	34
valid_sources[0x0f]	27024	1			T1	1		T2	20		T3	32
valid_sources[0x10]	28820	1			T1	2		T2	36		T3	41
valid_sources[0x11]	27156	1			T1	1		T2	16		T3	31
valid_sources[0x12]	29665	1			T2	22		T3	38		T4	3
valid_sources[0x13]	28555	1			T1	2		T2	24		T3	43
valid_sources[0x14]	28836	1			T2	7		T3	42		T5	7
valid_sources[0x15]	29153	1			T1	2		T2	25		T3	32
valid_sources[0x16]	29173	1			T1	1		T2	18		T3	33
valid_sources[0x17]	27348	1			T1	3		T2	12		T3	40
valid_sources[0x18]	29262	1			T1	2		T2	13		T3	41
valid_sources[0x19]	27889	1			T1	5		T2	22		T3	25
valid_sources[0x1a]	28237	1			T1	2		T2	5		T3	36
valid_sources[0x1b]	27481	1			T1	2		T2	13		T3	51
valid_sources[0x1c]	29744	1			T1	2		T2	22		T3	28
valid_sources[0x1d]	28526	1			T1	2		T2	29		T3	39
valid_sources[0x1e]	28411	1			T1	3		T2	12		T3	43
valid_sources[0x1f]	27483	1			T1	5		T2	28		T3	28
valid_sources[0x20]	27562	1			T1	2		T2	22		T3	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26134

1

T1

7

T2

25

T3

39

values[0x0]

all_enables

biggest_size

196502

1

T1

2

T2

137

T3

263

values[0x1]

all_enables

biggest_size

26517

1

T1

6

T2

16

T3

37

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1576852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

256816

1

T1

13

T2

153

T3

356

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628234	1			T1	42		T2	384		T3	796
values[0x0]	577850	1			T1	5		T2	376		T3	768
values[0x1]	627584	1			T1	43		T2	416		T3	816

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1208917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

624751

1

T1

42

T2

387

T3

796

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28562	1			T1	4		T2	26		T3	36
valid_sources[0x01]	29012	1			T1	2		T2	18		T3	75
valid_sources[0x02]	29242	1			T1	2		T2	16		T3	24
valid_sources[0x03]	28844	1			T1	2		T2	19		T3	53
valid_sources[0x04]	28722	1			T1	1		T2	31		T3	34
valid_sources[0x05]	28664	1			T1	5		T2	18		T3	25
valid_sources[0x06]	28597	1			T1	2		T2	15		T3	33
valid_sources[0x07]	28997	1			T1	4		T2	20		T3	24
valid_sources[0x08]	27820	1			T1	1		T2	22		T3	36
valid_sources[0x09]	28131	1			T1	1		T2	17		T3	41
valid_sources[0x0a]	29309	1			T1	1		T2	13		T3	44
valid_sources[0x0b]	28321	1			T1	2		T2	18		T3	27
valid_sources[0x0c]	29019	1			T1	2		T2	27		T3	64
valid_sources[0x0d]	28770	1			T1	3		T2	19		T3	30
valid_sources[0x0e]	28374	1			T1	1		T2	18		T3	35
valid_sources[0x0f]	28598	1			T2	18		T3	20		T5	5
valid_sources[0x10]	29000	1			T1	1		T2	25		T3	33
valid_sources[0x11]	28703	1			T1	2		T2	19		T3	53
valid_sources[0x12]	28739	1			T1	1		T2	13		T3	16
valid_sources[0x13]	28824	1			T1	2		T2	20		T3	25
valid_sources[0x14]	28659	1			T2	17		T3	38		T4	3
valid_sources[0x15]	28554	1			T2	15		T3	38		T4	3
valid_sources[0x16]	28620	1			T1	3		T2	19		T3	30
valid_sources[0x17]	27932	1			T2	16		T3	44		T5	8
valid_sources[0x18]	28506	1			T1	2		T2	15		T3	21
valid_sources[0x19]	29118	1			T1	1		T2	27		T3	46
valid_sources[0x1a]	29032	1			T1	4		T2	25		T3	64
valid_sources[0x1b]	28467	1			T1	3		T2	21		T3	46
valid_sources[0x1c]	29563	1			T1	1		T2	17		T3	36
valid_sources[0x1d]	28762	1			T1	1		T2	19		T3	38
valid_sources[0x1e]	28978	1			T2	15		T3	45		T4	1
valid_sources[0x1f]	28935	1			T2	18		T3	40		T4	7
valid_sources[0x20]	28840	1			T1	4		T2	22		T3	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26971

1

T1

4

T2

12

T3

43

values[0x0]

all_enables

biggest_size

202869

1

T1

4

T2

129

T3

281

values[0x1]

all_enables

biggest_size

26976

1

T1

5

T2

12

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1571469	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250676

1

T1

9

T2

153

T3

359

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	618628	1			T1	43		T2	374		T3	924
values[0x0]	585703	1			T1	8		T2	354		T3	831
values[0x1]	617814	1			T1	37		T2	378		T3	845

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

607398

1

T1

36

T2

365

T3

888

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28454	1			T1	1		T2	10		T3	39
valid_sources[0x01]	28923	1			T1	3		T2	8		T3	42
valid_sources[0x02]	28643	1			T1	1		T2	22		T3	34
valid_sources[0x03]	28537	1			T1	2		T2	26		T3	50
valid_sources[0x04]	27862	1			T1	1		T2	17		T3	49
valid_sources[0x05]	29370	1			T2	20		T3	33		T5	6
valid_sources[0x06]	28452	1			T1	1		T2	13		T3	29
valid_sources[0x07]	28923	1			T1	1		T2	13		T3	45
valid_sources[0x08]	28579	1			T1	1		T2	20		T3	55
valid_sources[0x09]	27550	1			T1	1		T2	16		T3	46
valid_sources[0x0a]	28983	1			T1	1		T2	27		T3	25
valid_sources[0x0b]	28343	1			T2	32		T3	45		T5	10
valid_sources[0x0c]	28842	1			T1	1		T2	16		T3	38
valid_sources[0x0d]	28133	1			T1	3		T2	26		T3	33
valid_sources[0x0e]	28386	1			T1	2		T2	12		T3	32
valid_sources[0x0f]	27644	1			T1	3		T2	26		T3	49
valid_sources[0x10]	27913	1			T1	5		T2	15		T3	22
valid_sources[0x11]	28658	1			T1	1		T2	26		T3	56
valid_sources[0x12]	29394	1			T2	26		T3	48		T4	5
valid_sources[0x13]	28675	1			T2	15		T3	58		T4	2
valid_sources[0x14]	28896	1			T1	1		T2	14		T3	43
valid_sources[0x15]	28412	1			T2	14		T3	49		T4	1
valid_sources[0x16]	28524	1			T2	24		T3	49		T4	1
valid_sources[0x17]	28309	1			T1	2		T2	18		T3	29
valid_sources[0x18]	29283	1			T2	24		T3	19		T5	12
valid_sources[0x19]	27697	1			T1	1		T2	14		T3	21
valid_sources[0x1a]	28579	1			T1	3		T2	17		T3	32
valid_sources[0x1b]	28149	1			T2	8		T3	27		T5	9
valid_sources[0x1c]	29325	1			T1	4		T2	23		T3	40
valid_sources[0x1d]	27975	1			T1	1		T2	18		T3	35
valid_sources[0x1e]	27984	1			T1	1		T2	28		T3	38
valid_sources[0x1f]	28562	1			T1	3		T2	13		T3	41
valid_sources[0x20]	28747	1			T1	1		T2	28		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26343

1

T1

3

T2

14

T3

43

values[0x0]

all_enables

biggest_size

197970

1

T1

3

T2

116

T3

280

values[0x1]

all_enables

biggest_size

26363

1

T1

3

T2

23

T3

36