Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7798100	0	0
GntImpliesValid_A	2147483647	7798100	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7798100	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	463158024	0	0
ReadyAndValidImplyGrant_A	2147483647	7798100	0	0
ReqAndReadyImplyGrant_A	2147483647	7798100	0	0
ReqImpliesValid_A	2147483647	33475652	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44300	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7798100	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1212024	1211448	0	0
T2	18344664	18343968	0	0
T3	5032464	5032440	0	0
T4	4481256	4479720	0	0
T5	1224624	1184016	0	0
T6	10055640	10055424	0	0
T7	11920992	11919672	0	0
T8	500880	499704	0	0
T9	3570168	3567768	0	0
T10	12740496	12739416	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1212024	1211448	0	0
T2	18344664	18343968	0	0
T3	5032464	5032440	0	0
T4	4481256	4479720	0	0
T5	1224624	1184016	0	0
T6	10055640	10055424	0	0
T7	11920992	11919672	0	0
T8	500880	499704	0	0
T9	3570168	3567768	0	0
T10	12740496	12739416	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1212024	1211448	0	0
T2	18344664	18343968	0	0
T3	5032464	5032440	0	0
T4	4481256	4479720	0	0
T5	1224624	1184016	0	0
T6	10055640	10055424	0	0
T7	11920992	11919672	0	0
T8	500880	499704	0	0
T9	3570168	3567768	0	0
T10	12740496	12739416	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	463158024	0	0
T1	1212024	66702	0	0
T2	18344664	651512	0	0
T3	5032464	202461	0	0
T4	4481256	157230	0	0
T5	1224624	24628	0	0
T6	10055640	374721	0	0
T7	11920992	615510	0	0
T8	500880	32541	0	0
T9	3570168	125835	0	0
T10	12740496	761995	0	0
T11	0	12703	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33475652	0	0
T1	1212024	7156	0	0
T2	18344664	5944	0	0
T3	5032464	12106	0	0
T4	4481256	599	0	0
T5	1224624	38008	0	0
T6	10055640	26018	0	0
T7	11920992	28696	0	0
T8	500880	4510	0	0
T9	3570168	823	0	0
T10	12740496	162711	0	0
T11	0	9020	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44300	0	21600
T5	102052	490	0	2
T6	837970	19	0	2
T7	993416	0	0	2
T8	41740	0	0	2
T9	297514	0	0	2
T10	1061708	7	0	2
T11	94442	71	0	2
T12	0	8	0	0
T13	0	28	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	6	0	0
T17	0	2	0	0
T18	0	5	0	0
T19	0	1	0	0
T20	326712	0	0	2
T21	2878	0	0	2
T22	426082	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1212024	1211448	0	0
T2	18344664	18343968	0	0
T3	5032464	5032440	0	0
T4	4481256	4479720	0	0
T5	1224624	1184016	0	0
T6	10055640	10055424	0	0
T7	11920992	11919672	0	0
T8	500880	499704	0	0
T9	3570168	3567768	0	0
T10	12740496	12739416	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7798100	0	0
T1	1212024	3471	0	0
T2	18344664	3536	0	0
T3	5032464	7342	0	0
T4	4481256	359	0	0
T5	1224624	27291	0	0
T6	10055640	9247	0	0
T7	11920992	497	0	0
T8	500880	2058	0	0
T9	3570168	507	0	0
T10	12740496	55230	0	0
T11	0	7302	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	870251	0	0
GntImpliesValid_A	432396691	870251	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	870251	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	11864701	0	0
ReadyAndValidImplyGrant_A	432396691	870251	0	0
ReqAndReadyImplyGrant_A	432396691	870251	0	0
ReqImpliesValid_A	432396691	2440064	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	870251	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	11864701	0	0
T1	50501	2800	0	0
T2	764361	1633	0	0
T3	209686	3276	0	0
T4	186719	184	0	0
T5	51026	2127	0	0
T6	418985	4552	0	0
T7	496708	23291	0	0
T8	20870	1955	0	0
T9	148757	195	0	0
T10	530854	39420	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2440064	0	0
T1	50501	567	0	0
T2	764361	498	0	0
T3	209686	1183	0	0
T4	186719	67	0	0
T5	51026	3353	0	0
T6	418985	2532	0	0
T7	496708	2361	0	0
T8	20870	402	0	0
T9	148757	71	0	0
T10	530854	8728	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	870251	0	0
T1	50501	381	0	0
T2	764361	385	0	0
T3	209686	835	0	0
T4	186719	49	0	0
T5	51026	2733	0	0
T6	418985	1274	0	0
T7	496708	71	0	0
T8	20870	253	0	0
T9	148757	51	0	0
T10	530854	5357	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	867701	0	0
GntImpliesValid_A	432396691	867701	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	867701	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	11959612	0	0
ReadyAndValidImplyGrant_A	432396691	867701	0	0
ReqAndReadyImplyGrant_A	432396691	867701	0	0
ReqImpliesValid_A	432396691	2483436	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	867701	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	11959612	0	0
T1	50501	2779	0	0
T2	764361	1606	0	0
T3	209686	3120	0	0
T4	186719	168	0	0
T5	51026	2138	0	0
T6	418985	2347	0	0
T7	496708	20034	0	0
T8	20870	1641	0	0
T9	148757	252	0	0
T10	530854	46374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2483436	0	0
T1	50501	568	0	0
T2	764361	543	0	0
T3	209686	960	0	0
T4	186719	60	0	0
T5	51026	3274	0	0
T6	418985	802	0	0
T7	496708	1341	0	0
T8	20870	438	0	0
T9	148757	62	0	0
T10	530854	28102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	867701	0	0
T1	50501	384	0	0
T2	764361	389	0	0
T3	209686	740	0	0
T4	186719	39	0	0
T5	51026	2699	0	0
T6	418985	584	0	0
T7	496708	61	0	0
T8	20870	223	0	0
T9	148757	59	0	0
T10	530854	7709	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	214503	0	0
GntImpliesValid_A	432396691	214503	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	214503	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2929147	0	0
ReadyAndValidImplyGrant_A	432396691	214503	0	0
ReqAndReadyImplyGrant_A	432396691	214503	0	0
ReqImpliesValid_A	432396691	590346	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	214503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2929147	0	0
T1	50501	655	0	0
T2	764361	485	0	0
T3	209686	963	0	0
T4	186719	33	0	0
T5	51026	493	0	0
T6	418985	1761	0	0
T7	496708	3773	0	0
T8	20870	367	0	0
T9	148757	41	0	0
T10	530854	8109	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	590346	0	0
T1	50501	85	0	0
T2	764361	135	0	0
T3	209686	309	0	0
T4	186719	19	0	0
T5	51026	1295	0	0
T6	418985	1269	0	0
T7	496708	8	0	0
T8	20870	64	0	0
T9	148757	13	0	0
T10	530854	6016	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214503	0	0
T1	50501	82	0	0
T2	764361	120	0	0
T3	209686	235	0	0
T4	186719	10	0	0
T5	51026	887	0	0
T6	418985	519	0	0
T7	496708	8	0	0
T8	20870	52	0	0
T9	148757	13	0	0
T10	530854	1510	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	211163	0	0
GntImpliesValid_A	432396691	211163	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	211163	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3041976	0	0
ReadyAndValidImplyGrant_A	432396691	211163	0	0
ReqAndReadyImplyGrant_A	432396691	211163	0	0
ReqImpliesValid_A	432396691	510979	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	211163	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3041976	0	0
T1	50501	654	0	0
T2	764361	554	0	0
T3	209686	931	0	0
T4	186719	65	0	0
T5	51026	423	0	0
T6	418985	1323	0	0
T7	496708	5962	0	0
T8	20870	468	0	0
T9	148757	36	0	0
T10	530854	11259	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	510979	0	0
T1	50501	98	0	0
T2	764361	161	0	0
T3	209686	282	0	0
T4	186719	29	0	0
T5	51026	425	0	0
T6	418985	1088	0	0
T7	496708	14	0	0
T8	20870	63	0	0
T9	148757	12	0	0
T10	530854	3217	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	211163	0	0
T1	50501	81	0	0
T2	764361	121	0	0
T3	209686	228	0	0
T4	186719	14	0	0
T5	51026	417	0	0
T6	418985	413	0	0
T7	496708	14	0	0
T8	20870	52	0	0
T9	148757	10	0	0
T10	530854	1559	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	214455	0	0
GntImpliesValid_A	432396691	214455	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	214455	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	4284180	0	0
ReadyAndValidImplyGrant_A	432396691	214455	0	0
ReqAndReadyImplyGrant_A	432396691	214455	0	0
ReqImpliesValid_A	432396691	932615	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	214455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	4284180	0	0
T1	50501	637	0	0
T2	764361	1998	0	0
T3	209686	924	0	0
T4	186719	146	0	0
T5	51026	2427	0	0
T6	418985	3464	0	0
T7	496708	7496	0	0
T8	20870	787	0	0
T9	148757	99	0	0
T10	530854	7644	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	932615	0	0
T1	50501	117	0	0
T2	764361	318	0	0
T3	209686	257	0	0
T4	186719	26	0	0
T5	51026	578	0	0
T6	418985	2118	0	0
T7	496708	18	0	0
T8	20870	87	0	0
T9	148757	10	0	0
T10	530854	4452	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214455	0	0
T1	50501	99	0	0
T2	764361	102	0	0
T3	209686	203	0	0
T4	186719	12	0	0
T5	51026	440	0	0
T6	418985	443	0	0
T7	496708	18	0	0
T8	20870	72	0	0
T9	148757	10	0	0
T10	530854	2210	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	201229	0	0
GntImpliesValid_A	432396691	201229	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	201229	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	4373353	0	0
ReadyAndValidImplyGrant_A	432396691	201229	0	0
ReqAndReadyImplyGrant_A	432396691	201229	0	0
ReqImpliesValid_A	432396691	955798	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	201229	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	4373353	0	0
T1	50501	772	0	0
T2	764361	781	0	0
T3	209686	2144	0	0
T4	186719	133	0	0
T5	51026	2913	0	0
T6	418985	0	0	0
T7	496708	3890	0	0
T8	20870	829	0	0
T9	148757	218	0	0
T10	530854	7455	0	0
T11	0	6737	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	955798	0	0
T1	50501	94	0	0
T2	764361	133	0	0
T3	209686	337	0	0
T4	186719	39	0	0
T5	51026	5796	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	99	0	0
T9	148757	43	0	0
T10	530854	1236	0	0
T11	0	1533	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	201229	0	0
T1	50501	94	0	0
T2	764361	92	0	0
T3	209686	193	0	0
T4	186719	13	0	0
T5	51026	1303	0	0
T6	418985	0	0	0
T7	496708	14	0	0
T8	20870	57	0	0
T9	148757	19	0	0
T10	530854	1093	0	0
T11	0	629	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	223864	0	0
GntImpliesValid_A	432396691	223864	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	223864	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	4709922	0	0
ReadyAndValidImplyGrant_A	432396691	223864	0	0
ReqAndReadyImplyGrant_A	432396691	223864	0	0
ReqImpliesValid_A	432396691	1166809	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	223864	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	4709922	0	0
T1	50501	1363	0	0
T2	764361	1230	0	0
T3	209686	951	0	0
T4	186719	126	0	0
T5	51026	2901	0	0
T6	418985	0	0	0
T7	496708	1786	0	0
T8	20870	548	0	0
T9	148757	203	0	0
T10	530854	6754	0	0
T11	0	3155	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	1166809	0	0
T1	50501	176	0	0
T2	764361	161	0	0
T3	209686	276	0	0
T4	186719	7	0	0
T5	51026	645	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	87	0	0
T9	148757	40	0	0
T10	530854	1965	0	0
T11	0	904	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223864	0	0
T1	50501	99	0	0
T2	764361	104	0	0
T3	209686	221	0	0
T4	186719	7	0	0
T5	51026	425	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	54	0	0
T9	148757	22	0	0
T10	530854	1555	0	0
T11	0	636	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	204417	0	0
GntImpliesValid_A	432396691	204417	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	204417	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	4301714	0	0
ReadyAndValidImplyGrant_A	432396691	204417	0	0
ReqAndReadyImplyGrant_A	432396691	204417	0	0
ReqImpliesValid_A	432396691	997335	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	204417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	4301714	0	0
T1	50501	671	0	0
T2	764361	632	0	0
T3	209686	990	0	0
T4	186719	138	0	0
T5	51026	2852	0	0
T6	418985	0	0	0
T7	496708	2166	0	0
T8	20870	942	0	0
T9	148757	210	0	0
T10	530854	5503	0	0
T11	0	2811	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	997335	0	0
T1	50501	113	0	0
T2	764361	117	0	0
T3	209686	244	0	0
T4	186719	8	0	0
T5	51026	1629	0	0
T6	418985	0	0	0
T7	496708	234	0	0
T8	20870	173	0	0
T9	148757	19	0	0
T10	530854	1145	0	0
T11	0	843	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	204417	0	0
T1	50501	96	0	0
T2	764361	99	0	0
T3	209686	196	0	0
T4	186719	8	0	0
T5	51026	669	0	0
T6	418985	0	0	0
T7	496708	11	0	0
T8	20870	53	0	0
T9	148757	17	0	0
T10	530854	1030	0	0
T11	0	604	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	214773	0	0
GntImpliesValid_A	432396691	214773	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	214773	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3005493	0	0
ReadyAndValidImplyGrant_A	432396691	214773	0	0
ReqAndReadyImplyGrant_A	432396691	214773	0	0
ReqImpliesValid_A	432396691	537012	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	214773	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3005493	0	0
T1	50501	811	0	0
T2	764361	503	0	0
T3	209686	756	0	0
T4	186719	23	0	0
T5	51026	420	0	0
T6	418985	1995	0	0
T7	496708	3896	0	0
T8	20870	573	0	0
T9	148757	77	0	0
T10	530854	12550	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	537012	0	0
T1	50501	145	0	0
T2	764361	140	0	0
T3	209686	239	0	0
T4	186719	5	0	0
T5	51026	422	0	0
T6	418985	1282	0	0
T7	496708	222	0	0
T8	20870	80	0	0
T9	148757	20	0	0
T10	530854	6353	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214773	0	0
T1	50501	105	0	0
T2	764361	122	0	0
T3	209686	183	0	0
T4	186719	5	0	0
T5	51026	414	0	0
T6	418985	576	0	0
T7	496708	14	0	0
T8	20870	69	0	0
T9	148757	16	0	0
T10	530854	1996	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	212423	0	0
GntImpliesValid_A	432396691	212423	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	212423	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3007257	0	0
ReadyAndValidImplyGrant_A	432396691	212423	0	0
ReqAndReadyImplyGrant_A	432396691	212423	0	0
ReqImpliesValid_A	432396691	518124	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	212423	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3007257	0	0
T1	50501	792	0	0
T2	764361	355	0	0
T3	209686	937	0	0
T4	186719	77	0	0
T5	51026	407	0	0
T6	418985	1	0	0
T7	496708	2063	0	0
T8	20870	574	0	0
T9	148757	56	0	0
T10	530854	9634	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	518124	0	0
T1	50501	129	0	0
T2	764361	94	0	0
T3	209686	271	0	0
T4	186719	15	0	0
T5	51026	411	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	88	0	0
T9	148757	10	0	0
T10	530854	4719	0	0
T11	0	660	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	212423	0	0
T1	50501	104	0	0
T2	764361	85	0	0
T3	209686	217	0	0
T4	186719	15	0	0
T5	51026	402	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	1534	0	0
T11	0	638	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	223356	0	0
GntImpliesValid_A	432396691	223356	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	223356	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3043671	0	0
ReadyAndValidImplyGrant_A	432396691	223356	0	0
ReqAndReadyImplyGrant_A	432396691	223356	0	0
ReqImpliesValid_A	432396691	629523	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	223356	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3043671	0	0
T1	50501	836	0	0
T2	764361	451	0	0
T3	209686	888	0	0
T4	186719	63	0	0
T5	51026	769	0	0
T6	418985	1511	0	0
T7	496708	5478	0	0
T8	20870	400	0	0
T9	148757	43	0	0
T10	530854	13366	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	629523	0	0
T1	50501	142	0	0
T2	764361	132	0	0
T3	209686	212	0	0
T4	186719	10	0	0
T5	51026	2159	0	0
T6	418985	1164	0	0
T7	496708	19	0	0
T8	20870	58	0	0
T9	148757	7	0	0
T10	530854	6549	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	223356	0	0
T1	50501	99	0	0
T2	764361	113	0	0
T3	209686	199	0	0
T4	186719	10	0	0
T5	51026	1457	0	0
T6	418985	468	0	0
T7	496708	19	0	0
T8	20870	53	0	0
T9	148757	7	0	0
T10	530854	2095	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	214848	0	0
GntImpliesValid_A	432396691	214848	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	214848	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2958435	0	0
ReadyAndValidImplyGrant_A	432396691	214848	0	0
ReqAndReadyImplyGrant_A	432396691	214848	0	0
ReqImpliesValid_A	432396691	544917	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	214848	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2958435	0	0
T1	50501	676	0	0
T2	764361	485	0	0
T3	209686	1005	0	0
T4	186719	49	0	0
T5	51026	1168	0	0
T6	418985	1	0	0
T7	496708	5198	0	0
T8	20870	447	0	0
T9	148757	63	0	0
T10	530854	13163	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	544917	0	0
T1	50501	101	0	0
T2	764361	137	0	0
T3	209686	261	0	0
T4	186719	12	0	0
T5	51026	1658	0	0
T6	418985	0	0	0
T7	496708	264	0	0
T8	20870	88	0	0
T9	148757	25	0	0
T10	530854	6465	0	0
T11	0	1265	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	214848	0	0
T1	50501	91	0	0
T2	764361	106	0	0
T3	209686	223	0	0
T4	186719	11	0	0
T5	51026	1406	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	60	0	0
T9	148757	20	0	0
T10	530854	1998	0	0
T11	0	1173	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	216526	0	0
GntImpliesValid_A	432396691	216526	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	216526	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3025901	0	0
ReadyAndValidImplyGrant_A	432396691	216526	0	0
ReqAndReadyImplyGrant_A	432396691	216526	0	0
ReqImpliesValid_A	432396691	547456	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	216526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3025901	0	0
T1	50501	860	0	0
T2	764361	332	0	0
T3	209686	952	0	0
T4	186719	61	0	0
T5	51026	379	0	0
T6	418985	1	0	0
T7	496708	4517	0	0
T8	20870	464	0	0
T9	148757	90	0	0
T10	530854	11303	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	547456	0	0
T1	50501	133	0	0
T2	764361	108	0	0
T3	209686	320	0	0
T4	186719	13	0	0
T5	51026	393	0	0
T6	418985	0	0	0
T7	496708	240	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	3785	0	0
T11	0	1153	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216526	0	0
T1	50501	108	0	0
T2	764361	83	0	0
T3	209686	235	0	0
T4	186719	13	0	0
T5	51026	379	0	0
T6	418985	0	0	0
T7	496708	13	0	0
T8	20870	56	0	0
T9	148757	17	0	0
T10	530854	1644	0	0
T11	0	1061	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	225180	0	0
GntImpliesValid_A	432396691	225180	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	225180	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2932357	0	0
ReadyAndValidImplyGrant_A	432396691	225180	0	0
ReqAndReadyImplyGrant_A	432396691	225180	0	0
ReqImpliesValid_A	432396691	586380	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	225180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2932357	0	0
T1	50501	705	0	0
T2	764361	360	0	0
T3	209686	726	0	0
T4	186719	61	0	0
T5	51026	399	0	0
T6	418985	1	0	0
T7	496708	2434	0	0
T8	20870	352	0	0
T9	148757	40	0	0
T10	530854	9859	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	586380	0	0
T1	50501	89	0	0
T2	764361	98	0	0
T3	209686	214	0	0
T4	186719	13	0	0
T5	51026	411	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	66	0	0
T9	148757	10	0	0
T10	530854	3396	0	0
T11	0	651	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225180	0	0
T1	50501	84	0	0
T2	764361	89	0	0
T3	209686	179	0	0
T4	186719	13	0	0
T5	51026	398	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	53	0	0
T9	148757	10	0	0
T10	530854	1464	0	0
T11	0	625	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	216502	0	0
GntImpliesValid_A	432396691	216502	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	216502	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3056706	0	0
ReadyAndValidImplyGrant_A	432396691	216502	0	0
ReqAndReadyImplyGrant_A	432396691	216502	0	0
ReqImpliesValid_A	432396691	536566	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	216502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3056706	0	0
T1	50501	607	0	0
T2	764361	417	0	0
T3	209686	758	0	0
T4	186719	16	0	0
T5	51026	745	0	0
T6	418985	1256	0	0
T7	496708	4206	0	0
T8	20870	376	0	0
T9	148757	51	0	0
T10	530854	13183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	536566	0	0
T1	50501	84	0	0
T2	764361	111	0	0
T3	209686	245	0	0
T4	186719	4	0	0
T5	51026	1922	0	0
T6	418985	1120	0	0
T7	496708	13	0	0
T8	20870	64	0	0
T9	148757	12	0	0
T10	530854	6535	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	216502	0	0
T1	50501	78	0	0
T2	764361	90	0	0
T3	209686	192	0	0
T4	186719	4	0	0
T5	51026	1327	0	0
T6	418985	429	0	0
T7	496708	13	0	0
T8	20870	55	0	0
T9	148757	12	0	0
T10	530854	2094	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	219003	0	0
GntImpliesValid_A	432396691	219003	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	219003	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3008303	0	0
ReadyAndValidImplyGrant_A	432396691	219003	0	0
ReqAndReadyImplyGrant_A	432396691	219003	0	0
ReqImpliesValid_A	432396691	547892	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	219003	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3008303	0	0
T1	50501	754	0	0
T2	764361	379	0	0
T3	209686	970	0	0
T4	186719	58	0	0
T5	51026	478	0	0
T6	418985	1	0	0
T7	496708	1791	0	0
T8	20870	466	0	0
T9	148757	40	0	0
T10	530854	10999	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	547892	0	0
T1	50501	111	0	0
T2	764361	93	0	0
T3	209686	266	0	0
T4	186719	11	0	0
T5	51026	1490	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	141	0	0
T9	148757	12	0	0
T10	530854	3849	0	0
T11	0	643	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	219003	0	0
T1	50501	91	0	0
T2	764361	88	0	0
T3	209686	214	0	0
T4	186719	11	0	0
T5	51026	977	0	0
T6	418985	0	0	0
T7	496708	6	0	0
T8	20870	71	0	0
T9	148757	12	0	0
T10	530854	1597	0	0
T11	0	621	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	230816	0	0
GntImpliesValid_A	432396691	230816	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	230816	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	3083996	0	0
ReadyAndValidImplyGrant_A	432396691	230816	0	0
ReqAndReadyImplyGrant_A	432396691	230816	0	0
ReqImpliesValid_A	432396691	577956	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	230816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	3083996	0	0
T1	50501	1349	0	0
T2	764361	491	0	0
T3	209686	856	0	0
T4	186719	8	0	0
T5	51026	481	0	0
T6	418985	1385	0	0
T7	496708	2884	0	0
T8	20870	372	0	0
T9	148757	74	0	0
T10	530854	10798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	577956	0	0
T1	50501	323	0	0
T2	764361	130	0	0
T3	209686	280	0	0
T4	186719	3	0	0
T5	51026	499	0	0
T6	418985	1101	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	3567	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	230816	0	0
T1	50501	184	0	0
T2	764361	104	0	0
T3	209686	222	0	0
T4	186719	3	0	0
T5	51026	483	0	0
T6	418985	453	0	0
T7	496708	7	0	0
T8	20870	54	0	0
T9	148757	16	0	0
T10	530854	1585	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	210751	0	0
GntImpliesValid_A	432396691	210751	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	210751	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2991834	0	0
ReadyAndValidImplyGrant_A	432396691	210751	0	0
ReqAndReadyImplyGrant_A	432396691	210751	0	0
ReqImpliesValid_A	432396691	556115	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	210751	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2991834	0	0
T1	50501	629	0	0
T2	764361	404	0	0
T3	209686	684	0	0
T4	186719	31	0	0
T5	51026	456	0	0
T6	418985	1602	0	0
T7	496708	3534	0	0
T8	20870	448	0	0
T9	148757	57	0	0
T10	530854	10377	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	556115	0	0
T1	50501	83	0	0
T2	764361	112	0	0
T3	209686	197	0	0
T4	186719	8	0	0
T5	51026	734	0	0
T6	418985	1280	0	0
T7	496708	680	0	0
T8	20870	56	0	0
T9	148757	16	0	0
T10	530854	3629	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	210751	0	0
T1	50501	83	0	0
T2	764361	88	0	0
T3	209686	174	0	0
T4	186719	8	0	0
T5	51026	588	0	0
T6	418985	521	0	0
T7	496708	13	0	0
T8	20870	50	0	0
T9	148757	15	0	0
T10	530854	1539	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	228051	0	0
GntImpliesValid_A	432396691	228051	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	228051	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2999770	0	0
ReadyAndValidImplyGrant_A	432396691	228051	0	0
ReqAndReadyImplyGrant_A	432396691	228051	0	0
ReqImpliesValid_A	432396691	612348	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	228051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2999770	0	0
T1	50501	523	0	0
T2	764361	387	0	0
T3	209686	898	0	0
T4	186719	41	0	0
T5	51026	587	0	0
T6	418985	1	0	0
T7	496708	3203	0	0
T8	20870	345	0	0
T9	148757	40	0	0
T10	530854	7815	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	612348	0	0
T1	50501	118	0	0
T2	764361	118	0	0
T3	209686	252	0	0
T4	186719	10	0	0
T5	51026	1087	0	0
T6	418985	0	0	0
T7	496708	617	0	0
T8	20870	83	0	0
T9	148757	11	0	0
T10	530854	1215	0	0
T11	0	679	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	228051	0	0
T1	50501	80	0	0
T2	764361	99	0	0
T3	209686	200	0	0
T4	186719	10	0	0
T5	51026	830	0	0
T6	418985	0	0	0
T7	496708	10	0	0
T8	20870	51	0	0
T9	148757	10	0	0
T10	530854	1039	0	0
T11	0	658	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	225780	0	0
GntImpliesValid_A	432396691	225780	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	225780	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2992622	0	0
ReadyAndValidImplyGrant_A	432396691	225780	0	0
ReqAndReadyImplyGrant_A	432396691	225780	0	0
ReqImpliesValid_A	432396691	604097	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	225780	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2992622	0	0
T1	50501	866	0	0
T2	764361	363	0	0
T3	209686	939	0	0
T4	186719	21	0	0
T5	51026	669	0	0
T6	418985	1574	0	0
T7	496708	4388	0	0
T8	20870	426	0	0
T9	148757	95	0	0
T10	530854	8681	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	604097	0	0
T1	50501	151	0	0
T2	764361	79	0	0
T3	209686	258	0	0
T4	186719	5	0	0
T5	51026	1746	0	0
T6	418985	1212	0	0
T7	496708	257	0	0
T8	20870	86	0	0
T9	148757	22	0	0
T10	530854	3082	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	225780	0	0
T1	50501	111	0	0
T2	764361	75	0	0
T3	209686	214	0	0
T4	186719	5	0	0
T5	51026	1201	0	0
T6	418985	494	0	0
T7	496708	13	0	0
T8	20870	59	0	0
T9	148757	19	0	0
T10	530854	1517	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	220529	0	0
GntImpliesValid_A	432396691	220529	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	220529	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2894669	0	0
ReadyAndValidImplyGrant_A	432396691	220529	0	0
ReqAndReadyImplyGrant_A	432396691	220529	0	0
ReqImpliesValid_A	432396691	569672	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	220529	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2894669	0	0
T1	50501	705	0	0
T2	764361	430	0	0
T3	209686	925	0	0
T4	186719	60	0	0
T5	51026	797	0	0
T6	418985	1726	0	0
T7	496708	4154	0	0
T8	20870	446	0	0
T9	148757	59	0	0
T10	530854	7952	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	569672	0	0
T1	50501	183	0	0
T2	764361	123	0	0
T3	209686	292	0	0
T4	186719	12	0	0
T5	51026	1091	0	0
T6	418985	1265	0	0
T7	496708	441	0	0
T8	20870	75	0	0
T9	148757	15	0	0
T10	530854	1182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	220529	0	0
T1	50501	110	0	0
T2	764361	99	0	0
T3	209686	225	0	0
T4	186719	12	0	0
T5	51026	937	0	0
T6	418985	517	0	0
T7	496708	14	0	0
T8	20870	54	0	0
T9	148757	13	0	0
T10	530854	1038	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	202688	0	0
GntImpliesValid_A	432396691	202688	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	202688	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	2931598	0	0
ReadyAndValidImplyGrant_A	432396691	202688	0	0
ReqAndReadyImplyGrant_A	432396691	202688	0	0
ReqImpliesValid_A	432396691	519658	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	0	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	202688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2931598	0	0
T1	50501	582	0	0
T2	764361	443	0	0
T3	209686	854	0	0
T4	186719	59	0	0
T5	51026	584	0	0
T6	418985	1	0	0
T7	496708	5277	0	0
T8	20870	357	0	0
T9	148757	61	0	0
T10	530854	8380	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	519658	0	0
T1	50501	87	0	0
T2	764361	131	0	0
T3	209686	253	0	0
T4	186719	27	0	0
T5	51026	713	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	53	0	0
T9	148757	18	0	0
T10	530854	1286	0	0
T11	0	689	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	202688	0	0
T1	50501	85	0	0
T2	764361	100	0	0
T3	209686	214	0	0
T4	186719	16	0	0
T5	51026	642	0	0
T6	418985	0	0	0
T7	496708	15	0	0
T8	20870	44	0	0
T9	148757	15	0	0
T10	530854	1077	0	0
T11	0	657	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	868237	0	0
GntImpliesValid_A	432396691	868237	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	868237	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	11199058	0	0
ReadyAndValidImplyGrant_A	432396691	868237	0	0
ReqAndReadyImplyGrant_A	432396691	868237	0	0
ReqImpliesValid_A	432396691	2274518	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	17080	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	868237	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	11199058	0	0
T1	50501	2398	0	0
T2	764361	1312	0	0
T3	209686	2527	0	0
T4	186719	110	0	0
T5	51026	14	0	0
T6	418985	2003	0	0
T7	496708	19561	0	0
T8	20870	1452	0	0
T9	148757	168	0	0
T10	530854	37531	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	2274518	0	0
T1	50501	496	0	0
T2	764361	541	0	0
T3	209686	1065	0	0
T4	186719	49	0	0
T5	51026	2807	0	0
T6	418985	784	0	0
T7	496708	692	0	0
T8	20870	401	0	0
T9	148757	62	0	0
T10	530854	8320	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	17080	0	900
T5	51026	27	0	1
T6	418985	0	0	1
T7	496708	0	0	1
T8	20870	0	0	1
T9	148757	0	0	1
T10	530854	2	0	1
T11	47221	33	0	1
T12	0	2	0	0
T13	0	17	0	0
T14	0	1	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	163356	0	0	1
T21	1439	0	0	1
T22	213041	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	868237	0	0
T1	50501	369	0	0
T2	764361	390	0	0
T3	209686	807	0	0
T4	186719	35	0	0
T5	51026	2807	0	0
T6	418985	592	0	0
T7	496708	59	0	0
T8	20870	247	0	0
T9	148757	50	0	0
T10	530854	5531	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432396691	432272804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432396691	861054	0	0
GntImpliesValid_A	432396691	861054	0	0
GrantKnown_A	432396691	432272804	0	0
IdxKnown_A	432396691	432272804	0	0
IndexIsCorrect_A	432396691	861054	0	0
LockArbDecision_A	432396691	0	0	0
NoReadyValidNoGrant_A	432396691	362561749	0	0
ReadyAndValidImplyGrant_A	432396691	861054	0	0
ReqAndReadyImplyGrant_A	432396691	861054	0	0
ReqImpliesValid_A	432396691	13236036	0	0
ReqStaysHighUntilGranted0_M	432396691	0	0	0
RoundRobin_A	432396691	27220	0	900
ValidKnown_A	432396691	432272804	0	0
gen_data_port_assertion.DataFlow_A	432396691	861054	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	362561749	0	0
T1	50501	43278	0	0
T2	764361	635481	0	0
T3	209686	174487	0	0
T4	186719	155499	0	0
T5	51026	1	0	0
T6	418985	348215	0	0
T7	496708	474528	0	0
T8	20870	17506	0	0
T9	148757	123567	0	0
T10	530854	443886	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	13236036	0	0
T1	50501	2963	0	0
T2	764361	1731	0	0
T3	209686	3633	0	0
T4	186719	147	0	0
T5	51026	3470	0	0
T6	418985	9001	0	0
T7	496708	21203	0	0
T8	20870	1645	0	0
T9	148757	278	0	0
T10	530854	43918	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	27220	0	900
T5	51026	463	0	1
T6	418985	19	0	1
T7	496708	0	0	1
T8	20870	0	0	1
T9	148757	0	0	1
T10	530854	5	0	1
T11	47221	38	0	1
T12	0	6	0	0
T13	0	11	0	0
T15	0	1	0	0
T16	0	4	0	0
T17	0	1	0	0
T18	0	3	0	0
T20	163356	0	0	1
T21	1439	0	0	1
T22	213041	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	432272804	0	0
T1	50501	50477	0	0
T2	764361	764332	0	0
T3	209686	209685	0	0
T4	186719	186655	0	0
T5	51026	49334	0	0
T6	418985	418976	0	0
T7	496708	496653	0	0
T8	20870	20821	0	0
T9	148757	148657	0	0
T10	530854	530809	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432396691	861054	0	0
T1	50501	373	0	0
T2	764361	393	0	0
T3	209686	793	0	0
T4	186719	36	0	0
T5	51026	3470	0	0
T6	418985	1964	0	0
T7	496708	59	0	0
T8	20870	200	0	0
T9	148757	64	0	0
T10	530854	5459	0	0