Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1540553 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244583 1 T1 11 T2 5 T3 49


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 605739 1 T1 46 T2 31 T3 144
values[0x0] 573563 1 T1 25 T2 3 T3 149
values[0x1] 605834 1 T1 39 T2 27 T3 131


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1190098 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 595038 1 T1 41 T2 26 T3 117


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27145 1 T3 3 T4 7 T5 14
valid_sources[0x01] 28585 1 T3 1 T4 2 T5 14
valid_sources[0x02] 29013 1 T2 4 T3 7 T5 9
valid_sources[0x03] 27534 1 T3 16 T5 12 T6 105
valid_sources[0x04] 28295 1 T1 2 T3 5 T4 2
valid_sources[0x05] 27978 1 T2 1 T3 6 T4 1
valid_sources[0x06] 28552 1 T2 3 T3 6 T5 15
valid_sources[0x07] 28747 1 T2 2 T3 16 T5 19
valid_sources[0x08] 27899 1 T2 1 T3 4 T5 9
valid_sources[0x09] 28180 1 T2 2 T3 4 T5 14
valid_sources[0x0a] 28358 1 T3 5 T4 1 T5 17
valid_sources[0x0b] 27214 1 T3 16 T4 2 T5 13
valid_sources[0x0c] 27664 1 T3 15 T4 1 T5 9
valid_sources[0x0d] 27678 1 T3 6 T4 3 T5 19
valid_sources[0x0e] 28039 1 T3 8 T4 2 T5 10
valid_sources[0x0f] 27250 1 T1 2 T4 4 T5 9
valid_sources[0x10] 28039 1 T1 1 T2 1 T3 4
valid_sources[0x11] 28337 1 T1 3 T2 2 T5 16
valid_sources[0x12] 27478 1 T4 1 T5 15 T6 71
valid_sources[0x13] 28413 1 T1 6 T2 2 T3 4
valid_sources[0x14] 27961 1 T3 6 T5 6 T6 122
valid_sources[0x15] 27360 1 T1 14 T3 3 T5 10
valid_sources[0x16] 28390 1 T4 3 T5 13 T6 59
valid_sources[0x17] 27116 1 T2 1 T3 5 T4 3
valid_sources[0x18] 27601 1 T1 14 T2 2 T3 8
valid_sources[0x19] 29075 1 T2 1 T3 15 T4 5
valid_sources[0x1a] 27914 1 T1 4 T2 1 T3 8
valid_sources[0x1b] 28378 1 T2 1 T3 1 T4 1
valid_sources[0x1c] 28072 1 T1 5 T5 12 T6 61
valid_sources[0x1d] 28318 1 T2 2 T3 2 T4 8
valid_sources[0x1e] 28714 1 T3 8 T4 4 T5 9
valid_sources[0x1f] 27960 1 T4 3 T5 13 T6 72
valid_sources[0x20] 28232 1 T3 17 T4 8 T5 11


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25739 1 T1 1 T2 1 T3 5
values[0x0] all_enables biggest_size 193176 1 T1 9 T2 1 T3 38
values[0x1] all_enables biggest_size 25668 1 T1 1 T2 3 T3 6


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1560916 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 253978 1 T1 20 T2 7 T3 58


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 620763 1 T1 44 T2 26 T3 128
values[0x0] 573381 1 T1 50 T2 4 T3 144
values[0x1] 620750 1 T1 53 T2 29 T3 165


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1199150 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 615744 1 T1 45 T2 21 T3 143


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28849 1 T1 1 T2 1 T3 11
valid_sources[0x01] 28538 1 T2 1 T3 21 T4 2
valid_sources[0x02] 28597 1 T1 3 T3 3 T4 1
valid_sources[0x03] 28810 1 T3 1 T4 1 T5 5
valid_sources[0x04] 28010 1 T1 1 T2 1 T3 5
valid_sources[0x05] 28265 1 T1 2 T4 1 T5 13
valid_sources[0x06] 28900 1 T1 4 T2 1 T4 6
valid_sources[0x07] 28064 1 T1 4 T2 2 T5 22
valid_sources[0x08] 28415 1 T2 4 T4 2 T5 9
valid_sources[0x09] 28225 1 T1 1 T3 26 T4 1
valid_sources[0x0a] 28342 1 T3 19 T4 3 T5 9
valid_sources[0x0b] 28092 1 T1 2 T2 2 T3 4
valid_sources[0x0c] 28641 1 T1 3 T3 11 T5 5
valid_sources[0x0d] 28135 1 T1 1 T2 1 T4 3
valid_sources[0x0e] 28932 1 T1 2 T4 2 T5 13
valid_sources[0x0f] 28453 1 T1 3 T2 1 T4 6
valid_sources[0x10] 28344 1 T1 4 T2 3 T5 8
valid_sources[0x11] 28410 1 T1 4 T2 1 T3 7
valid_sources[0x12] 29042 1 T1 6 T3 1 T4 1
valid_sources[0x13] 28779 1 T3 3 T4 1 T5 13
valid_sources[0x14] 28290 1 T2 1 T4 6 T5 12
valid_sources[0x15] 27957 1 T4 3 T5 8 T6 107
valid_sources[0x16] 28108 1 T1 2 T5 11 T6 46
valid_sources[0x17] 28663 1 T1 5 T3 9 T5 12
valid_sources[0x18] 27902 1 T1 3 T2 1 T4 5
valid_sources[0x19] 27811 1 T1 1 T2 1 T3 5
valid_sources[0x1a] 28894 1 T1 2 T2 2 T4 1
valid_sources[0x1b] 28681 1 T1 1 T2 1 T3 2
valid_sources[0x1c] 28159 1 T1 1 T2 1 T4 1
valid_sources[0x1d] 27843 1 T2 2 T3 2 T4 3
valid_sources[0x1e] 28356 1 T1 4 T3 17 T4 1
valid_sources[0x1f] 28085 1 T3 4 T4 1 T5 15
valid_sources[0x20] 28540 1 T1 2 T2 1 T3 9


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26430 1 T1 2 T2 3 T3 4
values[0x0] all_enables biggest_size 201153 1 T1 16 T2 3 T3 44
values[0x1] all_enables biggest_size 26395 1 T1 2 T2 1 T3 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1554721 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246619 1 T1 7 T2 3 T3 78


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 610434 1 T1 30 T2 35 T3 161
values[0x0] 579111 1 T1 23 T2 3 T3 162
values[0x1] 611795 1 T1 33 T2 26 T3 168


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1201815 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 599525 1 T1 25 T2 19 T3 181


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28110 1 T2 2 T3 4 T4 3
valid_sources[0x01] 29063 1 T2 1 T3 4 T4 4
valid_sources[0x02] 27773 1 T2 1 T3 7 T4 1
valid_sources[0x03] 28052 1 T2 3 T3 12 T4 3
valid_sources[0x04] 28880 1 T1 2 T3 5 T4 3
valid_sources[0x05] 27831 1 T2 2 T3 6 T4 4
valid_sources[0x06] 27969 1 T3 2 T4 1 T5 16
valid_sources[0x07] 28212 1 T1 2 T2 1 T3 8
valid_sources[0x08] 28227 1 T1 1 T3 5 T4 1
valid_sources[0x09] 27726 1 T1 1 T3 5 T4 3
valid_sources[0x0a] 27905 1 T1 2 T3 6 T4 2
valid_sources[0x0b] 28090 1 T1 2 T2 2 T3 2
valid_sources[0x0c] 28202 1 T2 1 T3 12 T4 4
valid_sources[0x0d] 27482 1 T1 4 T2 2 T3 5
valid_sources[0x0e] 28295 1 T1 1 T2 2 T3 4
valid_sources[0x0f] 28027 1 T1 3 T2 1 T3 8
valid_sources[0x10] 28354 1 T2 2 T3 5 T4 3
valid_sources[0x11] 27952 1 T1 1 T3 5 T4 1
valid_sources[0x12] 27929 1 T1 3 T2 2 T3 13
valid_sources[0x13] 28953 1 T1 1 T2 2 T3 11
valid_sources[0x14] 28646 1 T1 2 T3 14 T4 4
valid_sources[0x15] 28130 1 T1 1 T2 1 T3 5
valid_sources[0x16] 28052 1 T3 11 T4 1 T5 17
valid_sources[0x17] 28289 1 T1 1 T3 12 T4 1
valid_sources[0x18] 27955 1 T1 4 T2 2 T3 7
valid_sources[0x19] 28319 1 T2 2 T3 4 T4 2
valid_sources[0x1a] 28480 1 T1 3 T2 2 T3 12
valid_sources[0x1b] 28062 1 T2 1 T3 9 T4 3
valid_sources[0x1c] 27716 1 T1 2 T2 1 T3 9
valid_sources[0x1d] 27999 1 T2 1 T3 13 T4 1
valid_sources[0x1e] 28317 1 T2 3 T3 14 T4 4
valid_sources[0x1f] 28530 1 T3 10 T4 2 T5 14
valid_sources[0x20] 27991 1 T1 3 T2 3 T3 5


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26025 1 T1 1 T3 13 T4 7
values[0x0] all_enables biggest_size 194547 1 T1 6 T3 59 T4 4
values[0x1] all_enables biggest_size 26047 1 T2 3 T3 6 T4 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%