Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7721507	0	0
GntImpliesValid_A	2147483647	7721507	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7721507	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	485415107	0	0
ReadyAndValidImplyGrant_A	2147483647	7721507	0	0
ReqAndReadyImplyGrant_A	2147483647	7721507	0	0
ReqImpliesValid_A	2147483647	35581114	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	39918	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7721507	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	225624	224256	0	0
T2	1020072	1018824	0	0
T3	14648448	14647248	0	0
T4	1973064	1972440	0	0
T5	13538184	13480104	0	0
T6	575352	574752	0	0
T7	314280	313704	0	0
T8	14078472	14076168	0	0
T9	12577080	12575448	0	0
T10	1729296	1728144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	225624	224256	0	0
T2	1020072	1018824	0	0
T3	14648448	14647248	0	0
T4	1973064	1972440	0	0
T5	13538184	13480104	0	0
T6	575352	574752	0	0
T7	314280	313704	0	0
T8	14078472	14076168	0	0
T9	12577080	12575448	0	0
T10	1729296	1728144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	225624	224256	0	0
T2	1020072	1018824	0	0
T3	14648448	14647248	0	0
T4	1973064	1972440	0	0
T5	13538184	13480104	0	0
T6	575352	574752	0	0
T7	314280	313704	0	0
T8	14078472	14076168	0	0
T9	12577080	12575448	0	0
T10	1729296	1728144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	485415107	0	0
T1	225624	10613	0	0
T2	1020072	63474	0	0
T3	14648448	987140	0	0
T4	1973064	130094	0	0
T5	13538184	787014	0	0
T6	575352	1909	0	0
T7	314280	977	0	0
T8	14078472	813703	0	0
T9	12577080	743488	0	0
T10	1729296	111966	0	0
T11	0	517	0	0
T12	0	10995	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35581114	0	0
T1	225624	805	0	0
T2	1020072	9093	0	0
T3	14648448	89642	0	0
T4	1973064	18931	0	0
T5	13538184	103318	0	0
T6	575352	28215	0	0
T7	314280	14525	0	0
T8	14078472	257288	0	0
T9	12577080	156577	0	0
T10	1729296	15523	0	0
T11	0	266	0	0
T12	0	2198	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39918	0	21600
T5	1128182	10	0	2
T6	47946	0	0	2
T7	26190	297	0	2
T8	1173206	16	0	2
T9	1048090	34	0	2
T10	144108	2	0	2
T11	413978	0	0	2
T12	134104	154	0	2
T13	741794	0	0	2
T14	0	39	0	0
T15	0	51	0	0
T16	0	14	0	0
T17	0	24	0	0
T18	0	5	0	0
T19	0	1	0	0
T20	127950	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	225624	224256	0	0
T2	1020072	1018824	0	0
T3	14648448	14647248	0	0
T4	1973064	1972440	0	0
T5	13538184	13480104	0	0
T6	575352	574752	0	0
T7	314280	313704	0	0
T8	14078472	14076168	0	0
T9	12577080	12575448	0	0
T10	1729296	1728144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7721507	0	0
T1	225624	342	0	0
T2	1020072	3862	0	0
T3	14648448	1352	0	0
T4	1973064	8050	0	0
T5	13538184	43367	0	0
T6	575352	13594	0	0
T7	314280	7885	0	0
T8	14078472	49809	0	0
T9	12577080	51959	0	0
T10	1729296	6273	0	0
T11	0	193	0	0
T12	0	1090	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	853216	0	0
GntImpliesValid_A	445948577	853216	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	853216	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	12785157	0	0
ReadyAndValidImplyGrant_A	445948577	853216	0	0
ReqAndReadyImplyGrant_A	445948577	853216	0	0
ReqImpliesValid_A	445948577	2460642	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	853216	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	12785157	0	0
T1	9401	274	0	0
T2	42503	3266	0	0
T3	610352	46052	0	0
T4	82211	6616	0	0
T5	564091	32771	0	0
T6	23973	764	0	0
T7	13095	399	0	0
T8	586603	33819	0	0
T9	524045	37713	0	0
T10	72054	4652	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	2460642	0	0
T1	9401	66	0	0
T2	42503	713	0	0
T3	610352	3070	0	0
T4	82211	1560	0	0
T5	564091	8357	0	0
T6	23973	3045	0	0
T7	13095	726	0	0
T8	586603	16137	0	0
T9	524045	7682	0	0
T10	72054	1093	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	853216	0	0
T1	9401	41	0	0
T2	42503	430	0	0
T3	610352	150	0	0
T4	82211	886	0	0
T5	564091	4916	0	0
T6	23973	1904	0	0
T7	13095	562	0	0
T8	586603	5285	0	0
T9	524045	5016	0	0
T10	72054	688	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	862814	0	0
GntImpliesValid_A	445948577	862814	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	862814	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	12577366	0	0
ReadyAndValidImplyGrant_A	445948577	862814	0	0
ReqAndReadyImplyGrant_A	445948577	862814	0	0
ReqImpliesValid_A	445948577	2439894	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	862814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	12577366	0	0
T1	9401	345	0	0
T2	42503	3238	0	0
T3	610352	48990	0	0
T4	82211	5618	0	0
T5	564091	37880	0	0
T6	23973	758	0	0
T7	13095	395	0	0
T8	586603	33241	0	0
T9	524045	47721	0	0
T10	72054	5317	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	2439894	0	0
T1	9401	79	0	0
T2	42503	744	0	0
T3	610352	4363	0	0
T4	82211	1334	0	0
T5	564091	13365	0	0
T6	23973	1363	0	0
T7	13095	2040	0	0
T8	586603	14518	0	0
T9	524045	21996	0	0
T10	72054	1222	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	862814	0	0
T1	9401	46	0	0
T2	42503	449	0	0
T3	610352	145	0	0
T4	82211	838	0	0
T5	564091	6404	0	0
T6	23973	1060	0	0
T7	13095	1217	0	0
T8	586603	5139	0	0
T9	524045	7317	0	0
T10	72054	731	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	206920	0	0
GntImpliesValid_A	445948577	206920	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	206920	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3130477	0	0
ReadyAndValidImplyGrant_A	445948577	206920	0	0
ReqAndReadyImplyGrant_A	445948577	206920	0	0
ReqImpliesValid_A	445948577	524742	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	206920	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3130477	0	0
T1	9401	108	0	0
T2	42503	863	0	0
T3	610352	9513	0	0
T4	82211	1822	0	0
T5	564091	9689	0	0
T6	23973	2	0	0
T7	13095	75	0	0
T8	586603	8626	0	0
T9	524045	9612	0	0
T10	72054	1178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	524742	0	0
T1	9401	24	0	0
T2	42503	152	0	0
T3	610352	30	0	0
T4	82211	340	0	0
T5	564091	2125	0	0
T6	23973	1001	0	0
T7	13095	900	0	0
T8	586603	2587	0	0
T9	524045	4872	0	0
T10	72054	216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206920	0	0
T1	9401	13	0	0
T2	42503	112	0	0
T3	610352	30	0	0
T4	82211	247	0	0
T5	564091	1412	0	0
T6	23973	501	0	0
T7	13095	487	0	0
T8	586603	1230	0	0
T9	524045	1491	0	0
T10	72054	165	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217589	0	0
GntImpliesValid_A	445948577	217589	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217589	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3133465	0	0
ReadyAndValidImplyGrant_A	445948577	217589	0	0
ReqAndReadyImplyGrant_A	445948577	217589	0	0
ReqImpliesValid_A	445948577	575487	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3133465	0	0
T1	9401	55	0	0
T2	42503	845	0	0
T3	610352	13757	0	0
T4	82211	1551	0	0
T5	564091	6802	0	0
T6	23973	2	0	0
T7	13095	1	0	0
T8	586603	11451	0	0
T9	524045	10469	0	0
T10	72054	1397	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	575487	0	0
T1	9401	6	0	0
T2	42503	158	0	0
T3	610352	1565	0	0
T4	82211	310	0	0
T5	564091	1050	0	0
T6	23973	995	0	0
T7	13095	0	0	0
T8	586603	8870	0	0
T9	524045	3361	0	0
T10	72054	218	0	0
T11	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217589	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	42	0	0
T4	82211	229	0	0
T5	564091	904	0	0
T6	23973	498	0	0
T7	13095	0	0	0
T8	586603	2042	0	0
T9	524045	1508	0	0
T10	72054	175	0	0
T11	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217257	0	0
GntImpliesValid_A	445948577	217257	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217257	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	5747846	0	0
ReadyAndValidImplyGrant_A	445948577	217257	0	0
ReqAndReadyImplyGrant_A	445948577	217257	0	0
ReqImpliesValid_A	445948577	1359652	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217257	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	5747846	0	0
T1	9401	60	0	0
T2	42503	2458	0	0
T3	610352	14776	0	0
T4	82211	2853	0	0
T5	564091	23884	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	14515	0	0
T9	524045	4846	0	0
T10	72054	1762	0	0
T11	0	103	0	0
T12	0	10995	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	1359652	0	0
T1	9401	6	0	0
T2	42503	300	0	0
T3	610352	186	0	0
T4	82211	519	0	0
T5	564091	2825	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1250	0	0
T9	524045	1100	0	0
T10	72054	221	0	0
T11	0	12	0	0
T12	0	1653	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217257	0	0
T1	9401	6	0	0
T2	42503	103	0	0
T3	610352	20	0	0
T4	82211	233	0	0
T5	564091	1067	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	685	0	0
T9	524045	998	0	0
T10	72054	165	0	0
T11	0	12	0	0
T12	0	559	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	219931	0	0
GntImpliesValid_A	445948577	219931	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	219931	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	5698555	0	0
ReadyAndValidImplyGrant_A	445948577	219931	0	0
ReqAndReadyImplyGrant_A	445948577	219931	0	0
ReqImpliesValid_A	445948577	1270093	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	219931	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	5698555	0	0
T1	9401	176	0	0
T2	42503	2052	0	0
T3	610352	28950	0	0
T4	82211	1897	0	0
T5	564091	16816	0	0
T6	23973	0	0	0
T7	13095	47	0	0
T8	586603	49336	0	0
T9	524045	26492	0	0
T10	72054	3779	0	0
T11	0	160	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	1270093	0	0
T1	9401	9	0	0
T2	42503	232	0	0
T3	610352	5515	0	0
T4	82211	383	0	0
T5	564091	1921	0	0
T6	23973	0	0	0
T7	13095	2374	0	0
T8	586603	52080	0	0
T9	524045	11630	0	0
T10	72054	480	0	0
T11	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219931	0	0
T1	9401	9	0	0
T2	42503	106	0	0
T3	610352	47	0	0
T4	82211	249	0	0
T5	564091	961	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	2977	0	0
T9	524045	2397	0	0
T10	72054	168	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	215781	0	0
GntImpliesValid_A	445948577	215781	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	215781	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	5259269	0	0
ReadyAndValidImplyGrant_A	445948577	215781	0	0
ReqAndReadyImplyGrant_A	445948577	215781	0	0
ReqImpliesValid_A	445948577	1170433	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	215781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	5259269	0	0
T1	9401	111	0	0
T2	42503	1136	0	0
T3	610352	9556	0	0
T4	82211	6044	0	0
T5	564091	16628	0	0
T6	23973	42	0	0
T7	13095	0	0	0
T8	586603	9978	0	0
T9	524045	6250	0	0
T10	72054	1741	0	0
T11	0	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	1170433	0	0
T1	9401	34	0	0
T2	42503	204	0	0
T3	610352	242	0	0
T4	82211	744	0	0
T5	564091	1535	0	0
T6	23973	5348	0	0
T7	13095	0	0	0
T8	586603	16468	0	0
T9	524045	1135	0	0
T10	72054	206	0	0
T11	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	215781	0	0
T1	9401	8	0	0
T2	42503	103	0	0
T3	610352	29	0	0
T4	82211	205	0	0
T5	564091	880	0	0
T6	23973	932	0	0
T7	13095	0	0	0
T8	586603	1588	0	0
T9	524045	1002	0	0
T10	72054	162	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	212211	0	0
GntImpliesValid_A	445948577	212211	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	212211	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	5665184	0	0
ReadyAndValidImplyGrant_A	445948577	212211	0	0
ReqAndReadyImplyGrant_A	445948577	212211	0	0
ReqImpliesValid_A	445948577	1324523	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	212211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	5665184	0	0
T1	9401	72	0	0
T2	42503	1082	0	0
T3	610352	43724	0	0
T4	82211	5584	0	0
T5	564091	12216	0	0
T6	23973	21	0	0
T7	13095	0	0	0
T8	586603	33225	0	0
T9	524045	7825	0	0
T10	72054	10176	0	0
T11	0	174	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	1324523	0	0
T1	9401	41	0	0
T2	42503	153	0	0
T3	610352	3022	0	0
T4	82211	822	0	0
T5	564091	1249	0	0
T6	23973	2379	0	0
T7	13095	0	0	0
T8	586603	26303	0	0
T9	524045	2723	0	0
T10	72054	2218	0	0
T11	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212211	0	0
T1	9401	10	0	0
T2	42503	113	0	0
T3	610352	31	0	0
T4	82211	233	0	0
T5	564091	837	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	2477	0	0
T9	524045	1462	0	0
T10	72054	184	0	0
T11	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	212467	0	0
GntImpliesValid_A	445948577	212467	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	212467	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3155668	0	0
ReadyAndValidImplyGrant_A	445948577	212467	0	0
ReqAndReadyImplyGrant_A	445948577	212467	0	0
ReqImpliesValid_A	445948577	576207	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	212467	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3155668	0	0
T1	9401	30	0	0
T2	42503	865	0	0
T3	610352	9102	0	0
T4	82211	1651	0	0
T5	564091	9811	0	0
T6	23973	43	0	0
T7	13095	1	0	0
T8	586603	7039	0	0
T9	524045	10462	0	0
T10	72054	1432	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	576207	0	0
T1	9401	5	0	0
T2	42503	130	0	0
T3	610352	582	0	0
T4	82211	332	0	0
T5	564091	3168	0	0
T6	23973	924	0	0
T7	13095	0	0	0
T8	586603	2489	0	0
T9	524045	4526	0	0
T10	72054	259	0	0
T11	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212467	0	0
T1	9401	5	0	0
T2	42503	113	0	0
T3	610352	27	0	0
T4	82211	228	0	0
T5	564091	1397	0	0
T6	23973	483	0	0
T7	13095	0	0	0
T8	586603	1173	0	0
T9	524045	1606	0	0
T10	72054	177	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	219449	0	0
GntImpliesValid_A	445948577	219449	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	219449	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3129570	0	0
ReadyAndValidImplyGrant_A	445948577	219449	0	0
ReqAndReadyImplyGrant_A	445948577	219449	0	0
ReqImpliesValid_A	445948577	574746	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	219449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3129570	0	0
T1	9401	94	0	0
T2	42503	809	0	0
T3	610352	13968	0	0
T4	82211	1622	0	0
T5	564091	6330	0	0
T6	23973	2	0	0
T7	13095	6	0	0
T8	586603	5767	0	0
T9	524045	7976	0	0
T10	72054	1192	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	574746	0	0
T1	9401	9	0	0
T2	42503	150	0	0
T3	610352	1294	0	0
T4	82211	327	0	0
T5	564091	979	0	0
T6	23973	1137	0	0
T7	13095	871	0	0
T8	586603	3491	0	0
T9	524045	1238	0	0
T10	72054	284	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	219449	0	0
T1	9401	9	0	0
T2	42503	109	0	0
T3	610352	44	0	0
T4	82211	216	0	0
T5	564091	849	0	0
T6	23973	569	0	0
T7	13095	438	0	0
T8	586603	989	0	0
T9	524045	1072	0	0
T10	72054	174	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	214364	0	0
GntImpliesValid_A	445948577	214364	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	214364	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3159914	0	0
ReadyAndValidImplyGrant_A	445948577	214364	0	0
ReqAndReadyImplyGrant_A	445948577	214364	0	0
ReqImpliesValid_A	445948577	592747	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	214364	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3159914	0	0
T1	9401	40	0	0
T2	42503	734	0	0
T3	610352	11711	0	0
T4	82211	1701	0	0
T5	564091	7146	0	0
T6	23973	1	0	0
T7	13095	2	0	0
T8	586603	5049	0	0
T9	524045	10211	0	0
T10	72054	1274	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	592747	0	0
T1	9401	5	0	0
T2	42503	127	0	0
T3	610352	296	0	0
T4	82211	374	0	0
T5	564091	1122	0	0
T6	23973	0	0	0
T7	13095	1007	0	0
T8	586603	819	0	0
T9	524045	4562	0	0
T10	72054	210	0	0
T11	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	214364	0	0
T1	9401	5	0	0
T2	42503	96	0	0
T3	610352	39	0	0
T4	82211	237	0	0
T5	564091	942	0	0
T6	23973	0	0	0
T7	13095	504	0	0
T8	586603	671	0	0
T9	524045	1555	0	0
T10	72054	176	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	208060	0	0
GntImpliesValid_A	445948577	208060	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	208060	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3174575	0	0
ReadyAndValidImplyGrant_A	445948577	208060	0	0
ReqAndReadyImplyGrant_A	445948577	208060	0	0
ReqImpliesValid_A	445948577	576364	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	208060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3174575	0	0
T1	9401	33	0	0
T2	42503	777	0	0
T3	610352	14679	0	0
T4	82211	1848	0	0
T5	564091	8153	0	0
T6	23973	2	0	0
T7	13095	1	0	0
T8	586603	6105	0	0
T9	524045	14439	0	0
T10	72054	1200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	576364	0	0
T1	9401	6	0	0
T2	42503	142	0	0
T3	610352	1013	0	0
T4	82211	362	0	0
T5	564091	1405	0	0
T6	23973	931	0	0
T7	13095	0	0	0
T8	586603	5628	0	0
T9	524045	5428	0	0
T10	72054	237	0	0
T11	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	208060	0	0
T1	9401	6	0	0
T2	42503	107	0	0
T3	610352	45	0	0
T4	82211	257	0	0
T5	564091	1085	0	0
T6	23973	466	0	0
T7	13095	0	0	0
T8	586603	1197	0	0
T9	524045	2474	0	0
T10	72054	174	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217924	0	0
GntImpliesValid_A	445948577	217924	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217924	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3165609	0	0
ReadyAndValidImplyGrant_A	445948577	217924	0	0
ReqAndReadyImplyGrant_A	445948577	217924	0	0
ReqImpliesValid_A	445948577	635951	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3165609	0	0
T1	9401	67	0	0
T2	42503	758	0	0
T3	610352	8950	0	0
T4	82211	1569	0	0
T5	564091	6871	0	0
T6	23973	1	0	0
T7	13095	1	0	0
T8	586603	8137	0	0
T9	524045	7526	0	0
T10	72054	1137	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	635951	0	0
T1	9401	7	0	0
T2	42503	152	0	0
T3	610352	28	0	0
T4	82211	276	0	0
T5	564091	1156	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	3672	0	0
T9	524045	1320	0	0
T10	72054	264	0	0
T11	0	12	0	0
T12	0	545	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217924	0	0
T1	9401	7	0	0
T2	42503	111	0	0
T3	610352	28	0	0
T4	82211	230	0	0
T5	564091	924	0	0
T6	23973	0	0	0
T7	13095	0	0	0
T8	586603	1219	0	0
T9	524045	1005	0	0
T10	72054	153	0	0
T11	0	10	0	0
T12	0	531	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	205459	0	0
GntImpliesValid_A	445948577	205459	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	205459	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3078270	0	0
ReadyAndValidImplyGrant_A	445948577	205459	0	0
ReqAndReadyImplyGrant_A	445948577	205459	0	0
ReqImpliesValid_A	445948577	528851	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	205459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3078270	0	0
T1	9401	81	0	0
T2	42503	731	0	0
T3	610352	15158	0	0
T4	82211	1682	0	0
T5	564091	10161	0	0
T6	23973	1	0	0
T7	13095	2	0	0
T8	586603	9814	0	0
T9	524045	7842	0	0
T10	72054	1388	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	528851	0	0
T1	9401	8	0	0
T2	42503	140	0	0
T3	610352	146	0	0
T4	82211	276	0	0
T5	564091	2895	0	0
T6	23973	0	0	0
T7	13095	991	0	0
T8	586603	5593	0	0
T9	524045	1424	0	0
T10	72054	242	0	0
T11	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	205459	0	0
T1	9401	8	0	0
T2	42503	102	0	0
T3	610352	41	0	0
T4	82211	227	0	0
T5	564091	1436	0	0
T6	23973	0	0	0
T7	13095	496	0	0
T8	586603	1590	0	0
T9	524045	1048	0	0
T10	72054	186	0	0
T11	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	206273	0	0
GntImpliesValid_A	445948577	206273	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	206273	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3141849	0	0
ReadyAndValidImplyGrant_A	445948577	206273	0	0
ReqAndReadyImplyGrant_A	445948577	206273	0	0
ReqImpliesValid_A	445948577	547944	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	206273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3141849	0	0
T1	9401	96	0	0
T2	42503	771	0	0
T3	610352	10140	0	0
T4	82211	1366	0	0
T5	564091	8793	0	0
T6	23973	64	0	0
T7	13095	1	0	0
T8	586603	5561	0	0
T9	524045	7594	0	0
T10	72054	1219	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	547944	0	0
T1	9401	10	0	0
T2	42503	174	0	0
T3	610352	2032	0	0
T4	82211	293	0	0
T5	564091	1870	0	0
T6	23973	2055	0	0
T7	13095	0	0	0
T8	586603	4439	0	0
T9	524045	1245	0	0
T10	72054	188	0	0
T11	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	206273	0	0
T1	9401	9	0	0
T2	42503	100	0	0
T3	610352	39	0	0
T4	82211	179	0	0
T5	564091	1325	0	0
T6	23973	1059	0	0
T7	13095	0	0	0
T8	586603	1063	0	0
T9	524045	1033	0	0
T10	72054	150	0	0
T11	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	212324	0	0
GntImpliesValid_A	445948577	212324	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	212324	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3172208	0	0
ReadyAndValidImplyGrant_A	445948577	212324	0	0
ReqAndReadyImplyGrant_A	445948577	212324	0	0
ReqImpliesValid_A	445948577	613982	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	212324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3172208	0	0
T1	9401	62	0	0
T2	42503	684	0	0
T3	610352	8912	0	0
T4	82211	1637	0	0
T5	564091	6941	0	0
T6	23973	2	0	0
T7	13095	1	0	0
T8	586603	8654	0	0
T9	524045	10072	0	0
T10	72054	1290	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	613982	0	0
T1	9401	8	0	0
T2	42503	123	0	0
T3	610352	517	0	0
T4	82211	328	0	0
T5	564091	1098	0	0
T6	23973	873	0	0
T7	13095	0	0	0
T8	586603	7658	0	0
T9	524045	2528	0	0
T10	72054	213	0	0
T11	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	212324	0	0
T1	9401	8	0	0
T2	42503	93	0	0
T3	610352	35	0	0
T4	82211	222	0	0
T5	564091	922	0	0
T6	23973	437	0	0
T7	13095	0	0	0
T8	586603	1675	0	0
T9	524045	1529	0	0
T10	72054	172	0	0
T11	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	233696	0	0
GntImpliesValid_A	445948577	233696	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	233696	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3233893	0	0
ReadyAndValidImplyGrant_A	445948577	233696	0	0
ReqAndReadyImplyGrant_A	445948577	233696	0	0
ReqImpliesValid_A	445948577	601470	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	233696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3233893	0	0
T1	9401	116	0	0
T2	42503	694	0	0
T3	610352	12236	0	0
T4	82211	1949	0	0
T5	564091	7855	0	0
T6	23973	1	0	0
T7	13095	35	0	0
T8	586603	4545	0	0
T9	524045	7749	0	0
T10	72054	1545	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	601470	0	0
T1	9401	16	0	0
T2	42503	120	0	0
T3	610352	43	0	0
T4	82211	324	0	0
T5	564091	1199	0	0
T6	23973	0	0	0
T7	13095	1084	0	0
T8	586603	752	0	0
T9	524045	1209	0	0
T10	72054	259	0	0
T11	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	233696	0	0
T1	9401	14	0	0
T2	42503	94	0	0
T3	610352	43	0	0
T4	82211	251	0	0
T5	564091	1038	0	0
T6	23973	0	0	0
T7	13095	559	0	0
T8	586603	629	0	0
T9	524045	1010	0	0
T10	72054	201	0	0
T11	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	201030	0	0
GntImpliesValid_A	445948577	201030	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	201030	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3060703	0	0
ReadyAndValidImplyGrant_A	445948577	201030	0	0
ReqAndReadyImplyGrant_A	445948577	201030	0	0
ReqImpliesValid_A	445948577	509585	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	201030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3060703	0	0
T1	9401	82	0	0
T2	42503	684	0	0
T3	610352	10160	0	0
T4	82211	1685	0	0
T5	564091	13066	0	0
T6	23973	2	0	0
T7	13095	1	0	0
T8	586603	6129	0	0
T9	524045	12891	0	0
T10	72054	1260	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	509585	0	0
T1	9401	24	0	0
T2	42503	141	0	0
T3	610352	1153	0	0
T4	82211	312	0	0
T5	564091	4320	0	0
T6	23973	1051	0	0
T7	13095	0	0	0
T8	586603	2886	0	0
T9	524045	6744	0	0
T10	72054	230	0	0
T11	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	201030	0	0
T1	9401	12	0	0
T2	42503	95	0	0
T3	610352	34	0	0
T4	82211	241	0	0
T5	564091	1834	0	0
T6	23973	526	0	0
T7	13095	0	0	0
T8	586603	1198	0	0
T9	524045	2092	0	0
T10	72054	174	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	220603	0	0
GntImpliesValid_A	445948577	220603	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	220603	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3130783	0	0
ReadyAndValidImplyGrant_A	445948577	220603	0	0
ReqAndReadyImplyGrant_A	445948577	220603	0	0
ReqImpliesValid_A	445948577	633102	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	220603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3130783	0	0
T1	9401	77	0	0
T2	42503	602	0	0
T3	610352	14367	0	0
T4	82211	1742	0	0
T5	564091	9964	0	0
T6	23973	2	0	0
T7	13095	4	0	0
T8	586603	7769	0	0
T9	524045	7633	0	0
T10	72054	1197	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	633102	0	0
T1	9401	10	0	0
T2	42503	106	0	0
T3	610352	1110	0	0
T4	82211	310	0	0
T5	564091	2315	0	0
T6	23973	1015	0	0
T7	13095	2815	0	0
T8	586603	9215	0	0
T9	524045	1107	0	0
T10	72054	204	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	220603	0	0
T1	9401	10	0	0
T2	42503	93	0	0
T3	610352	41	0	0
T4	82211	243	0	0
T5	564091	1322	0	0
T6	23973	508	0	0
T7	13095	1409	0	0
T8	586603	1646	0	0
T9	524045	977	0	0
T10	72054	149	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217412	0	0
GntImpliesValid_A	445948577	217412	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217412	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3228923	0	0
ReadyAndValidImplyGrant_A	445948577	217412	0	0
ReqAndReadyImplyGrant_A	445948577	217412	0	0
ReqImpliesValid_A	445948577	578790	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3228923	0	0
T1	9401	66	0	0
T2	42503	857	0	0
T3	610352	16706	0	0
T4	82211	1576	0	0
T5	564091	9095	0	0
T6	23973	2	0	0
T7	13095	1	0	0
T8	586603	11118	0	0
T9	524045	10099	0	0
T10	72054	1452	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	578790	0	0
T1	9401	8	0	0
T2	42503	138	0	0
T3	610352	1440	0	0
T4	82211	297	0	0
T5	564091	2693	0	0
T6	23973	1185	0	0
T7	13095	0	0	0
T8	586603	5642	0	0
T9	524045	4059	0	0
T10	72054	229	0	0
T11	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217412	0	0
T1	9401	8	0	0
T2	42503	117	0	0
T3	610352	55	0	0
T4	82211	227	0	0
T5	564091	1277	0	0
T6	23973	593	0	0
T7	13095	0	0	0
T8	586603	2252	0	0
T9	524045	1527	0	0
T10	72054	187	0	0
T11	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217892	0	0
GntImpliesValid_A	445948577	217892	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217892	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3204961	0	0
ReadyAndValidImplyGrant_A	445948577	217892	0	0
ReqAndReadyImplyGrant_A	445948577	217892	0	0
ReqImpliesValid_A	445948577	565761	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3204961	0	0
T1	9401	53	0	0
T2	42503	723	0	0
T3	610352	10749	0	0
T4	82211	1694	0	0
T5	564091	6936	0	0
T6	23973	53	0	0
T7	13095	1	0	0
T8	586603	8158	0	0
T9	524045	7146	0	0
T10	72054	1296	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	565761	0	0
T1	9401	7	0	0
T2	42503	153	0	0
T3	610352	777	0	0
T4	82211	309	0	0
T5	564091	990	0	0
T6	23973	1042	0	0
T7	13095	0	0	0
T8	586603	3094	0	0
T9	524045	1158	0	0
T10	72054	186	0	0
T11	0	24	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217892	0	0
T1	9401	7	0	0
T2	42503	102	0	0
T3	610352	33	0	0
T4	82211	237	0	0
T5	564091	857	0	0
T6	23973	547	0	0
T7	13095	0	0	0
T8	586603	1229	0	0
T9	524045	970	0	0
T10	72054	167	0	0
T11	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	217551	0	0
GntImpliesValid_A	445948577	217551	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	217551	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	3161856	0	0
ReadyAndValidImplyGrant_A	445948577	217551	0	0
ReqAndReadyImplyGrant_A	445948577	217551	0	0
ReqImpliesValid_A	445948577	559466	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	0	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	217551	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	3161856	0	0
T1	9401	47	0	0
T2	42503	873	0	0
T3	610352	11942	0	0
T4	82211	1808	0	0
T5	564091	9697	0	0
T6	23973	142	0	0
T7	13095	1	0	0
T8	586603	6095	0	0
T9	524045	10888	0	0
T10	72054	1231	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	559466	0	0
T1	9401	4	0	0
T2	42503	150	0	0
T3	610352	722	0	0
T4	82211	330	0	0
T5	564091	1879	0	0
T6	23973	1793	0	0
T7	13095	0	0	0
T8	586603	5448	0	0
T9	524045	2204	0	0
T10	72054	241	0	0
T11	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	217551	0	0
T1	9401	4	0	0
T2	42503	110	0	0
T3	610352	44	0	0
T4	82211	230	0	0
T5	564091	1337	0	0
T6	23973	967	0	0
T7	13095	0	0	0
T8	586603	1180	0	0
T9	524045	1478	0	0
T10	72054	181	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	856564	0	0
GntImpliesValid_A	445948577	856564	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	856564	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	12134003	0	0
ReadyAndValidImplyGrant_A	445948577	856564	0	0
ReqAndReadyImplyGrant_A	445948577	856564	0	0
ReqImpliesValid_A	445948577	2373410	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	14697	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	856564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	12134003	0	0
T1	9401	336	0	0
T2	42503	2642	0	0
T3	610352	48241	0	0
T4	82211	5866	0	0
T5	564091	29838	0	0
T6	23973	1	0	0
T7	13095	1	0	0
T8	586603	31106	0	0
T9	524045	32760	0	0
T10	72054	4755	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	2373410	0	0
T1	9401	94	0	0
T2	42503	752	0	0
T3	610352	6071	0	0
T4	82211	1646	0	0
T5	564091	8397	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	7699	0	0
T9	524045	7818	0	0
T10	72054	1168	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	14697	0	900
T5	564091	8	0	1
T6	23973	0	0	1
T7	13095	297	0	1
T8	586603	0	0	1
T9	524045	4	0	1
T10	72054	0	0	1
T11	206989	0	0	1
T12	67052	23	0	1
T13	370897	0	0	1
T14	0	21	0	0
T15	0	28	0	0
T16	0	5	0	0
T17	0	16	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	63975	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	856564	0	0
T1	9401	56	0	0
T2	42503	452	0	0
T3	610352	152	0	0
T4	82211	907	0	0
T5	564091	5134	0	0
T6	23973	1005	0	0
T7	13095	1215	0	0
T8	586603	4718	0	0
T9	524045	5011	0	0
T10	72054	744	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	445948577	445820342	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	445948577	854720	0	0
GntImpliesValid_A	445948577	854720	0	0
GrantKnown_A	445948577	445820342	0	0
IdxKnown_A	445948577	445820342	0	0
IndexIsCorrect_A	445948577	854720	0	0
LockArbDecision_A	445948577	0	0	0
NoReadyValidNoGrant_A	445948577	375085003	0	0
ReadyAndValidImplyGrant_A	445948577	854720	0	0
ReqAndReadyImplyGrant_A	445948577	854720	0	0
ReqImpliesValid_A	445948577	13987272	0	0
ReqStaysHighUntilGranted0_M	445948577	0	0	0
RoundRobin_A	445948577	25221	0	900
ValidKnown_A	445948577	445820342	0	0
gen_data_port_assertion.DataFlow_A	445948577	854720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	375085003	0	0
T1	9401	8132	0	0
T2	42503	35330	0	0
T3	610352	554801	0	0
T4	82211	68713	0	0
T5	564091	479671	0	0
T6	23973	1	0	0
T7	13095	1	0	0
T8	586603	488466	0	0
T9	524045	427272	0	0
T10	72054	59096	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	13987272	0	0
T1	9401	319	0	0
T2	42503	3739	0	0
T3	610352	54425	0	0
T4	82211	6823	0	0
T5	564091	35405	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	50550	0	0
T9	524045	55508	0	0
T10	72054	5235	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	25221	0	900
T5	564091	2	0	1
T6	23973	0	0	1
T7	13095	0	0	1
T8	586603	16	0	1
T9	524045	30	0	1
T10	72054	2	0	1
T11	206989	0	0	1
T12	67052	131	0	1
T13	370897	0	0	1
T14	0	18	0	0
T15	0	23	0	0
T16	0	9	0	0
T17	0	8	0	0
T18	0	2	0	0
T20	63975	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	445820342	0	0
T1	9401	9344	0	0
T2	42503	42451	0	0
T3	610352	610302	0	0
T4	82211	82185	0	0
T5	564091	561671	0	0
T6	23973	23948	0	0
T7	13095	13071	0	0
T8	586603	586507	0	0
T9	524045	523977	0	0
T10	72054	72006	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445948577	854720	0	0
T1	9401	35	0	0
T2	42503	445	0	0
T3	610352	158	0	0
T4	82211	798	0	0
T5	564091	4307	0	0
T6	23973	1073	0	0
T7	13095	502	0	0
T8	586603	5957	0	0
T9	524045	6381	0	0
T10	72054	670	0	0