Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1532302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242704

1

T1

25

T2

12

T3

1076

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	602015	1			T1	46		T2	65		T3	2614
values[0x0]	570317	1			T1	61		T2	10		T3	2532
values[0x1]	602674	1			T1	62		T2	56		T3	2602

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1183898	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591108

1

T1

58

T2

54

T3

2619

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28046	1			T1	36		T3	93		T4	1
valid_sources[0x01]	27116	1			T1	5		T3	142		T5	6
valid_sources[0x02]	27339	1			T3	173		T6	19		T4	1
valid_sources[0x03]	27561	1			T2	2		T3	171		T5	4
valid_sources[0x04]	28595	1			T2	1		T3	141		T5	1
valid_sources[0x05]	27987	1			T3	187		T5	1		T6	29
valid_sources[0x06]	27849	1			T1	2		T2	1		T3	108
valid_sources[0x07]	27649	1			T1	11		T3	87		T5	2
valid_sources[0x08]	28075	1			T1	7		T3	76		T5	1
valid_sources[0x09]	27732	1			T3	146		T5	4		T6	26
valid_sources[0x0a]	27770	1			T1	11		T2	1		T3	127
valid_sources[0x0b]	28246	1			T1	5		T3	151		T5	1
valid_sources[0x0c]	27359	1			T1	4		T3	121		T5	3
valid_sources[0x0d]	27833	1			T2	5		T3	87		T5	3
valid_sources[0x0e]	27908	1			T2	7		T3	99		T5	4
valid_sources[0x0f]	27539	1			T1	7		T3	97		T5	2
valid_sources[0x10]	27570	1			T3	84		T5	2		T6	46
valid_sources[0x11]	27934	1			T2	18		T3	67		T5	3
valid_sources[0x12]	27849	1			T2	6		T3	85		T5	4
valid_sources[0x13]	27661	1			T2	5		T3	169		T5	2
valid_sources[0x14]	27869	1			T3	147		T5	1		T6	14
valid_sources[0x15]	26936	1			T3	80		T5	3		T6	18
valid_sources[0x16]	28007	1			T3	125		T5	4		T6	37
valid_sources[0x17]	27375	1			T3	161		T5	2		T6	12
valid_sources[0x18]	27506	1			T2	4		T3	66		T5	4
valid_sources[0x19]	28234	1			T3	97		T5	4		T6	18
valid_sources[0x1a]	27253	1			T2	6		T3	79		T5	1
valid_sources[0x1b]	28051	1			T3	62		T5	3		T6	43
valid_sources[0x1c]	28015	1			T2	1		T3	119		T5	2
valid_sources[0x1d]	28118	1			T1	2		T2	3		T3	71
valid_sources[0x1e]	28292	1			T1	6		T3	146		T5	2
valid_sources[0x1f]	26809	1			T3	112		T5	4		T6	19
valid_sources[0x20]	27294	1			T1	5		T2	2		T3	146

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25652

1

T1

2

T2

3

T3

106

values[0x0]

all_enables

biggest_size

191754

1

T1

20

T2

5

T3

846

values[0x1]

all_enables

biggest_size

25298

1

T1

3

T2

4

T3

124

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1549996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252834

1

T1

36

T2

8

T3

1088

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	616235	1			T1	47		T2	65		T3	2759
values[0x0]	570505	1			T1	71		T2	11		T3	2535
values[0x1]	616090	1			T1	65		T2	61		T3	2605

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1189553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613277

1

T1

62

T2

54

T3

2696

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28874	1			T1	3		T2	5		T3	109
valid_sources[0x01]	28467	1			T1	5		T2	3		T3	115
valid_sources[0x02]	28129	1			T1	1		T2	1		T3	156
valid_sources[0x03]	27938	1			T1	1		T2	1		T3	185
valid_sources[0x04]	28281	1			T1	1		T2	3		T3	113
valid_sources[0x05]	28250	1			T1	2		T2	2		T3	175
valid_sources[0x06]	28193	1			T1	3		T2	2		T3	119
valid_sources[0x07]	28604	1			T2	2		T3	91		T6	40
valid_sources[0x08]	28956	1			T2	1		T3	67		T6	20
valid_sources[0x09]	28064	1			T1	3		T3	157		T6	31
valid_sources[0x0a]	28419	1			T1	6		T2	2		T3	124
valid_sources[0x0b]	27319	1			T1	3		T2	1		T3	138
valid_sources[0x0c]	28699	1			T1	2		T2	3		T3	107
valid_sources[0x0d]	27759	1			T1	2		T3	103		T5	1
valid_sources[0x0e]	27858	1			T1	10		T2	5		T3	118
valid_sources[0x0f]	29045	1			T1	6		T3	75		T6	37
valid_sources[0x10]	28339	1			T1	1		T2	2		T3	105
valid_sources[0x11]	28622	1			T1	5		T3	110		T5	12
valid_sources[0x12]	27994	1			T1	4		T2	1		T3	120
valid_sources[0x13]	27876	1			T1	7		T2	1		T3	164
valid_sources[0x14]	27810	1			T1	1		T2	4		T3	91
valid_sources[0x15]	28040	1			T1	3		T2	1		T3	109
valid_sources[0x16]	27882	1			T1	3		T2	4		T3	129
valid_sources[0x17]	28131	1			T1	1		T2	4		T3	136
valid_sources[0x18]	28377	1			T1	2		T2	4		T3	91
valid_sources[0x19]	27569	1			T2	3		T3	106		T5	25
valid_sources[0x1a]	28305	1			T1	4		T3	129		T6	56
valid_sources[0x1b]	27802	1			T1	1		T3	98		T6	47
valid_sources[0x1c]	27212	1			T1	3		T3	111		T6	29
valid_sources[0x1d]	28293	1			T1	2		T2	2		T3	73
valid_sources[0x1e]	29049	1			T1	3		T2	6		T3	161
valid_sources[0x1f]	28379	1			T1	3		T2	2		T3	141
valid_sources[0x20]	28473	1			T1	5		T2	3		T3	124

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26506

1

T1

2

T2

3

T3

123

values[0x0]

all_enables

biggest_size

199900

1

T1

32

T2

3

T3

881

values[0x1]

all_enables

biggest_size

26428

1

T1

2

T2

2

T3

84

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1538905	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243949

1

T1

20

T2

10

T3

1110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	604776	1			T1	41		T2	64		T3	2686
values[0x0]	573676	1			T1	57		T2	8		T3	2585
values[0x1]	604402	1			T1	43		T2	56		T3	2705

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1189474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

593380

1

T1

45

T2

47

T3

2698

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27416	1			T1	5		T2	1		T3	89
valid_sources[0x01]	26713	1			T1	3		T2	12		T3	134
valid_sources[0x02]	27475	1			T1	1		T2	1		T3	196
valid_sources[0x03]	27478	1			T1	1		T3	153		T6	20
valid_sources[0x04]	27705	1			T1	1		T3	103		T6	13
valid_sources[0x05]	27921	1			T1	7		T2	3		T3	160
valid_sources[0x06]	28183	1			T1	2		T3	132		T5	3
valid_sources[0x07]	27768	1			T1	3		T3	89		T5	3
valid_sources[0x08]	27889	1			T1	5		T2	4		T3	111
valid_sources[0x09]	28232	1			T1	2		T3	146		T5	1
valid_sources[0x0a]	27553	1			T1	2		T3	149		T5	2
valid_sources[0x0b]	27143	1			T1	4		T2	3		T3	138
valid_sources[0x0c]	27585	1			T1	3		T3	152		T5	4
valid_sources[0x0d]	27454	1			T1	3		T2	2		T3	68
valid_sources[0x0e]	27399	1			T1	2		T2	2		T3	120
valid_sources[0x0f]	27726	1			T1	5		T2	5		T3	77
valid_sources[0x10]	28081	1			T2	1		T3	117		T5	2
valid_sources[0x11]	27875	1			T1	1		T2	2		T3	79
valid_sources[0x12]	28340	1			T1	4		T3	120		T5	1
valid_sources[0x13]	28561	1			T2	1		T3	175		T4	3
valid_sources[0x14]	27938	1			T2	4		T3	129		T5	2
valid_sources[0x15]	27493	1			T1	2		T3	84		T5	2
valid_sources[0x16]	27842	1			T1	2		T3	127		T5	4
valid_sources[0x17]	27268	1			T2	1		T3	119		T5	2
valid_sources[0x18]	27665	1			T1	3		T2	7		T3	80
valid_sources[0x19]	27162	1			T1	1		T2	4		T3	154
valid_sources[0x1a]	27754	1			T1	2		T2	12		T3	115
valid_sources[0x1b]	27738	1			T1	1		T3	97		T5	5
valid_sources[0x1c]	27432	1			T1	5		T3	125		T5	4
valid_sources[0x1d]	27867	1			T1	1		T2	3		T3	84
valid_sources[0x1e]	27632	1			T1	1		T2	1		T3	161
valid_sources[0x1f]	28234	1			T2	6		T3	92		T6	15
valid_sources[0x20]	28090	1			T1	1		T2	2		T3	126

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25395

1

T1

1

T2

2

T3

111

values[0x0]

all_enables

biggest_size

192888

1

T1

19

T2

3

T3

898

values[0x1]

all_enables

biggest_size

25666

1

T2

5

T3

101

T5

4