Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21264	21264	0	0
GntImpliesReady_A	2147483647	7518886	0	0
GntImpliesValid_A	2147483647	7518886	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7518886	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	455606234	0	0
ReadyAndValidImplyGrant_A	2147483647	7518886	0	0
ReqAndReadyImplyGrant_A	2147483647	7518886	0	0
ReqImpliesValid_A	2147483647	34959826	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46596	0	21264
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7518886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10815024	10814832	0	0
T2	294048	293760	0	0
T3	5254728	5238504	0	0
T4	1469472	1468128	0	0
T5	70608	69216	0	0
T6	286128	285744	0	0
T7	6579096	6578136	0	0
T8	45600	44736	0	0
T9	104616	100464	0	0
T10	53616	52392	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21264	21264	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10815024	10814832	0	0
T2	294048	293760	0	0
T3	5254728	5238504	0	0
T4	1469472	1468128	0	0
T5	70608	69216	0	0
T6	286128	285744	0	0
T7	6579096	6578136	0	0
T8	45600	44736	0	0
T9	104616	100464	0	0
T10	53616	52392	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10815024	10814832	0	0
T2	294048	293760	0	0
T3	5254728	5238504	0	0
T4	1469472	1468128	0	0
T5	70608	69216	0	0
T6	286128	285744	0	0
T7	6579096	6578136	0	0
T8	45600	44736	0	0
T9	104616	100464	0	0
T10	53616	52392	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	455606234	0	0
T1	10815024	549423	0	0
T2	294048	8149	0	0
T3	5254728	306843	0	0
T4	1469472	91952	0	0
T5	70608	1028	0	0
T6	286128	5042	0	0
T7	6579096	408284	0	0
T8	45600	488	0	0
T9	104616	2762	0	0
T10	53616	632	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34959826	0	0
T1	10815024	30774	0	0
T2	294048	7674	0	0
T3	5254728	64900	0	0
T4	1469472	11964	0	0
T5	70608	554	0	0
T6	286128	4598	0	0
T7	6579096	93012	0	0
T8	45600	493	0	0
T9	104616	2997	0	0
T10	53616	480	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46596	0	21264
T2	24504	25	0	2
T3	437894	40	0	2
T4	122456	0	0	2
T5	5884	0	0	2
T6	23844	17	0	2
T7	548258	19	0	2
T8	3800	0	0	2
T9	8718	4	0	2
T10	4468	0	0	2
T11	8690	6	0	2
T12	0	31	0	0
T13	0	24	0	0
T14	0	2	0	0
T15	0	6	0	0
T16	0	13	0	0
T17	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10815024	10814832	0	0
T2	294048	293760	0	0
T3	5254728	5238504	0	0
T4	1469472	1468128	0	0
T5	70608	69216	0	0
T6	286128	285744	0	0
T7	6579096	6578136	0	0
T8	45600	44736	0	0
T9	104616	100464	0	0
T10	53616	52392	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7518886	0	0
T1	10815024	493	0	0
T2	294048	6989	0	0
T3	5254728	20877	0	0
T4	1469472	4899	0	0
T5	70608	428	0	0
T6	286128	4496	0	0
T7	6579096	32229	0	0
T8	45600	454	0	0
T9	104616	2114	0	0
T10	53616	424	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	848986	0	0
GntImpliesValid_A	414448545	848986	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	848986	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	12522994	0	0
ReadyAndValidImplyGrant_A	414448545	848986	0	0
ReqAndReadyImplyGrant_A	414448545	848986	0	0
ReqImpliesValid_A	414448545	2471045	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	848986	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	12522994	0	0
T1	450626	20242	0	0
T2	12252	565	0	0
T3	218947	13479	0	0
T4	61228	3833	0	0
T5	2942	32	0	0
T6	11922	500	0	0
T7	274129	23689	0	0
T8	1900	34	0	0
T9	4359	221	0	0
T10	2234	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	2471045	0	0
T1	450626	979	0	0
T2	12252	908	0	0
T3	218947	2825	0	0
T4	61228	949	0	0
T5	2942	49	0	0
T6	11922	539	0	0
T7	274129	5243	0	0
T8	1900	47	0	0
T9	4359	297	0	0
T10	2234	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	848986	0	0
T1	450626	52	0	0
T2	12252	736	0	0
T3	218947	1935	0	0
T4	61228	544	0	0
T5	2942	40	0	0
T6	11922	519	0	0
T7	274129	3221	0	0
T8	1900	40	0	0
T9	4359	257	0	0
T10	2234	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	841862	0	0
GntImpliesValid_A	414448545	841862	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	841862	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	12605560	0	0
ReadyAndValidImplyGrant_A	414448545	841862	0	0
ReqAndReadyImplyGrant_A	414448545	841862	0	0
ReqImpliesValid_A	414448545	2504312	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	841862	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	12605560	0	0
T1	450626	23264	0	0
T2	12252	619	0	0
T3	218947	16188	0	0
T4	61228	4501	0	0
T5	2942	38	0	0
T6	11922	481	0	0
T7	274129	24447	0	0
T8	1900	37	0	0
T9	4359	220	0	0
T10	2234	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	2504312	0	0
T1	450626	3008	0	0
T2	12252	920	0	0
T3	218947	5341	0	0
T4	61228	1026	0	0
T5	2942	71	0	0
T6	11922	516	0	0
T7	274129	5324	0	0
T8	1900	56	0	0
T9	4359	310	0	0
T10	2234	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841862	0	0
T1	450626	70	0	0
T2	12252	769	0	0
T3	218947	2682	0	0
T4	61228	615	0	0
T5	2942	54	0	0
T6	11922	498	0	0
T7	274129	3233	0	0
T8	1900	46	0	0
T9	4359	263	0	0
T10	2234	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	199026	0	0
GntImpliesValid_A	414448545	199026	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	199026	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3039984	0	0
ReadyAndValidImplyGrant_A	414448545	199026	0	0
ReqAndReadyImplyGrant_A	414448545	199026	0	0
ReqImpliesValid_A	414448545	551785	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	199026	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3039984	0	0
T1	450626	4588	0	0
T2	12252	180	0	0
T3	218947	2684	0	0
T4	61228	969	0	0
T5	2942	9	0	0
T6	11922	158	0	0
T7	274129	4344	0	0
T8	1900	19	0	0
T9	4359	29	0	0
T10	2234	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	551785	0	0
T1	450626	387	0	0
T2	12252	195	0	0
T3	218947	357	0	0
T4	61228	179	0	0
T5	2942	8	0	0
T6	11922	159	0	0
T7	274129	762	0	0
T8	1900	20	0	0
T9	4359	26	0	0
T10	2234	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199026	0	0
T1	450626	11	0	0
T2	12252	187	0	0
T3	218947	350	0	0
T4	61228	133	0	0
T5	2942	8	0	0
T6	11922	158	0	0
T7	274129	587	0	0
T8	1900	19	0	0
T9	4359	26	0	0
T10	2234	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	214761	0	0
GntImpliesValid_A	414448545	214761	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	214761	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3132806	0	0
ReadyAndValidImplyGrant_A	414448545	214761	0	0
ReqAndReadyImplyGrant_A	414448545	214761	0	0
ReqImpliesValid_A	414448545	614522	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	214761	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3132806	0	0
T1	450626	1542	0	0
T2	12252	210	0	0
T3	218947	6336	0	0
T4	61228	1035	0	0
T5	2942	10	0	0
T6	11922	112	0	0
T7	274129	8554	0	0
T8	1900	19	0	0
T9	4359	44	0	0
T10	2234	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	614522	0	0
T1	450626	5	0	0
T2	12252	219	0	0
T3	218947	2639	0	0
T4	61228	174	0	0
T5	2942	9	0	0
T6	11922	119	0	0
T7	274129	3790	0	0
T8	1900	18	0	0
T9	4359	42	0	0
T10	2234	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	214761	0	0
T1	450626	5	0	0
T2	12252	214	0	0
T3	218947	942	0	0
T4	61228	136	0	0
T5	2942	9	0	0
T6	11922	115	0	0
T7	274129	1581	0	0
T8	1900	18	0	0
T9	4359	41	0	0
T10	2234	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	212513	0	0
GntImpliesValid_A	414448545	212513	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	212513	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	5908998	0	0
ReadyAndValidImplyGrant_A	414448545	212513	0	0
ReqAndReadyImplyGrant_A	414448545	212513	0	0
ReqImpliesValid_A	414448545	1329578	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	212513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	5908998	0	0
T1	450626	1151	0	0
T2	12252	879	0	0
T3	218947	2753	0	0
T4	61228	1811	0	0
T5	2942	52	0	0
T6	11922	764	0	0
T7	274129	3488	0	0
T8	1900	51	0	0
T9	4359	106	0	0
T10	2234	179	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	1329578	0	0
T1	450626	48	0	0
T2	12252	293	0	0
T3	218947	605	0	0
T4	61228	199	0	0
T5	2942	6	0	0
T6	11922	150	0	0
T7	274129	676	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212513	0	0
T1	450626	16	0	0
T2	12252	218	0	0
T3	218947	392	0	0
T4	61228	129	0	0
T5	2942	6	0	0
T6	11922	120	0	0
T7	274129	602	0	0
T8	1900	9	0	0
T9	4359	25	0	0
T10	2234	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	198445	0	0
GntImpliesValid_A	414448545	198445	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	198445	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	5047152	0	0
ReadyAndValidImplyGrant_A	414448545	198445	0	0
ReqAndReadyImplyGrant_A	414448545	198445	0	0
ReqImpliesValid_A	414448545	1147104	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	198445	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	5047152	0	0
T1	450626	4729	0	0
T2	12252	1076	0	0
T3	218947	2236	0	0
T4	61228	1656	0	0
T5	2942	145	0	0
T6	11922	412	0	0
T7	274129	9018	0	0
T8	1900	66	0	0
T9	4359	160	0	0
T10	2234	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	1147104	0	0
T1	450626	13	0	0
T2	12252	310	0	0
T3	218947	397	0	0
T4	61228	184	0	0
T5	2942	51	0	0
T6	11922	116	0	0
T7	274129	7324	0	0
T8	1900	19	0	0
T9	4359	28	0	0
T10	2234	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198445	0	0
T1	450626	13	0	0
T2	12252	224	0	0
T3	218947	355	0	0
T4	61228	128	0	0
T5	2942	18	0	0
T6	11922	115	0	0
T7	274129	2015	0	0
T8	1900	15	0	0
T9	4359	23	0	0
T10	2234	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	204283	0	0
GntImpliesValid_A	414448545	204283	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	204283	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	4905656	0	0
ReadyAndValidImplyGrant_A	414448545	204283	0	0
ReqAndReadyImplyGrant_A	414448545	204283	0	0
ReqImpliesValid_A	414448545	1084736	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	204283	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	4905656	0	0
T1	450626	1256	0	0
T2	12252	1159	0	0
T3	218947	7454	0	0
T4	61228	1774	0	0
T5	2942	58	0	0
T6	11922	394	0	0
T7	274129	5881	0	0
T8	1900	33	0	0
T9	4359	121	0	0
T10	2234	42	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	1084736	0	0
T1	450626	14	0	0
T2	12252	213	0	0
T3	218947	13131	0	0
T4	61228	302	0	0
T5	2942	17	0	0
T6	11922	128	0	0
T7	274129	4784	0	0
T8	1900	8	0	0
T9	4359	36	0	0
T10	2234	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204283	0	0
T1	450626	14	0	0
T2	12252	170	0	0
T3	218947	852	0	0
T4	61228	142	0	0
T5	2942	8	0	0
T6	11922	119	0	0
T7	274129	1566	0	0
T8	1900	8	0	0
T9	4359	31	0	0
T10	2234	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	212877	0	0
GntImpliesValid_A	414448545	212877	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	212877	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	4880824	0	0
ReadyAndValidImplyGrant_A	414448545	212877	0	0
ReqAndReadyImplyGrant_A	414448545	212877	0	0
ReqImpliesValid_A	414448545	1352972	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	212877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	4880824	0	0
T1	450626	2145	0	0
T2	12252	726	0	0
T3	218947	2009	0	0
T4	61228	7480	0	0
T5	2942	490	0	0
T6	11922	523	0	0
T7	274129	8667	0	0
T8	1900	25	0	0
T9	4359	1302	0	0
T10	2234	55	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	1352972	0	0
T1	450626	12	0	0
T2	12252	240	0	0
T3	218947	381	0	0
T4	61228	927	0	0
T5	2942	71	0	0
T6	11922	114	0	0
T7	274129	898	0	0
T8	1900	13	0	0
T9	4359	1236	0	0
T10	2234	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212877	0	0
T1	450626	12	0	0
T2	12252	190	0	0
T3	218947	363	0	0
T4	61228	154	0	0
T5	2942	18	0	0
T6	11922	114	0	0
T7	274129	574	0	0
T8	1900	7	0	0
T9	4359	456	0	0
T10	2234	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	198816	0	0
GntImpliesValid_A	414448545	198816	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	198816	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3106466	0	0
ReadyAndValidImplyGrant_A	414448545	198816	0	0
ReqAndReadyImplyGrant_A	414448545	198816	0	0
ReqImpliesValid_A	414448545	537845	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	198816	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3106466	0	0
T1	450626	5413	0	0
T2	12252	183	0	0
T3	218947	2305	0	0
T4	61228	993	0	0
T5	2942	12	0	0
T6	11922	124	0	0
T7	274129	4480	0	0
T8	1900	16	0	0
T9	4359	40	0	0
T10	2234	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	537845	0	0
T1	450626	17	0	0
T2	12252	196	0	0
T3	218947	337	0	0
T4	61228	162	0	0
T5	2942	15	0	0
T6	11922	127	0	0
T7	274129	767	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	198816	0	0
T1	450626	17	0	0
T2	12252	189	0	0
T3	218947	310	0	0
T4	61228	124	0	0
T5	2942	13	0	0
T6	11922	125	0	0
T7	274129	613	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	206060	0	0
GntImpliesValid_A	414448545	206060	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	206060	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3105207	0	0
ReadyAndValidImplyGrant_A	414448545	206060	0	0
ReqAndReadyImplyGrant_A	414448545	206060	0	0
ReqImpliesValid_A	414448545	573164	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	206060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3105207	0	0
T1	450626	1853	0	0
T2	12252	191	0	0
T3	218947	2474	0	0
T4	61228	1093	0	0
T5	2942	16	0	0
T6	11922	115	0	0
T7	274129	6706	0	0
T8	1900	16	0	0
T9	4359	44	0	0
T10	2234	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	573164	0	0
T1	450626	11	0	0
T2	12252	200	0	0
T3	218947	352	0	0
T4	61228	196	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	1512	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206060	0	0
T1	450626	11	0	0
T2	12252	195	0	0
T3	218947	322	0	0
T4	61228	137	0	0
T5	2942	15	0	0
T6	11922	114	0	0
T7	274129	983	0	0
T8	1900	15	0	0
T9	4359	40	0	0
T10	2234	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	212267	0	0
GntImpliesValid_A	414448545	212267	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	212267	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3094261	0	0
ReadyAndValidImplyGrant_A	414448545	212267	0	0
ReqAndReadyImplyGrant_A	414448545	212267	0	0
ReqImpliesValid_A	414448545	593508	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	212267	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3094261	0	0
T1	450626	1089	0	0
T2	12252	181	0	0
T3	218947	2455	0	0
T4	61228	1076	0	0
T5	2942	13	0	0
T6	11922	113	0	0
T7	274129	4938	0	0
T8	1900	14	0	0
T9	4359	35	0	0
T10	2234	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	593508	0	0
T1	450626	4	0	0
T2	12252	198	0	0
T3	218947	366	0	0
T4	61228	222	0	0
T5	2942	12	0	0
T6	11922	116	0	0
T7	274129	781	0	0
T8	1900	15	0	0
T9	4359	33	0	0
T10	2234	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212267	0	0
T1	450626	4	0	0
T2	12252	189	0	0
T3	218947	325	0	0
T4	61228	145	0	0
T5	2942	12	0	0
T6	11922	114	0	0
T7	274129	629	0	0
T8	1900	14	0	0
T9	4359	32	0	0
T10	2234	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	216222	0	0
GntImpliesValid_A	414448545	216222	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	216222	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3137506	0	0
ReadyAndValidImplyGrant_A	414448545	216222	0	0
ReqAndReadyImplyGrant_A	414448545	216222	0	0
ReqImpliesValid_A	414448545	601757	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	216222	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3137506	0	0
T1	450626	6848	0	0
T2	12252	198	0	0
T3	218947	2614	0	0
T4	61228	886	0	0
T5	2942	17	0	0
T6	11922	140	0	0
T7	274129	5380	0	0
T8	1900	16	0	0
T9	4359	32	0	0
T10	2234	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	601757	0	0
T1	450626	195	0	0
T2	12252	207	0	0
T3	218947	425	0	0
T4	61228	212	0	0
T5	2942	16	0	0
T6	11922	141	0	0
T7	274129	4334	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	216222	0	0
T1	450626	22	0	0
T2	12252	202	0	0
T3	218947	358	0	0
T4	61228	140	0	0
T5	2942	16	0	0
T6	11922	140	0	0
T7	274129	989	0	0
T8	1900	15	0	0
T9	4359	28	0	0
T10	2234	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	199746	0	0
GntImpliesValid_A	414448545	199746	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	199746	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3085557	0	0
ReadyAndValidImplyGrant_A	414448545	199746	0	0
ReqAndReadyImplyGrant_A	414448545	199746	0	0
ReqImpliesValid_A	414448545	534848	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	199746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3085557	0	0
T1	450626	5345	0	0
T2	12252	186	0	0
T3	218947	3396	0	0
T4	61228	1074	0	0
T5	2942	9	0	0
T6	11922	110	0	0
T7	274129	4538	0	0
T8	1900	20	0	0
T9	4359	37	0	0
T10	2234	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	534848	0	0
T1	450626	947	0	0
T2	12252	193	0	0
T3	218947	522	0	0
T4	61228	221	0	0
T5	2942	12	0	0
T6	11922	113	0	0
T7	274129	741	0	0
T8	1900	21	0	0
T9	4359	33	0	0
T10	2234	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	199746	0	0
T1	450626	16	0	0
T2	12252	189	0	0
T3	218947	419	0	0
T4	61228	144	0	0
T5	2942	10	0	0
T6	11922	111	0	0
T7	274129	608	0	0
T8	1900	20	0	0
T9	4359	33	0	0
T10	2234	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	207166	0	0
GntImpliesValid_A	414448545	207166	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	207166	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3166362	0	0
ReadyAndValidImplyGrant_A	414448545	207166	0	0
ReqAndReadyImplyGrant_A	414448545	207166	0	0
ReqImpliesValid_A	414448545	546405	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	207166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3166362	0	0
T1	450626	3151	0	0
T2	12252	208	0	0
T3	218947	2530	0	0
T4	61228	719	0	0
T5	2942	19	0	0
T6	11922	110	0	0
T7	274129	7610	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	546405	0	0
T1	450626	10	0	0
T2	12252	229	0	0
T3	218947	446	0	0
T4	61228	140	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1486	0	0
T8	1900	16	0	0
T9	4359	39	0	0
T10	2234	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	207166	0	0
T1	450626	10	0	0
T2	12252	218	0	0
T3	218947	342	0	0
T4	61228	110	0	0
T5	2942	18	0	0
T6	11922	109	0	0
T7	274129	1008	0	0
T8	1900	15	0	0
T9	4359	39	0	0
T10	2234	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	206012	0	0
GntImpliesValid_A	414448545	206012	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	206012	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3117802	0	0
ReadyAndValidImplyGrant_A	414448545	206012	0	0
ReqAndReadyImplyGrant_A	414448545	206012	0	0
ReqImpliesValid_A	414448545	562710	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	206012	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3117802	0	0
T1	450626	5499	0	0
T2	12252	202	0	0
T3	218947	3492	0	0
T4	61228	846	0	0
T5	2942	14	0	0
T6	11922	97	0	0
T7	274129	4656	0	0
T8	1900	15	0	0
T9	4359	36	0	0
T10	2234	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	562710	0	0
T1	450626	231	0	0
T2	12252	207	0	0
T3	218947	1804	0	0
T4	61228	155	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	741	0	0
T8	1900	16	0	0
T9	4359	32	0	0
T10	2234	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206012	0	0
T1	450626	15	0	0
T2	12252	204	0	0
T3	218947	534	0	0
T4	61228	115	0	0
T5	2942	13	0	0
T6	11922	96	0	0
T7	274129	608	0	0
T8	1900	15	0	0
T9	4359	32	0	0
T10	2234	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	206285	0	0
GntImpliesValid_A	414448545	206285	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	206285	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3085097	0	0
ReadyAndValidImplyGrant_A	414448545	206285	0	0
ReqAndReadyImplyGrant_A	414448545	206285	0	0
ReqImpliesValid_A	414448545	545147	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	206285	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3085097	0	0
T1	450626	3153	0	0
T2	12252	197	0	0
T3	218947	5657	0	0
T4	61228	1098	0	0
T5	2942	16	0	0
T6	11922	129	0	0
T7	274129	5800	0	0
T8	1900	12	0	0
T9	4359	42	0	0
T10	2234	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	545147	0	0
T1	450626	10	0	0
T2	12252	204	0	0
T3	218947	2186	0	0
T4	61228	261	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	4879	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	206285	0	0
T1	450626	10	0	0
T2	12252	200	0	0
T3	218947	845	0	0
T4	61228	150	0	0
T5	2942	15	0	0
T6	11922	128	0	0
T7	274129	1109	0	0
T8	1900	11	0	0
T9	4359	38	0	0
T10	2234	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	232085	0	0
GntImpliesValid_A	414448545	232085	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	232085	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3170041	0	0
ReadyAndValidImplyGrant_A	414448545	232085	0	0
ReqAndReadyImplyGrant_A	414448545	232085	0	0
ReqImpliesValid_A	414448545	627824	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	232085	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3170041	0	0
T1	450626	5650	0	0
T2	12252	238	0	0
T3	218947	9818	0	0
T4	61228	1111	0	0
T5	2942	15	0	0
T6	11922	120	0	0
T7	274129	7421	0	0
T8	1900	12	0	0
T9	4359	47	0	0
T10	2234	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	627824	0	0
T1	450626	15	0	0
T2	12252	251	0	0
T3	218947	7070	0	0
T4	61228	190	0	0
T5	2942	14	0	0
T6	11922	121	0	0
T7	274129	4009	0	0
T8	1900	15	0	0
T9	4359	45	0	0
T10	2234	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	232085	0	0
T1	450626	15	0	0
T2	12252	244	0	0
T3	218947	1740	0	0
T4	61228	152	0	0
T5	2942	14	0	0
T6	11922	120	0	0
T7	274129	1159	0	0
T8	1900	13	0	0
T9	4359	44	0	0
T10	2234	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	197205	0	0
GntImpliesValid_A	414448545	197205	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	197205	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3082912	0	0
ReadyAndValidImplyGrant_A	414448545	197205	0	0
ReqAndReadyImplyGrant_A	414448545	197205	0	0
ReqImpliesValid_A	414448545	506758	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	197205	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3082912	0	0
T1	450626	2875	0	0
T2	12252	173	0	0
T3	218947	3801	0	0
T4	61228	912	0	0
T5	2942	9	0	0
T6	11922	138	0	0
T7	274129	4228	0	0
T8	1900	9	0	0
T9	4359	48	0	0
T10	2234	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	506758	0	0
T1	450626	13	0	0
T2	12252	176	0	0
T3	218947	2068	0	0
T4	61228	160	0	0
T5	2942	8	0	0
T6	11922	143	0	0
T7	274129	596	0	0
T8	1900	10	0	0
T9	4359	46	0	0
T10	2234	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	197205	0	0
T1	450626	13	0	0
T2	12252	174	0	0
T3	218947	827	0	0
T4	61228	114	0	0
T5	2942	8	0	0
T6	11922	140	0	0
T7	274129	550	0	0
T8	1900	9	0	0
T9	4359	45	0	0
T10	2234	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	212418	0	0
GntImpliesValid_A	414448545	212418	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	212418	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3145870	0	0
ReadyAndValidImplyGrant_A	414448545	212418	0	0
ReqAndReadyImplyGrant_A	414448545	212418	0	0
ReqImpliesValid_A	414448545	605405	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	212418	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3145870	0	0
T1	450626	4882	0	0
T2	12252	185	0	0
T3	218947	3343	0	0
T4	61228	851	0	0
T5	2942	12	0	0
T6	11922	129	0	0
T7	274129	7318	0	0
T8	1900	13	0	0
T9	4359	40	0	0
T10	2234	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	605405	0	0
T1	450626	15	0	0
T2	12252	206	0	0
T3	218947	1684	0	0
T4	61228	141	0	0
T5	2942	11	0	0
T6	11922	132	0	0
T7	274129	1573	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	212418	0	0
T1	450626	15	0	0
T2	12252	195	0	0
T3	218947	645	0	0
T4	61228	115	0	0
T5	2942	11	0	0
T6	11922	130	0	0
T7	274129	1032	0	0
T8	1900	12	0	0
T9	4359	36	0	0
T10	2234	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	200926	0	0
GntImpliesValid_A	414448545	200926	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	200926	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3112519	0	0
ReadyAndValidImplyGrant_A	414448545	200926	0	0
ReqAndReadyImplyGrant_A	414448545	200926	0	0
ReqImpliesValid_A	414448545	518854	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	200926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3112519	0	0
T1	450626	3027	0	0
T2	12252	204	0	0
T3	218947	2742	0	0
T4	61228	774	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	6935	0	0
T8	1900	17	0	0
T9	4359	29	0	0
T10	2234	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	518854	0	0
T1	450626	6	0	0
T2	12252	221	0	0
T3	218947	427	0	0
T4	61228	122	0	0
T5	2942	12	0	0
T6	11922	115	0	0
T7	274129	1734	0	0
T8	1900	20	0	0
T9	4359	27	0	0
T10	2234	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	200926	0	0
T1	450626	6	0	0
T2	12252	212	0	0
T3	218947	368	0	0
T4	61228	109	0	0
T5	2942	11	0	0
T6	11922	114	0	0
T7	274129	1038	0	0
T8	1900	18	0	0
T9	4359	26	0	0
T10	2234	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	204714	0	0
GntImpliesValid_A	414448545	204714	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	204714	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3107283	0	0
ReadyAndValidImplyGrant_A	414448545	204714	0	0
ReqAndReadyImplyGrant_A	414448545	204714	0	0
ReqImpliesValid_A	414448545	555259	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	204714	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3107283	0	0
T1	450626	4794	0	0
T2	12252	190	0	0
T3	218947	2626	0	0
T4	61228	1107	0	0
T5	2942	15	0	0
T6	11922	124	0	0
T7	274129	4820	0	0
T8	1900	16	0	0
T9	4359	46	0	0
T10	2234	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	555259	0	0
T1	450626	16	0	0
T2	12252	205	0	0
T3	218947	337	0	0
T4	61228	231	0	0
T5	2942	14	0	0
T6	11922	129	0	0
T7	274129	807	0	0
T8	1900	15	0	0
T9	4359	44	0	0
T10	2234	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	204714	0	0
T1	450626	16	0	0
T2	12252	197	0	0
T3	218947	328	0	0
T4	61228	147	0	0
T5	2942	14	0	0
T6	11922	126	0	0
T7	274129	647	0	0
T8	1900	15	0	0
T9	4359	43	0	0
T10	2234	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	209824	0	0
GntImpliesValid_A	414448545	209824	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	209824	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	3096050	0	0
ReadyAndValidImplyGrant_A	414448545	209824	0	0
ReqAndReadyImplyGrant_A	414448545	209824	0	0
ReqImpliesValid_A	414448545	563127	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	0	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	209824	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	3096050	0	0
T1	450626	2979	0	0
T2	12252	197	0	0
T3	218947	2785	0	0
T4	61228	1054	0	0
T5	2942	14	0	0
T6	11922	133	0	0
T7	274129	4596	0	0
T8	1900	11	0	0
T9	4359	35	0	0
T10	2234	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	563127	0	0
T1	450626	9	0	0
T2	12252	216	0	0
T3	218947	395	0	0
T4	61228	143	0	0
T5	2942	13	0	0
T6	11922	136	0	0
T7	274129	802	0	0
T8	1900	14	0	0
T9	4359	31	0	0
T10	2234	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	886

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	209824	0	0
T1	450626	9	0	0
T2	12252	206	0	0
T3	218947	349	0	0
T4	61228	122	0	0
T5	2942	13	0	0
T6	11922	134	0	0
T7	274129	622	0	0
T8	1900	12	0	0
T9	4359	31	0	0
T10	2234	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	835260	0	0
GntImpliesValid_A	414448545	835260	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	835260	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	11744657	0	0
ReadyAndValidImplyGrant_A	414448545	835260	0	0
ReqAndReadyImplyGrant_A	414448545	835260	0	0
ReqImpliesValid_A	414448545	2305064	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	16947	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	835260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	11744657	0	0
T1	450626	17797	0	0
T2	12252	1	0	0
T3	218947	17314	0	0
T4	61228	3600	0	0
T5	2942	1	0	0
T6	11922	1	0	0
T7	274129	21796	0	0
T8	1900	1	0	0
T9	4359	4	0	0
T10	2234	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	2305064	0	0
T1	450626	144	0	0
T2	12252	718	0	0
T3	218947	6953	0	0
T4	61228	944	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	5301	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	16947	0	886
T2	12252	13	0	1
T3	218947	37	0	1
T4	61228	0	0	1
T5	2942	0	0	1
T6	11922	8	0	1
T7	274129	2	0	1
T8	1900	0	0	1
T9	4359	0	0	1
T10	2234	0	0	1
T11	4345	4	0	1
T12	0	13	0	0
T13	0	15	0	0
T15	0	1	0	0
T16	0	13	0	0
T17	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	835260	0	0
T1	450626	54	0	0
T2	12252	718	0	0
T3	218947	3470	0	0
T4	61228	559	0	0
T5	2942	49	0	0
T6	11922	527	0	0
T7	274129	3312	0	0
T8	1900	46	0	0
T9	4359	216	0	0
T10	2234	44	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414448545	414329027	0	0
CheckNGreaterZero_A	886	886	0	0
GntImpliesReady_A	414448545	841127	0	0
GntImpliesValid_A	414448545	841127	0	0
GrantKnown_A	414448545	414329027	0	0
IdxKnown_A	414448545	414329027	0	0
IndexIsCorrect_A	414448545	841127	0	0
LockArbDecision_A	414448545	0	0	0
NoReadyValidNoGrant_A	414448545	348204670	0	0
ReadyAndValidImplyGrant_A	414448545	841127	0	0
ReqAndReadyImplyGrant_A	414448545	841127	0	0
ReqImpliesValid_A	414448545	13726097	0	0
ReqStaysHighUntilGranted0_M	414448545	0	0	0
RoundRobin_A	414448545	29649	0	886
ValidKnown_A	414448545	414329027	0	0
gen_data_port_assertion.DataFlow_A	414448545	841127	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	886	886	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	348204670	0	0
T1	450626	416151	0	0
T2	12252	1	0	0
T3	218947	186352	0	0
T4	61228	51699	0	0
T5	2942	1	0	0
T6	11922	1	0	0
T7	274129	218974	0	0
T8	1900	1	0	0
T9	4359	1	0	0
T10	2234	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	13726097	0	0
T1	450626	24665	0	0
T2	12252	749	0	0
T3	218947	13852	0	0
T4	61228	4524	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	34148	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	29649	0	886
T2	12252	12	0	1
T3	218947	3	0	1
T4	61228	0	0	1
T5	2942	0	0	1
T6	11922	9	0	1
T7	274129	17	0	1
T8	1900	0	0	1
T9	4359	4	0	1
T10	2234	0	0	1
T11	4345	2	0	1
T12	0	18	0	0
T13	0	9	0	0
T14	0	2	0	0
T15	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	414329027	0	0
T1	450626	450618	0	0
T2	12252	12240	0	0
T3	218947	218271	0	0
T4	61228	61172	0	0
T5	2942	2884	0	0
T6	11922	11906	0	0
T7	274129	274089	0	0
T8	1900	1864	0	0
T9	4359	4186	0	0
T10	2234	2183	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414448545	841127	0	0
T1	450626	67	0	0
T2	12252	749	0	0
T3	218947	1824	0	0
T4	61228	535	0	0
T5	2942	35	0	0
T6	11922	510	0	0
T7	274129	3943	0	0
T8	1900	47	0	0
T9	4359	273	0	0
T10	2234	49	0	0