Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1423881 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 226631 1 T1 77 T2 14 T3 3


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 561575 1 T1 159 T2 48 T3 15
values[0x0] 528064 1 T1 171 T2 45 T3 2
values[0x1] 560873 1 T1 186 T2 50 T3 12


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1099787 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 550725 1 T1 183 T2 45 T3 14


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26038 1 T1 34 T2 1 T3 5
valid_sources[0x01] 26257 1 T2 3 T3 1 T6 1
valid_sources[0x02] 25814 1 T1 14 T2 1 T6 2
valid_sources[0x03] 25697 1 T2 1 T3 1 T6 4
valid_sources[0x04] 26468 1 T6 3 T4 2 T8 15
valid_sources[0x05] 24943 1 T1 9 T2 6 T6 1
valid_sources[0x06] 25387 1 T1 8 T2 2 T5 2
valid_sources[0x07] 24961 1 T1 9 T2 3 T6 1
valid_sources[0x08] 24881 1 T1 14 T6 1 T5 3
valid_sources[0x09] 26551 1 T2 2 T6 1 T5 2
valid_sources[0x0a] 25080 1 T1 18 T2 1 T7 12
valid_sources[0x0b] 25563 1 T1 14 T3 2 T6 1
valid_sources[0x0c] 25458 1 T1 16 T3 6 T5 5
valid_sources[0x0d] 26232 1 T1 18 T2 1 T6 6
valid_sources[0x0e] 25336 1 T1 12 T6 3 T5 1
valid_sources[0x0f] 26690 1 T6 3 T5 3 T4 3
valid_sources[0x10] 26321 1 T1 9 T2 5 T6 2
valid_sources[0x11] 25208 1 T2 2 T5 1 T8 10
valid_sources[0x12] 25517 1 T2 1 T3 1 T5 5
valid_sources[0x13] 25165 1 T3 1 T6 1 T5 2
valid_sources[0x14] 26020 1 T1 15 T2 1 T6 1
valid_sources[0x15] 25482 1 T2 2 T6 2 T7 1
valid_sources[0x16] 25233 1 T6 3 T5 6 T4 3
valid_sources[0x17] 25357 1 T1 20 T6 1 T7 3
valid_sources[0x18] 26075 1 T3 3 T6 2 T7 2
valid_sources[0x19] 26150 1 T1 30 T2 1 T6 3
valid_sources[0x1a] 26177 1 T6 2 T4 2 T8 15
valid_sources[0x1b] 26552 1 T2 1 T6 3 T5 1
valid_sources[0x1c] 26313 1 T1 5 T2 5 T6 4
valid_sources[0x1d] 24896 1 T2 5 T5 2 T4 2
valid_sources[0x1e] 26133 1 T1 18 T2 2 T6 5
valid_sources[0x1f] 25458 1 T6 2 T5 8 T8 26
valid_sources[0x20] 26219 1 T1 6 T6 7 T5 4


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24052 1 T1 6 T2 1 T3 1
values[0x0] all_enables biggest_size 178825 1 T1 65 T2 10 T3 2
values[0x1] all_enables biggest_size 23754 1 T1 6 T2 3 T6 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1434461 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 233645 1 T1 64 T2 25 T3 3


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 572237 1 T1 160 T2 45 T3 11
values[0x0] 523917 1 T1 142 T2 59 T3 2
values[0x1] 571952 1 T1 180 T2 63 T3 10


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1100200 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 567906 1 T1 168 T2 52 T3 11


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25943 1 T1 26 T6 5 T7 3
valid_sources[0x01] 26656 1 T6 5 T5 2 T4 2
valid_sources[0x02] 25972 1 T1 5 T2 5 T3 1
valid_sources[0x03] 25862 1 T2 6 T6 1 T5 2
valid_sources[0x04] 26644 1 T2 1 T6 3 T5 1
valid_sources[0x05] 25651 1 T1 9 T2 4 T6 1
valid_sources[0x06] 26517 1 T1 10 T2 1 T6 3
valid_sources[0x07] 25385 1 T1 19 T2 1 T5 1
valid_sources[0x08] 25883 1 T1 12 T2 1 T6 1
valid_sources[0x09] 26021 1 T2 2 T6 3 T5 3
valid_sources[0x0a] 26076 1 T1 17 T2 1 T3 1
valid_sources[0x0b] 26270 1 T1 14 T2 6 T3 1
valid_sources[0x0c] 26051 1 T1 5 T6 2 T4 4
valid_sources[0x0d] 26478 1 T1 14 T2 4 T6 2
valid_sources[0x0e] 26771 1 T1 20 T2 6 T3 1
valid_sources[0x0f] 25859 1 T5 3 T4 1 T8 15
valid_sources[0x10] 25562 1 T1 19 T6 1 T5 1
valid_sources[0x11] 26526 1 T6 3 T5 2 T7 18
valid_sources[0x12] 25882 1 T2 1 T3 1 T6 2
valid_sources[0x13] 25448 1 T3 2 T6 2 T5 1
valid_sources[0x14] 26159 1 T1 17 T2 10 T3 2
valid_sources[0x15] 26125 1 T6 3 T5 5 T7 29
valid_sources[0x16] 26455 1 T2 4 T6 4 T7 8
valid_sources[0x17] 26378 1 T1 6 T6 3 T5 1
valid_sources[0x18] 25634 1 T2 4 T5 6 T4 4
valid_sources[0x19] 26329 1 T1 23 T5 3 T7 8
valid_sources[0x1a] 25828 1 T2 1 T5 2 T4 3
valid_sources[0x1b] 25703 1 T2 11 T3 2 T6 1
valid_sources[0x1c] 25171 1 T1 20 T6 1 T5 8
valid_sources[0x1d] 25543 1 T6 3 T7 2 T4 4
valid_sources[0x1e] 25692 1 T1 6 T2 6 T5 3
valid_sources[0x1f] 26116 1 T2 7 T5 3 T4 4
valid_sources[0x20] 25872 1 T1 13 T2 1 T5 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24990 1 T1 4 T2 2 T3 2
values[0x0] all_enables biggest_size 183959 1 T1 52 T2 22 T6 3
values[0x1] all_enables biggest_size 24696 1 T1 8 T2 1 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1432095 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 228002 1 T1 61 T2 18 T3 2


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 564822 1 T1 157 T2 42 T3 20
values[0x0] 531084 1 T1 171 T2 47 T3 1
values[0x1] 564191 1 T1 167 T2 49 T3 10


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1106261 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 553836 1 T1 146 T2 44 T3 16


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26450 1 T1 27 T2 3 T6 1
valid_sources[0x01] 26022 1 T2 5 T6 4 T8 8
valid_sources[0x02] 25945 1 T1 8 T2 5 T8 12
valid_sources[0x03] 25924 1 T2 1 T6 3 T7 12
valid_sources[0x04] 26193 1 T2 1 T6 4 T5 10
valid_sources[0x05] 25604 1 T1 15 T2 2 T6 2
valid_sources[0x06] 25561 1 T1 18 T2 1 T3 1
valid_sources[0x07] 25434 1 T1 12 T2 1 T6 1
valid_sources[0x08] 25804 1 T1 18 T2 2 T6 2
valid_sources[0x09] 26127 1 T2 1 T6 2 T8 15
valid_sources[0x0a] 25173 1 T1 6 T2 4 T6 5
valid_sources[0x0b] 26202 1 T1 6 T2 2 T6 2
valid_sources[0x0c] 25386 1 T1 6 T2 1 T6 4
valid_sources[0x0d] 26296 1 T1 15 T2 2 T6 2
valid_sources[0x0e] 26735 1 T1 20 T2 4 T6 2
valid_sources[0x0f] 25544 1 T2 1 T3 2 T6 3
valid_sources[0x10] 26983 1 T1 14 T2 3 T6 3
valid_sources[0x11] 25678 1 T2 2 T6 1 T8 14
valid_sources[0x12] 26274 1 T2 1 T6 3 T5 8
valid_sources[0x13] 26351 1 T2 2 T6 3 T4 10
valid_sources[0x14] 26561 1 T1 10 T2 1 T6 2
valid_sources[0x15] 25495 1 T2 3 T3 2 T6 2
valid_sources[0x16] 25797 1 T2 1 T6 3 T7 4
valid_sources[0x17] 26151 1 T1 19 T2 3 T6 3
valid_sources[0x18] 25161 1 T3 3 T6 2 T7 12
valid_sources[0x19] 26653 1 T1 31 T2 3 T6 2
valid_sources[0x1a] 25781 1 T2 1 T3 1 T6 2
valid_sources[0x1b] 26836 1 T2 2 T6 1 T7 15
valid_sources[0x1c] 25137 1 T1 8 T2 2 T3 1
valid_sources[0x1d] 25905 1 T2 7 T8 17 T11 100
valid_sources[0x1e] 26060 1 T1 9 T2 3 T3 1
valid_sources[0x1f] 26163 1 T2 3 T6 2 T8 14
valid_sources[0x20] 25939 1 T1 5 T2 2 T6 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24090 1 T1 5 T2 1 T3 1
values[0x0] all_enables biggest_size 179775 1 T1 50 T2 17 T6 3
values[0x1] all_enables biggest_size 24137 1 T1 6 T3 1 T6 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%