Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7854765	0	0
GntImpliesValid_A	2147483647	7854765	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7854765	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	452796240	0	0
ReadyAndValidImplyGrant_A	2147483647	7854765	0	0
ReqAndReadyImplyGrant_A	2147483647	7854765	0	0
ReqImpliesValid_A	2147483647	33725655	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	52662	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7854765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	623688	623160	0	0
T2	8148912	8147736	0	0
T3	58824	57744	0	0
T4	11136648	11135832	0	0
T5	43848	43368	0	0
T6	247464	246240	0	0
T7	55176	54480	0	0
T8	126912	126240	0	0
T9	52464	51480	0	0
T10	73080	71328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	623688	623160	0	0
T2	8148912	8147736	0	0
T3	58824	57744	0	0
T4	11136648	11135832	0	0
T5	43848	43368	0	0
T6	247464	246240	0	0
T7	55176	54480	0	0
T8	126912	126240	0	0
T9	52464	51480	0	0
T10	73080	71328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	623688	623160	0	0
T2	8148912	8147736	0	0
T3	58824	57744	0	0
T4	11136648	11135832	0	0
T5	43848	43368	0	0
T6	247464	246240	0	0
T7	55176	54480	0	0
T8	126912	126240	0	0
T9	52464	51480	0	0
T10	73080	71328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452796240	0	0
T1	623688	33000	0	0
T2	8148912	284329	0	0
T3	58824	1227	0	0
T4	11136648	568770	0	0
T5	43848	525	0	0
T6	247464	5296	0	0
T7	55176	723	0	0
T8	126912	3683	0	0
T9	52464	565	0	0
T10	73080	969	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33725655	0	0
T1	623688	2655	0	0
T2	8148912	786	0	0
T3	58824	1061	0	0
T4	11136648	27110	0	0
T5	43848	454	0	0
T6	247464	4500	0	0
T7	55176	567	0	0
T8	126912	3186	0	0
T9	52464	539	0	0
T10	73080	612	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52662	0	21600
T3	2451	2	0	1
T4	928054	0	0	2
T5	3654	0	0	2
T6	20622	9	0	2
T7	4598	0	0	2
T8	10576	12	0	2
T9	4372	0	0	2
T10	6090	0	0	2
T11	373218	40	0	2
T12	5911	12	0	1
T13	0	13	0	0
T14	0	1	0	0
T15	0	6	0	0
T16	0	31	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	16	0	0
T20	0	16	0	0
T21	0	13	0	0
T22	4500	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	623688	623160	0	0
T2	8148912	8147736	0	0
T3	58824	57744	0	0
T4	11136648	11135832	0	0
T5	43848	43368	0	0
T6	247464	246240	0	0
T7	55176	54480	0	0
T8	126912	126240	0	0
T9	52464	51480	0	0
T10	73080	71328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7854765	0	0
T1	623688	1489	0	0
T2	8148912	448	0	0
T3	58824	899	0	0
T4	11136648	439	0	0
T5	43848	416	0	0
T6	247464	4078	0	0
T7	55176	482	0	0
T8	126912	2673	0	0
T9	52464	464	0	0
T10	73080	531	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	863158	0	0
GntImpliesValid_A	420910071	863158	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	863158	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	11618402	0	0
ReadyAndValidImplyGrant_A	420910071	863158	0	0
ReqAndReadyImplyGrant_A	420910071	863158	0	0
ReqImpliesValid_A	420910071	2405488	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	863158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	11618402	0	0
T1	25987	1368	0	0
T2	339538	192	0	0
T3	2451	74	0	0
T4	464027	18677	0	0
T5	1827	39	0	0
T6	10311	390	0	0
T7	2299	39	0	0
T8	5288	205	0	0
T9	2186	34	0	0
T10	3045	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2405488	0	0
T1	25987	234	0	0
T2	339538	94	0	0
T3	2451	81	0	0
T4	464027	1028	0	0
T5	1827	72	0	0
T6	10311	547	0	0
T7	2299	78	0	0
T8	5288	384	0	0
T9	2186	51	0	0
T10	3045	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	863158	0	0
T1	25987	177	0	0
T2	339538	51	0	0
T3	2451	77	0	0
T4	464027	56	0	0
T5	1827	55	0	0
T6	10311	468	0	0
T7	2299	58	0	0
T8	5288	294	0	0
T9	2186	42	0	0
T10	3045	53	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	884139	0	0
GntImpliesValid_A	420910071	884139	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	884139	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	11443185	0	0
ReadyAndValidImplyGrant_A	420910071	884139	0	0
ReqAndReadyImplyGrant_A	420910071	884139	0	0
ReqImpliesValid_A	420910071	2558771	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	884139	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	11443185	0	0
T1	25987	1277	0	0
T2	339538	215	0	0
T3	2451	85	0	0
T4	464027	19081	0	0
T5	1827	33	0	0
T6	10311	375	0	0
T7	2299	49	0	0
T8	5288	209	0	0
T9	2186	36	0	0
T10	3045	44	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2558771	0	0
T1	25987	183	0	0
T2	339538	73	0	0
T3	2451	116	0	0
T4	464027	3650	0	0
T5	1827	44	0	0
T6	10311	522	0	0
T7	2299	64	0	0
T8	5288	358	0	0
T9	2186	71	0	0
T10	3045	73	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	884139	0	0
T1	25987	175	0	0
T2	339538	58	0	0
T3	2451	100	0	0
T4	464027	60	0	0
T5	1827	38	0	0
T6	10311	448	0	0
T7	2299	56	0	0
T8	5288	283	0	0
T9	2186	53	0	0
T10	3045	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	213276	0	0
GntImpliesValid_A	420910071	213276	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	213276	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2858572	0	0
ReadyAndValidImplyGrant_A	420910071	213276	0	0
ReqAndReadyImplyGrant_A	420910071	213276	0	0
ReqImpliesValid_A	420910071	535459	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	213276	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2858572	0	0
T1	25987	330	0	0
T2	339538	39	0	0
T3	2451	33	0	0
T4	464027	5845	0	0
T5	1827	11	0	0
T6	10311	108	0	0
T7	2299	16	0	0
T8	5288	59	0	0
T9	2186	14	0	0
T10	3045	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	535459	0	0
T1	25987	41	0	0
T2	339538	14	0	0
T3	2451	36	0	0
T4	464027	641	0	0
T5	1827	10	0	0
T6	10311	111	0	0
T7	2299	15	0	0
T8	5288	62	0	0
T9	2186	15	0	0
T10	3045	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213276	0	0
T1	25987	41	0	0
T2	339538	9	0	0
T3	2451	34	0	0
T4	464027	14	0	0
T5	1827	10	0	0
T6	10311	109	0	0
T7	2299	15	0	0
T8	5288	60	0	0
T9	2186	14	0	0
T10	3045	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	212836	0	0
GntImpliesValid_A	420910071	212836	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	212836	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2838333	0	0
ReadyAndValidImplyGrant_A	420910071	212836	0	0
ReqAndReadyImplyGrant_A	420910071	212836	0	0
ReqImpliesValid_A	420910071	551633	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	212836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2838333	0	0
T1	25987	402	0	0
T2	339538	32	0	0
T3	2451	26	0	0
T4	464027	2564	0	0
T5	1827	9	0	0
T6	10311	111	0	0
T7	2299	12	0	0
T8	5288	78	0	0
T9	2186	14	0	0
T10	3045	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	551633	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	29	0	0
T4	464027	446	0	0
T5	1827	10	0	0
T6	10311	124	0	0
T7	2299	11	0	0
T8	5288	91	0	0
T9	2186	15	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212836	0	0
T1	25987	51	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	10	0	0
T5	1827	9	0	0
T6	10311	117	0	0
T7	2299	11	0	0
T8	5288	84	0	0
T9	2186	14	0	0
T10	3045	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	220770	0	0
GntImpliesValid_A	420910071	220770	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	220770	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	5130771	0	0
ReadyAndValidImplyGrant_A	420910071	220770	0	0
ReqAndReadyImplyGrant_A	420910071	220770	0	0
ReqImpliesValid_A	420910071	1165816	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	220770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	5130771	0	0
T1	25987	365	0	0
T2	339538	98	0	0
T3	2451	132	0	0
T4	464027	2104	0	0
T5	1827	112	0	0
T6	10311	569	0	0
T7	2299	121	0	0
T8	5288	298	0	0
T9	2186	84	0	0
T10	3045	126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	1165816	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	31	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	156	0	0
T7	2299	21	0	0
T8	5288	104	0	0
T9	2186	28	0	0
T10	3045	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220770	0	0
T1	25987	41	0	0
T2	339538	8	0	0
T3	2451	20	0	0
T4	464027	8	0	0
T5	1827	12	0	0
T6	10311	110	0	0
T7	2299	14	0	0
T8	5288	68	0	0
T9	2186	15	0	0
T10	3045	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	231421	0	0
GntImpliesValid_A	420910071	231421	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	231421	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	5916692	0	0
ReadyAndValidImplyGrant_A	420910071	231421	0	0
ReqAndReadyImplyGrant_A	420910071	231421	0	0
ReqImpliesValid_A	420910071	1469702	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	231421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	5916692	0	0
T1	25987	312	0	0
T2	339538	267	0	0
T3	2451	276	0	0
T4	464027	2249	0	0
T5	1827	40	0	0
T6	10311	662	0	0
T7	2299	70	0	0
T8	5288	1067	0	0
T9	2186	109	0	0
T10	3045	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	1469702	0	0
T1	25987	40	0	0
T2	339538	23	0	0
T3	2451	107	0	0
T4	464027	10	0	0
T5	1827	13	0	0
T6	10311	134	0	0
T7	2299	10	0	0
T8	5288	206	0	0
T9	2186	32	0	0
T10	3045	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	231421	0	0
T1	25987	40	0	0
T2	339538	17	0	0
T3	2451	25	0	0
T4	464027	10	0	0
T5	1827	8	0	0
T6	10311	98	0	0
T7	2299	10	0	0
T8	5288	72	0	0
T9	2186	18	0	0
T10	3045	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	223748	0	0
GntImpliesValid_A	420910071	223748	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	223748	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	4265159	0	0
ReadyAndValidImplyGrant_A	420910071	223748	0	0
ReqAndReadyImplyGrant_A	420910071	223748	0	0
ReqImpliesValid_A	420910071	1056982	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	223748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	4265159	0	0
T1	25987	226	0	0
T2	339538	80	0	0
T3	2451	94	0	0
T4	464027	4135	0	0
T5	1827	48	0	0
T6	10311	858	0	0
T7	2299	199	0	0
T8	5288	438	0	0
T9	2186	60	0	0
T10	3045	108	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	1056982	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	31	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	215	0	0
T7	2299	44	0	0
T8	5288	177	0	0
T9	2186	18	0	0
T10	3045	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	223748	0	0
T1	25987	39	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	4	0	0
T5	1827	9	0	0
T6	10311	128	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	217648	0	0
GntImpliesValid_A	420910071	217648	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	217648	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	5146654	0	0
ReadyAndValidImplyGrant_A	420910071	217648	0	0
ReqAndReadyImplyGrant_A	420910071	217648	0	0
ReqImpliesValid_A	420910071	1176001	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	217648	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	5146654	0	0
T1	25987	571	0	0
T2	339538	112	0	0
T3	2451	124	0	0
T4	464027	1125	0	0
T5	1827	47	0	0
T6	10311	691	0	0
T7	2299	38	0	0
T8	5288	313	0	0
T9	2186	32	0	0
T10	3045	317	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	1176001	0	0
T1	25987	49	0	0
T2	339538	12	0	0
T3	2451	54	0	0
T4	464027	231	0	0
T5	1827	12	0	0
T6	10311	119	0	0
T7	2299	23	0	0
T8	5288	87	0	0
T9	2186	6	0	0
T10	3045	42	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	217648	0	0
T1	25987	47	0	0
T2	339538	10	0	0
T3	2451	31	0	0
T4	464027	13	0	0
T5	1827	12	0	0
T6	10311	105	0	0
T7	2299	10	0	0
T8	5288	62	0	0
T9	2186	6	0	0
T10	3045	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	212688	0	0
GntImpliesValid_A	420910071	212688	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	212688	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2814166	0	0
ReadyAndValidImplyGrant_A	420910071	212688	0	0
ReqAndReadyImplyGrant_A	420910071	212688	0	0
ReqImpliesValid_A	420910071	531250	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	212688	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2814166	0	0
T1	25987	348	0	0
T2	339538	57	0	0
T3	2451	27	0	0
T4	464027	2887	0	0
T5	1827	13	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	66	0	0
T9	2186	11	0	0
T10	3045	23	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	531250	0	0
T1	25987	49	0	0
T2	339538	10	0	0
T3	2451	28	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	107	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	12	0	0
T10	3045	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	212688	0	0
T1	25987	45	0	0
T2	339538	10	0	0
T3	2451	27	0	0
T4	464027	11	0	0
T5	1827	12	0	0
T6	10311	103	0	0
T7	2299	13	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	22	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	211624	0	0
GntImpliesValid_A	420910071	211624	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	211624	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2872831	0	0
ReadyAndValidImplyGrant_A	420910071	211624	0	0
ReqAndReadyImplyGrant_A	420910071	211624	0	0
ReqImpliesValid_A	420910071	534558	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	211624	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2872831	0	0
T1	25987	199	0	0
T2	339538	38	0	0
T3	2451	23	0	0
T4	464027	2705	0	0
T5	1827	16	0	0
T6	10311	100	0	0
T7	2299	12	0	0
T8	5288	82	0	0
T9	2186	12	0	0
T10	3045	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	534558	0	0
T1	25987	36	0	0
T2	339538	7	0	0
T3	2451	24	0	0
T4	464027	8	0	0
T5	1827	17	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	89	0	0
T9	2186	19	0	0
T10	3045	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	211624	0	0
T1	25987	28	0	0
T2	339538	7	0	0
T3	2451	23	0	0
T4	464027	8	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	85	0	0
T9	2186	15	0	0
T10	3045	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	210623	0	0
GntImpliesValid_A	420910071	210623	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	210623	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2829813	0	0
ReadyAndValidImplyGrant_A	420910071	210623	0	0
ReqAndReadyImplyGrant_A	420910071	210623	0	0
ReqImpliesValid_A	420910071	539614	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	210623	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2829813	0	0
T1	25987	503	0	0
T2	339538	52	0	0
T3	2451	21	0	0
T4	464027	2779	0	0
T5	1827	16	0	0
T6	10311	117	0	0
T7	2299	9	0	0
T8	5288	67	0	0
T9	2186	17	0	0
T10	3045	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	539614	0	0
T1	25987	62	0	0
T2	339538	11	0	0
T3	2451	22	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	132	0	0
T7	2299	8	0	0
T8	5288	74	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	210623	0	0
T1	25987	52	0	0
T2	339538	11	0	0
T3	2451	21	0	0
T4	464027	6	0	0
T5	1827	15	0	0
T6	10311	124	0	0
T7	2299	8	0	0
T8	5288	70	0	0
T9	2186	16	0	0
T10	3045	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T5,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T5,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T5,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	209243	0	0
GntImpliesValid_A	420910071	209243	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	209243	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2846909	0	0
ReadyAndValidImplyGrant_A	420910071	209243	0	0
ReqAndReadyImplyGrant_A	420910071	209243	0	0
ReqImpliesValid_A	420910071	545826	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	209243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2846909	0	0
T1	25987	300	0	0
T2	339538	33	0	0
T3	2451	24	0	0
T4	464027	3414	0	0
T5	1827	11	0	0
T6	10311	108	0	0
T7	2299	11	0	0
T8	5288	88	0	0
T9	2186	8	0	0
T10	3045	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	545826	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	111	0	0
T7	2299	10	0	0
T8	5288	99	0	0
T9	2186	7	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209243	0	0
T1	25987	34	0	0
T2	339538	11	0	0
T3	2451	23	0	0
T4	464027	10	0	0
T5	1827	12	0	0
T6	10311	109	0	0
T7	2299	10	0	0
T8	5288	93	0	0
T9	2186	7	0	0
T10	3045	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	218757	0	0
GntImpliesValid_A	420910071	218757	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	218757	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2848852	0	0
ReadyAndValidImplyGrant_A	420910071	218757	0	0
ReqAndReadyImplyGrant_A	420910071	218757	0	0
ReqImpliesValid_A	420910071	510522	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	218757	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2848852	0	0
T1	25987	300	0	0
T2	339538	56	0	0
T3	2451	26	0	0
T4	464027	3021	0	0
T5	1827	11	0	0
T6	10311	100	0	0
T7	2299	9	0	0
T8	5288	87	0	0
T9	2186	17	0	0
T10	3045	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	510522	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	563	0	0
T5	1827	10	0	0
T6	10311	107	0	0
T7	2299	10	0	0
T8	5288	100	0	0
T9	2186	18	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218757	0	0
T1	25987	37	0	0
T2	339538	13	0	0
T3	2451	25	0	0
T4	464027	13	0	0
T5	1827	10	0	0
T6	10311	103	0	0
T7	2299	9	0	0
T8	5288	93	0	0
T9	2186	17	0	0
T10	3045	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	215452	0	0
GntImpliesValid_A	420910071	215452	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	215452	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2875862	0	0
ReadyAndValidImplyGrant_A	420910071	215452	0	0
ReqAndReadyImplyGrant_A	420910071	215452	0	0
ReqImpliesValid_A	420910071	564134	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	215452	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2875862	0	0
T1	25987	326	0	0
T2	339538	19	0	0
T3	2451	33	0	0
T4	464027	2679	0	0
T5	1827	13	0	0
T6	10311	122	0	0
T7	2299	13	0	0
T8	5288	82	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	564134	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	38	0	0
T4	464027	10	0	0
T5	1827	16	0	0
T6	10311	137	0	0
T7	2299	12	0	0
T8	5288	97	0	0
T9	2186	17	0	0
T10	3045	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215452	0	0
T1	25987	36	0	0
T2	339538	5	0	0
T3	2451	35	0	0
T4	464027	10	0	0
T5	1827	14	0	0
T6	10311	129	0	0
T7	2299	12	0	0
T8	5288	89	0	0
T9	2186	16	0	0
T10	3045	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	215066	0	0
GntImpliesValid_A	420910071	215066	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	215066	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2757971	0	0
ReadyAndValidImplyGrant_A	420910071	215066	0	0
ReqAndReadyImplyGrant_A	420910071	215066	0	0
ReqImpliesValid_A	420910071	537069	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	215066	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2757971	0	0
T1	25987	322	0	0
T2	339538	70	0	0
T3	2451	27	0	0
T4	464027	4705	0	0
T5	1827	7	0	0
T6	10311	96	0	0
T7	2299	15	0	0
T8	5288	57	0	0
T9	2186	10	0	0
T10	3045	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	537069	0	0
T1	25987	45	0	0
T2	339538	20	0	0
T3	2451	28	0	0
T4	464027	297	0	0
T5	1827	8	0	0
T6	10311	105	0	0
T7	2299	14	0	0
T8	5288	60	0	0
T9	2186	9	0	0
T10	3045	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	215066	0	0
T1	25987	45	0	0
T2	339538	15	0	0
T3	2451	27	0	0
T4	464027	12	0	0
T5	1827	7	0	0
T6	10311	100	0	0
T7	2299	14	0	0
T8	5288	58	0	0
T9	2186	9	0	0
T10	3045	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	220657	0	0
GntImpliesValid_A	420910071	220657	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	220657	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2850354	0	0
ReadyAndValidImplyGrant_A	420910071	220657	0	0
ReqAndReadyImplyGrant_A	420910071	220657	0	0
ReqImpliesValid_A	420910071	568092	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	220657	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2850354	0	0
T1	25987	391	0	0
T2	339538	41	0	0
T3	2451	17	0	0
T4	464027	2133	0	0
T5	1827	13	0	0
T6	10311	99	0	0
T7	2299	15	0	0
T8	5288	69	0	0
T9	2186	10	0	0
T10	3045	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	568092	0	0
T1	25987	52	0	0
T2	339538	13	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	14	0	0
T6	10311	106	0	0
T7	2299	14	0	0
T8	5288	72	0	0
T9	2186	9	0	0
T10	3045	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	220657	0	0
T1	25987	51	0	0
T2	339538	12	0	0
T3	2451	16	0	0
T4	464027	7	0	0
T5	1827	13	0	0
T6	10311	102	0	0
T7	2299	14	0	0
T8	5288	70	0	0
T9	2186	9	0	0
T10	3045	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	237936	0	0
GntImpliesValid_A	420910071	237936	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	237936	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2940965	0	0
ReadyAndValidImplyGrant_A	420910071	237936	0	0
ReqAndReadyImplyGrant_A	420910071	237936	0	0
ReqImpliesValid_A	420910071	583472	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	237936	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2940965	0	0
T1	25987	298	0	0
T2	339538	74	0	0
T3	2451	45	0	0
T4	464027	2482	0	0
T5	1827	9	0	0
T6	10311	167	0	0
T7	2299	12	0	0
T8	5288	65	0	0
T9	2186	17	0	0
T10	3045	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	583472	0	0
T1	25987	38	0	0
T2	339538	33	0	0
T3	2451	46	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	194	0	0
T7	2299	11	0	0
T8	5288	66	0	0
T9	2186	16	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	237936	0	0
T1	25987	38	0	0
T2	339538	18	0	0
T3	2451	45	0	0
T4	464027	8	0	0
T5	1827	8	0	0
T6	10311	180	0	0
T7	2299	11	0	0
T8	5288	65	0	0
T9	2186	16	0	0
T10	3045	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	213421	0	0
GntImpliesValid_A	420910071	213421	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	213421	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2807805	0	0
ReadyAndValidImplyGrant_A	420910071	213421	0	0
ReqAndReadyImplyGrant_A	420910071	213421	0	0
ReqImpliesValid_A	420910071	562186	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	213421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2807805	0	0
T1	25987	306	0	0
T2	339538	46	0	0
T3	2451	29	0	0
T4	464027	3805	0	0
T5	1827	18	0	0
T6	10311	109	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	562186	0	0
T1	25987	49	0	0
T2	339538	30	0	0
T3	2451	36	0	0
T4	464027	11	0	0
T5	1827	19	0	0
T6	10311	122	0	0
T7	2299	17	0	0
T8	5288	77	0	0
T9	2186	15	0	0
T10	3045	22	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	213421	0	0
T1	25987	39	0	0
T2	339538	17	0	0
T3	2451	32	0	0
T4	464027	11	0	0
T5	1827	18	0	0
T6	10311	115	0	0
T7	2299	16	0	0
T8	5288	76	0	0
T9	2186	14	0	0
T10	3045	21	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T6,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T6,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	209290	0	0
GntImpliesValid_A	420910071	209290	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	209290	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2854711	0	0
ReadyAndValidImplyGrant_A	420910071	209290	0	0
ReqAndReadyImplyGrant_A	420910071	209290	0	0
ReqImpliesValid_A	420910071	518719	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	209290	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2854711	0	0
T1	25987	304	0	0
T2	339538	77	0	0
T3	2451	24	0	0
T4	464027	6710	0	0
T5	1827	11	0	0
T6	10311	105	0	0
T7	2299	13	0	0
T8	5288	73	0	0
T9	2186	12	0	0
T10	3045	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	518719	0	0
T1	25987	41	0	0
T2	339538	26	0	0
T3	2451	23	0	0
T4	464027	73	0	0
T5	1827	12	0	0
T6	10311	116	0	0
T7	2299	14	0	0
T8	5288	86	0	0
T9	2186	11	0	0
T10	3045	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	209290	0	0
T1	25987	41	0	0
T2	339538	19	0	0
T3	2451	23	0	0
T4	464027	16	0	0
T5	1827	11	0	0
T6	10311	110	0	0
T7	2299	13	0	0
T8	5288	79	0	0
T9	2186	11	0	0
T10	3045	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	214556	0	0
GntImpliesValid_A	420910071	214556	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	214556	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2841942	0	0
ReadyAndValidImplyGrant_A	420910071	214556	0	0
ReqAndReadyImplyGrant_A	420910071	214556	0	0
ReqImpliesValid_A	420910071	525129	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	214556	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2841942	0	0
T1	25987	333	0	0
T2	339538	34	0	0
T3	2451	36	0	0
T4	464027	1376	0	0
T5	1827	14	0	0
T6	10311	100	0	0
T7	2299	15	0	0
T8	5288	74	0	0
T9	2186	13	0	0
T10	3045	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	525129	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	39	0	0
T4	464027	122	0	0
T5	1827	13	0	0
T6	10311	111	0	0
T7	2299	18	0	0
T8	5288	83	0	0
T9	2186	14	0	0
T10	3045	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	214556	0	0
T1	25987	37	0	0
T2	339538	10	0	0
T3	2451	37	0	0
T4	464027	9	0	0
T5	1827	13	0	0
T6	10311	105	0	0
T7	2299	16	0	0
T8	5288	78	0	0
T9	2186	13	0	0
T10	3045	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	218664	0	0
GntImpliesValid_A	420910071	218664	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	218664	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2841495	0	0
ReadyAndValidImplyGrant_A	420910071	218664	0	0
ReqAndReadyImplyGrant_A	420910071	218664	0	0
ReqImpliesValid_A	420910071	552790	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	218664	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2841495	0	0
T1	25987	288	0	0
T2	339538	52	0	0
T3	2451	25	0	0
T4	464027	4853	0	0
T5	1827	16	0	0
T6	10311	108	0	0
T7	2299	12	0	0
T8	5288	64	0	0
T9	2186	13	0	0
T10	3045	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	552790	0	0
T1	25987	62	0	0
T2	339538	18	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	119	0	0
T7	2299	13	0	0
T8	5288	73	0	0
T9	2186	16	0	0
T10	3045	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218664	0	0
T1	25987	43	0	0
T2	339538	13	0	0
T3	2451	24	0	0
T4	464027	14	0	0
T5	1827	15	0	0
T6	10311	113	0	0
T7	2299	12	0	0
T8	5288	68	0	0
T9	2186	14	0	0
T10	3045	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	218620	0	0
GntImpliesValid_A	420910071	218620	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	218620	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	2891734	0	0
ReadyAndValidImplyGrant_A	420910071	218620	0	0
ReqAndReadyImplyGrant_A	420910071	218620	0	0
ReqImpliesValid_A	420910071	553407	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	0	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	218620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2891734	0	0
T1	25987	305	0	0
T2	339538	57	0	0
T3	2451	24	0	0
T4	464027	5819	0	0
T5	1827	16	0	0
T6	10311	99	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	553407	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	323	0	0
T5	1827	15	0	0
T6	10311	104	0	0
T7	2299	12	0	0
T8	5288	65	0	0
T9	2186	11	0	0
T10	3045	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	218620	0	0
T1	25987	42	0	0
T2	339538	16	0	0
T3	2451	23	0	0
T4	464027	13	0	0
T5	1827	15	0	0
T6	10311	101	0	0
T7	2299	11	0	0
T8	5288	64	0	0
T9	2186	10	0	0
T10	3045	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	889832	0	0
GntImpliesValid_A	420910071	889832	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	889832	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	10909507	0	0
ReadyAndValidImplyGrant_A	420910071	889832	0	0
ReqAndReadyImplyGrant_A	420910071	889832	0	0
ReqImpliesValid_A	420910071	2359086	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	22428	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	889832	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	10909507	0	0
T1	25987	1044	0	0
T2	339538	140	0	0
T3	2451	1	0	0
T4	464027	18569	0	0
T5	1827	1	0	0
T6	10311	1	0	0
T7	2299	1	0	0
T8	5288	1	0	0
T9	2186	1	0	0
T10	3045	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	2359086	0	0
T1	25987	177	0	0
T2	339538	53	0	0
T3	2451	86	0	0
T4	464027	1551	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	22428	0	900
T3	2451	2	0	1
T4	464027	0	0	1
T5	1827	0	0	1
T6	10311	4	0	1
T7	2299	0	0	1
T8	5288	7	0	1
T9	2186	0	0	1
T10	3045	0	0	1
T11	186609	39	0	1
T12	0	8	0	0
T15	0	3	0	0
T16	0	16	0	0
T17	0	17	0	0
T20	0	16	0	0
T21	0	13	0	0
T22	2250	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	889832	0	0
T1	25987	158	0	0
T2	339538	46	0	0
T3	2451	86	0	0
T4	464027	58	0	0
T5	1827	48	0	0
T6	10311	455	0	0
T7	2299	51	0	0
T8	5288	311	0	0
T9	2186	60	0	0
T10	3045	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420910071	420792219	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420910071	871340	0	0
GntImpliesValid_A	420910071	871340	0	0
GrantKnown_A	420910071	420792219	0	0
IdxKnown_A	420910071	420792219	0	0
IndexIsCorrect_A	420910071	871340	0	0
LockArbDecision_A	420910071	0	0	0
NoReadyValidNoGrant_A	420910071	352793555	0	0
ReadyAndValidImplyGrant_A	420910071	871340	0	0
ReqAndReadyImplyGrant_A	420910071	871340	0	0
ReqImpliesValid_A	420910071	12819949	0	0
ReqStaysHighUntilGranted0_M	420910071	0	0	0
RoundRobin_A	420910071	30234	0	900
ValidKnown_A	420910071	420792219	0	0
gen_data_port_assertion.DataFlow_A	420910071	871340	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	352793555	0	0
T1	25987	22582	0	0
T2	339538	282448	0	0
T3	2451	1	0	0
T4	464027	445053	0	0
T5	1827	1	0	0
T6	10311	1	0	0
T7	2299	1	0	0
T8	5288	1	0	0
T9	2186	1	0	0
T10	3045	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	12819949	0	0
T1	25987	1180	0	0
T2	339538	259	0	0
T3	2451	95	0	0
T4	464027	18078	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	30234	0	900
T4	464027	0	0	1
T5	1827	0	0	1
T6	10311	5	0	1
T7	2299	0	0	1
T8	5288	5	0	1
T9	2186	0	0	1
T10	3045	0	0	1
T11	186609	1	0	1
T12	5911	4	0	1
T13	0	13	0	0
T14	0	1	0	0
T15	0	3	0	0
T16	0	15	0	0
T18	0	19	0	0
T19	0	16	0	0
T22	2250	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	420792219	0	0
T1	25987	25965	0	0
T2	339538	339489	0	0
T3	2451	2406	0	0
T4	464027	463993	0	0
T5	1827	1807	0	0
T6	10311	10260	0	0
T7	2299	2270	0	0
T8	5288	5260	0	0
T9	2186	2145	0	0
T10	3045	2972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420910071	871340	0	0
T1	25987	152	0	0
T2	339538	55	0	0
T3	2451	95	0	0
T4	464027	58	0	0
T5	1827	36	0	0
T6	10311	447	0	0
T7	2299	73	0	0
T8	5288	300	0	0
T9	2186	53	0	0
T10	3045	48	0	0