Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1654969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262984

1

T1

19

T2

544

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650862	1			T1	58		T2	1380		T3	116
values[0x0]	616923	1			T1	49		T2	1321		T3	27
values[0x1]	650168	1			T1	53		T2	1368		T3	128

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

637890

1

T1

50

T2

1331

T3

112

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29825	1			T1	1		T2	58		T3	1
valid_sources[0x01]	30249	1			T1	4		T2	68		T3	8
valid_sources[0x02]	30606	1			T1	5		T2	60		T3	9
valid_sources[0x03]	29760	1			T2	54		T3	4		T4	2
valid_sources[0x04]	30876	1			T1	1		T2	61		T3	7
valid_sources[0x05]	29503	1			T1	3		T2	64		T3	3
valid_sources[0x06]	30879	1			T1	3		T2	72		T3	6
valid_sources[0x07]	30107	1			T1	2		T2	68		T3	4
valid_sources[0x08]	30965	1			T1	5		T2	63		T3	6
valid_sources[0x09]	29748	1			T2	75		T3	3		T6	133
valid_sources[0x0a]	29841	1			T1	5		T2	55		T3	2
valid_sources[0x0b]	30111	1			T1	14		T2	61		T3	7
valid_sources[0x0c]	28995	1			T1	7		T2	47		T3	1
valid_sources[0x0d]	29177	1			T1	13		T2	72		T3	4
valid_sources[0x0e]	30545	1			T1	2		T2	65		T3	6
valid_sources[0x0f]	29301	1			T2	64		T3	4		T4	3
valid_sources[0x10]	30360	1			T2	70		T3	9		T4	3
valid_sources[0x11]	29559	1			T2	72		T3	2		T6	95
valid_sources[0x12]	29481	1			T2	70		T3	4		T4	2
valid_sources[0x13]	30370	1			T1	2		T2	62		T3	2
valid_sources[0x14]	29635	1			T1	4		T2	64		T3	3
valid_sources[0x15]	29879	1			T1	4		T2	65		T3	5
valid_sources[0x16]	29079	1			T2	63		T3	4		T4	3
valid_sources[0x17]	30296	1			T1	2		T2	58		T3	7
valid_sources[0x18]	29016	1			T2	67		T3	4		T4	2
valid_sources[0x19]	29742	1			T2	58		T3	4		T6	87
valid_sources[0x1a]	29867	1			T1	2		T2	59		T3	6
valid_sources[0x1b]	29725	1			T1	4		T2	65		T3	6
valid_sources[0x1c]	30725	1			T2	65		T3	2		T4	3
valid_sources[0x1d]	29700	1			T1	9		T2	56		T3	4
valid_sources[0x1e]	29965	1			T2	62		T3	3		T6	55
valid_sources[0x1f]	30610	1			T2	65		T3	2		T4	3
valid_sources[0x20]	29172	1			T1	1		T2	69		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27774

1

T1

1

T2

47

T3

12

values[0x0]

all_enables

biggest_size

207575

1

T1

16

T2

441

T3

15

values[0x1]

all_enables

biggest_size

27635

1

T1

2

T2

56

T3

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1673263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

272404

1

T1

30

T2

572

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	664181	1			T1	68		T2	1290		T3	142
values[0x0]	614776	1			T1	56		T2	1267		T3	26
values[0x1]	666710	1			T1	73		T2	1256		T3	138

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1284948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

660719

1

T1

70

T2

1283

T3

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30144	1			T1	2		T2	56		T3	2
valid_sources[0x01]	30349	1			T2	54		T3	5		T5	14
valid_sources[0x02]	30990	1			T1	4		T2	51		T3	7
valid_sources[0x03]	29930	1			T2	49		T3	4		T4	12
valid_sources[0x04]	30324	1			T2	60		T5	2		T6	95
valid_sources[0x05]	29761	1			T1	2		T2	47		T3	7
valid_sources[0x06]	30001	1			T1	3		T2	59		T3	3
valid_sources[0x07]	30172	1			T1	1		T2	48		T3	5
valid_sources[0x08]	30559	1			T1	3		T2	57		T3	4
valid_sources[0x09]	29691	1			T1	12		T2	51		T3	2
valid_sources[0x0a]	29665	1			T2	49		T3	6		T5	9
valid_sources[0x0b]	30961	1			T1	11		T2	79		T3	6
valid_sources[0x0c]	30482	1			T2	50		T3	6		T4	10
valid_sources[0x0d]	30533	1			T1	2		T2	66		T3	4
valid_sources[0x0e]	30089	1			T1	6		T2	57		T3	2
valid_sources[0x0f]	30471	1			T1	10		T2	59		T3	2
valid_sources[0x10]	30329	1			T2	44		T3	2		T4	9
valid_sources[0x11]	30791	1			T1	8		T2	46		T3	2
valid_sources[0x12]	30437	1			T1	1		T2	59		T3	5
valid_sources[0x13]	30620	1			T1	8		T2	60		T3	11
valid_sources[0x14]	31053	1			T2	79		T3	6		T5	1
valid_sources[0x15]	30620	1			T1	3		T2	62		T3	5
valid_sources[0x16]	30459	1			T2	63		T3	1		T5	6
valid_sources[0x17]	30409	1			T2	46		T3	7		T6	53
valid_sources[0x18]	29955	1			T2	106		T3	2		T6	71
valid_sources[0x19]	30195	1			T2	47		T3	8		T4	3
valid_sources[0x1a]	30272	1			T1	1		T2	48		T3	3
valid_sources[0x1b]	30617	1			T1	3		T2	75		T3	9
valid_sources[0x1c]	30034	1			T1	2		T2	68		T3	2
valid_sources[0x1d]	30155	1			T1	3		T2	53		T3	11
valid_sources[0x1e]	30241	1			T1	3		T2	64		T3	7
valid_sources[0x1f]	30565	1			T1	12		T2	55		T3	3
valid_sources[0x20]	30242	1			T1	1		T2	55		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28679

1

T1

3

T2

52

T3

8

values[0x0]

all_enables

biggest_size

215313

1

T1

23

T2

459

T3

12

values[0x1]

all_enables

biggest_size

28412

1

T1

4

T2

61

T3

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1665311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264681

1

T1

24

T2

583

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	654761	1			T1	59		T2	1311		T3	152
values[0x0]	621680	1			T1	52		T2	1351		T3	22
values[0x1]	653551	1			T1	64		T2	1303		T3	136

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1288195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

641797

1

T1

61

T2

1338

T3

118

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30363	1			T1	5		T2	67		T3	3
valid_sources[0x01]	29801	1			T1	2		T2	59		T3	10
valid_sources[0x02]	31309	1			T1	6		T2	61		T3	7
valid_sources[0x03]	29885	1			T1	1		T2	78		T3	4
valid_sources[0x04]	31406	1			T1	4		T2	73		T3	1
valid_sources[0x05]	29672	1			T1	1		T2	62		T3	4
valid_sources[0x06]	30129	1			T2	68		T3	3		T4	2
valid_sources[0x07]	29626	1			T1	1		T2	62		T3	5
valid_sources[0x08]	29279	1			T1	3		T2	63		T3	8
valid_sources[0x09]	29790	1			T1	1		T2	47		T3	6
valid_sources[0x0a]	30064	1			T1	3		T2	65		T3	8
valid_sources[0x0b]	31180	1			T1	4		T2	49		T3	11
valid_sources[0x0c]	29645	1			T1	3		T2	64		T3	5
valid_sources[0x0d]	29512	1			T1	3		T2	54		T3	6
valid_sources[0x0e]	30039	1			T1	1		T2	51		T3	5
valid_sources[0x0f]	29289	1			T1	3		T2	55		T3	5
valid_sources[0x10]	29456	1			T1	1		T2	59		T3	3
valid_sources[0x11]	29926	1			T1	4		T2	56		T3	7
valid_sources[0x12]	29364	1			T1	3		T2	55		T3	10
valid_sources[0x13]	30363	1			T2	71		T3	7		T4	1
valid_sources[0x14]	30682	1			T1	1		T2	63		T3	2
valid_sources[0x15]	28931	1			T1	2		T2	58		T3	6
valid_sources[0x16]	31047	1			T1	4		T2	66		T3	5
valid_sources[0x17]	30451	1			T1	5		T2	59		T3	5
valid_sources[0x18]	30241	1			T1	3		T2	56		T3	5
valid_sources[0x19]	30071	1			T1	4		T2	63		T3	10
valid_sources[0x1a]	30569	1			T1	4		T2	55		T3	8
valid_sources[0x1b]	29869	1			T1	5		T2	65		T3	4
valid_sources[0x1c]	29635	1			T1	9		T2	73		T3	3
valid_sources[0x1d]	29003	1			T1	3		T2	60		T3	6
valid_sources[0x1e]	30099	1			T1	4		T2	58		T3	8
valid_sources[0x1f]	30035	1			T1	1		T2	52		T3	6
valid_sources[0x20]	29919	1			T1	1		T2	58		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27274

1

T1

4

T2

62

T3

8

values[0x0]

all_enables

biggest_size

209782

1

T1

19

T2

474

T3

8

values[0x1]

all_enables

biggest_size

27625

1

T1

1

T2

47

T3

16