Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8192797	0	0
GntImpliesValid_A	2147483647	8192797	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8192797	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	451077830	0	0
ReadyAndValidImplyGrant_A	2147483647	8192797	0	0
ReqAndReadyImplyGrant_A	2147483647	8192797	0	0
ReqImpliesValid_A	2147483647	33062325	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	54497	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8192797	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6662280	6661392	0	0
T2	11580120	11580024	0	0
T3	799056	770496	0	0
T4	5887104	5886624	0	0
T5	314232	313800	0	0
T6	829392	826320	0	0
T7	8430264	8424984	0	0
T8	1467912	1467624	0	0
T9	2154096	2153448	0	0
T10	10888080	10887912	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6662280	6661392	0	0
T2	11580120	11580024	0	0
T3	799056	770496	0	0
T4	5887104	5886624	0	0
T5	314232	313800	0	0
T6	829392	826320	0	0
T7	8430264	8424984	0	0
T8	1467912	1467624	0	0
T9	2154096	2153448	0	0
T10	10888080	10887912	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6662280	6661392	0	0
T2	11580120	11580024	0	0
T3	799056	770496	0	0
T4	5887104	5886624	0	0
T5	314232	313800	0	0
T6	829392	826320	0	0
T7	8430264	8424984	0	0
T8	1467912	1467624	0	0
T9	2154096	2153448	0	0
T10	10888080	10887912	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	451077830	0	0
T1	6662280	233397	0	0
T2	11580120	440930	0	0
T3	799056	19813	0	0
T4	5887104	205762	0	0
T5	314232	19324	0	0
T6	829392	11295	0	0
T7	8430264	504492	0	0
T8	1467912	80370	0	0
T9	2154096	106744	0	0
T10	10888080	412509	0	0
T11	0	8647	0	0
T12	0	10952	0	0
T13	0	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33062325	0	0
T1	6662280	825	0	0
T2	11580120	28155	0	0
T3	799056	20167	0	0
T4	5887104	700	0	0
T5	314232	2954	0	0
T6	829392	32147	0	0
T7	8430264	103841	0	0
T8	1467912	9028	0	0
T9	2154096	59839	0	0
T10	10888080	25781	0	0
T11	0	2659	0	0
T12	0	5201	0	0
T13	0	9474	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54497	0	21600
T3	66588	154	0	2
T4	490592	0	0	2
T5	26186	0	0	2
T6	69116	741	0	2
T7	702522	3	0	2
T8	122326	2	0	2
T9	179508	6	0	2
T10	907340	5	0	2
T11	125664	0	0	2
T12	160044	1	0	2
T13	0	898	0	0
T14	0	13	0	0
T15	0	16	0	0
T16	0	4	0	0
T17	0	13	0	0
T18	0	155	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6662280	6661392	0	0
T2	11580120	11580024	0	0
T3	799056	770496	0	0
T4	5887104	5886624	0	0
T5	314232	313800	0	0
T6	829392	826320	0	0
T7	8430264	8424984	0	0
T8	1467912	1467624	0	0
T9	2154096	2153448	0	0
T10	10888080	10887912	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192797	0	0
T1	6662280	532	0	0
T2	11580120	11843	0	0
T3	799056	17209	0	0
T4	5887104	407	0	0
T5	314232	1323	0	0
T6	829392	17218	0	0
T7	8430264	29511	0	0
T8	1467912	4316	0	0
T9	2154096	9403	0	0
T10	10888080	8875	0	0
T11	0	1782	0	0
T12	0	3079	0	0
T13	0	828	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	912716	0	0
GntImpliesValid_A	419235966	912716	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	912716	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	11394457	0	0
ReadyAndValidImplyGrant_A	419235966	912716	0	0
ReqAndReadyImplyGrant_A	419235966	912716	0	0
ReqImpliesValid_A	419235966	2380510	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	912716	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	11394457	0	0
T1	277595	302	0	0
T2	482505	5666	0	0
T3	33294	1420	0	0
T4	245296	278	0	0
T5	13093	830	0	0
T6	34558	1074	0	0
T7	351261	22812	0	0
T8	61163	3421	0	0
T9	89754	5423	0	0
T10	453670	6677	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2380510	0	0
T1	277595	88	0	0
T2	482505	2970	0	0
T3	33294	2147	0	0
T4	245296	87	0	0
T5	13093	277	0	0
T6	34558	1926	0	0
T7	351261	19570	0	0
T8	61163	796	0	0
T9	89754	1154	0	0
T10	453670	4177	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	912716	0	0
T1	277595	70	0	0
T2	482505	1523	0	0
T3	33294	1778	0	0
T4	245296	57	0	0
T5	13093	135	0	0
T6	34558	1499	0	0
T7	351261	4302	0	0
T8	61163	482	0	0
T9	89754	713	0	0
T10	453670	1955	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	930031	0	0
GntImpliesValid_A	419235966	930031	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	930031	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	11374303	0	0
ReadyAndValidImplyGrant_A	419235966	930031	0	0
ReqAndReadyImplyGrant_A	419235966	930031	0	0
ReqImpliesValid_A	419235966	2554954	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	930031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	11374303	0	0
T1	277595	273	0	0
T2	482505	7991	0	0
T3	33294	1634	0	0
T4	245296	217	0	0
T5	13093	977	0	0
T6	34558	1098	0	0
T7	351261	20124	0	0
T8	61163	3340	0	0
T9	89754	5733	0	0
T10	453670	4298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2554954	0	0
T1	277595	91	0	0
T2	482505	4841	0	0
T3	33294	3205	0	0
T4	245296	76	0	0
T5	13093	267	0	0
T6	34558	1892	0	0
T7	351261	4132	0	0
T8	61163	650	0	0
T9	89754	1237	0	0
T10	453670	2602	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	930031	0	0
T1	277595	66	0	0
T2	482505	2261	0	0
T3	33294	2414	0	0
T4	245296	51	0	0
T5	13093	147	0	0
T6	34558	1494	0	0
T7	351261	2716	0	0
T8	61163	453	0	0
T9	89754	738	0	0
T10	453670	1226	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	226215	0	0
GntImpliesValid_A	419235966	226215	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	226215	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2827860	0	0
ReadyAndValidImplyGrant_A	419235966	226215	0	0
ReqAndReadyImplyGrant_A	419235966	226215	0	0
ReqImpliesValid_A	419235966	519273	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	226215	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2827860	0	0
T1	277595	48	0	0
T2	482505	1840	0	0
T3	33294	283	0	0
T4	245296	39	0	0
T5	13093	296	0	0
T6	34558	717	0	0
T7	351261	3721	0	0
T8	61163	863	0	0
T9	89754	1	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	519273	0	0
T1	277595	13	0	0
T2	482505	1238	0	0
T3	33294	276	0	0
T4	245296	10	0	0
T5	13093	76	0	0
T6	34558	1297	0	0
T7	351261	563	0	0
T8	61163	174	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	118	0	0
T12	0	293	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226215	0	0
T1	277595	13	0	0
T2	482505	550	0	0
T3	33294	274	0	0
T4	245296	8	0	0
T5	13093	41	0	0
T6	34558	1006	0	0
T7	351261	508	0	0
T8	61163	107	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	110	0	0
T12	0	224	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	231356	0	0
GntImpliesValid_A	419235966	231356	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	231356	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2860153	0	0
ReadyAndValidImplyGrant_A	419235966	231356	0	0
ReqAndReadyImplyGrant_A	419235966	231356	0	0
ReqImpliesValid_A	419235966	563943	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	231356	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2860153	0	0
T1	277595	82	0	0
T2	482505	3144	0	0
T3	33294	305	0	0
T4	245296	67	0	0
T5	13093	237	0	0
T6	34558	477	0	0
T7	351261	4073	0	0
T8	61163	964	0	0
T9	89754	727	0	0
T10	453670	1549	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	563943	0	0
T1	277595	17	0	0
T2	482505	2356	0	0
T3	33294	302	0	0
T4	245296	10	0	0
T5	13093	33	0	0
T6	34558	635	0	0
T7	351261	644	0	0
T8	61163	158	0	0
T9	89754	4882	0	0
T10	453670	1232	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	231356	0	0
T1	277595	17	0	0
T2	482505	981	0	0
T3	33294	298	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	555	0	0
T7	351261	541	0	0
T8	61163	119	0	0
T9	89754	494	0	0
T10	453670	496	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	222435	0	0
GntImpliesValid_A	419235966	222435	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	222435	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	5626598	0	0
ReadyAndValidImplyGrant_A	419235966	222435	0	0
ReqAndReadyImplyGrant_A	419235966	222435	0	0
ReqImpliesValid_A	419235966	1180961	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	222435	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	5626598	0	0
T1	277595	75	0	0
T2	482505	0	0	0
T3	33294	3257	0	0
T4	245296	39	0	0
T5	13093	262	0	0
T6	34558	1675	0	0
T7	351261	14097	0	0
T8	61163	1497	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	3580	0	0
T12	0	2927	0	0
T13	0	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	1180961	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	801	0	0
T4	245296	10	0	0
T5	13093	46	0	0
T6	34558	2762	0	0
T7	351261	1087	0	0
T8	61163	166	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	359	0	0
T12	0	435	0	0
T13	0	2910	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222435	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	410	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	617	0	0
T7	351261	529	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	101	0	0
T12	0	196	0	0
T13	0	456	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	213195	0	0
GntImpliesValid_A	419235966	213195	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	213195	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	5311123	0	0
ReadyAndValidImplyGrant_A	419235966	213195	0	0
ReqAndReadyImplyGrant_A	419235966	213195	0	0
ReqImpliesValid_A	419235966	1007112	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	213195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	5311123	0	0
T1	277595	101	0	0
T2	482505	0	0	0
T3	33294	2069	0	0
T4	245296	80	0	0
T5	13093	167	0	0
T6	34558	945	0	0
T7	351261	27932	0	0
T8	61163	561	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	1310	0	0
T12	0	1721	0	0
T13	0	40	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	1007112	0	0
T1	277595	23	0	0
T2	482505	0	0	0
T3	33294	440	0	0
T4	245296	26	0	0
T5	13093	40	0	0
T6	34558	10329	0	0
T7	351261	10821	0	0
T8	61163	126	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	102	0	0
T12	0	371	0	0
T13	0	6564	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	213195	0	0
T1	277595	17	0	0
T2	482505	0	0	0
T3	33294	312	0	0
T4	245296	15	0	0
T5	13093	33	0	0
T6	34558	1627	0	0
T7	351261	1947	0	0
T8	61163	118	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	94	0	0
T12	0	228	0	0
T13	0	372	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	207702	0	0
GntImpliesValid_A	419235966	207702	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	207702	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	5138257	0	0
ReadyAndValidImplyGrant_A	419235966	207702	0	0
ReqAndReadyImplyGrant_A	419235966	207702	0	0
ReqImpliesValid_A	419235966	1020669	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	207702	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	5138257	0	0
T1	277595	48	0	0
T2	482505	0	0	0
T3	33294	2183	0	0
T4	245296	74	0	0
T5	13093	558	0	0
T6	34558	1378	0	0
T7	351261	13610	0	0
T8	61163	682	0	0
T9	89754	0	0	0
T10	453670	9579	0	0
T11	0	3757	0	0
T12	0	6304	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	1020669	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	376	0	0
T4	245296	21	0	0
T5	13093	115	0	0
T6	34558	227	0	0
T7	351261	989	0	0
T8	61163	167	0	0
T9	89754	0	0	0
T10	453670	3565	0	0
T11	0	354	0	0
T12	0	994	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	207702	0	0
T1	277595	7	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	43	0	0
T6	34558	160	0	0
T7	351261	503	0	0
T8	61163	129	0	0
T9	89754	0	0	0
T10	453670	570	0	0
T11	0	99	0	0
T12	0	262	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	226267	0	0
GntImpliesValid_A	419235966	226267	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	226267	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	5152877	0	0
ReadyAndValidImplyGrant_A	419235966	226267	0	0
ReqAndReadyImplyGrant_A	419235966	226267	0	0
ReqImpliesValid_A	419235966	1148405	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	226267	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	5152877	0	0
T1	277595	208	0	0
T2	482505	3123	0	0
T3	33294	2603	0	0
T4	245296	24	0	0
T5	13093	237	0	0
T6	34558	864	0	0
T7	351261	10094	0	0
T8	61163	810	0	0
T9	89754	658	0	0
T10	453670	3182	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	1148405	0	0
T1	277595	42	0	0
T2	482505	1646	0	0
T3	33294	953	0	0
T4	245296	8	0	0
T5	13093	69	0	0
T6	34558	193	0	0
T7	351261	843	0	0
T8	61163	167	0	0
T9	89754	5504	0	0
T10	453670	1740	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226267	0	0
T1	277595	15	0	0
T2	482505	571	0	0
T3	33294	460	0	0
T4	245296	5	0	0
T5	13093	45	0	0
T6	34558	143	0	0
T7	351261	467	0	0
T8	61163	134	0	0
T9	89754	439	0	0
T10	453670	497	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	227756	0	0
GntImpliesValid_A	419235966	227756	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	227756	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2802017	0	0
ReadyAndValidImplyGrant_A	419235966	227756	0	0
ReqAndReadyImplyGrant_A	419235966	227756	0	0
ReqImpliesValid_A	419235966	555118	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	227756	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2802017	0	0
T1	277595	64	0	0
T2	482505	1	0	0
T3	33294	298	0	0
T4	245296	66	0	0
T5	13093	227	0	0
T6	34558	122	0	0
T7	351261	6478	0	0
T8	61163	863	0	0
T9	89754	1	0	0
T10	453670	1573	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	555118	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	295	0	0
T4	245296	12	0	0
T5	13093	35	0	0
T6	34558	122	0	0
T7	351261	2463	0	0
T8	61163	145	0	0
T9	89754	0	0	0
T10	453670	1194	0	0
T11	0	100	0	0
T12	0	401	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227756	0	0
T1	277595	14	0	0
T2	482505	0	0	0
T3	33294	291	0	0
T4	245296	12	0	0
T5	13093	29	0	0
T6	34558	121	0	0
T7	351261	937	0	0
T8	61163	119	0	0
T9	89754	0	0	0
T10	453670	482	0	0
T11	0	88	0	0
T12	0	253	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	217517	0	0
GntImpliesValid_A	419235966	217517	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	217517	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2818769	0	0
ReadyAndValidImplyGrant_A	419235966	217517	0	0
ReqAndReadyImplyGrant_A	419235966	217517	0	0
ReqImpliesValid_A	419235966	543424	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	217517	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2818769	0	0
T1	277595	71	0	0
T2	482505	1	0	0
T3	33294	837	0	0
T4	245296	43	0	0
T5	13093	311	0	0
T6	34558	146	0	0
T7	351261	3899	0	0
T8	61163	856	0	0
T9	89754	3502	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	543424	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1286	0	0
T4	245296	10	0	0
T5	13093	85	0	0
T6	34558	146	0	0
T7	351261	638	0	0
T8	61163	165	0	0
T9	89754	11996	0	0
T10	453670	0	0	0
T11	0	129	0	0
T12	0	253	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217517	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	1056	0	0
T4	245296	10	0	0
T5	13093	44	0	0
T6	34558	145	0	0
T7	351261	516	0	0
T8	61163	109	0	0
T9	89754	1406	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	210	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	226400	0	0
GntImpliesValid_A	419235966	226400	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	226400	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2847533	0	0
ReadyAndValidImplyGrant_A	419235966	226400	0	0
ReqAndReadyImplyGrant_A	419235966	226400	0	0
ReqImpliesValid_A	419235966	557262	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	226400	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2847533	0	0
T1	277595	92	0	0
T2	482505	1	0	0
T3	33294	302	0	0
T4	245296	64	0	0
T5	13093	436	0	0
T6	34558	132	0	0
T7	351261	3808	0	0
T8	61163	790	0	0
T9	89754	1	0	0
T10	453670	1561	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	557262	0	0
T1	277595	24	0	0
T2	482505	0	0	0
T3	33294	307	0	0
T4	245296	12	0	0
T5	13093	119	0	0
T6	34558	132	0	0
T7	351261	621	0	0
T8	61163	125	0	0
T9	89754	0	0	0
T10	453670	1215	0	0
T11	0	158	0	0
T12	0	267	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226400	0	0
T1	277595	21	0	0
T2	482505	0	0	0
T3	33294	299	0	0
T4	245296	12	0	0
T5	13093	53	0	0
T6	34558	131	0	0
T7	351261	504	0	0
T8	61163	109	0	0
T9	89754	0	0	0
T10	453670	460	0	0
T11	0	109	0	0
T12	0	212	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	226451	0	0
GntImpliesValid_A	419235966	226451	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	226451	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2818306	0	0
ReadyAndValidImplyGrant_A	419235966	226451	0	0
ReqAndReadyImplyGrant_A	419235966	226451	0	0
ReqImpliesValid_A	419235966	544110	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	226451	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2818306	0	0
T1	277595	70	0	0
T2	482505	1	0	0
T3	33294	289	0	0
T4	245296	46	0	0
T5	13093	298	0	0
T6	34558	487	0	0
T7	351261	9975	0	0
T8	61163	776	0	0
T9	89754	1	0	0
T10	453670	1658	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	544110	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	296	0	0
T4	245296	13	0	0
T5	13093	55	0	0
T6	34558	791	0	0
T7	351261	5136	0	0
T8	61163	143	0	0
T9	89754	0	0	0
T10	453670	1166	0	0
T11	0	112	0	0
T12	0	245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	226451	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	287	0	0
T4	245296	13	0	0
T5	13093	41	0	0
T6	34558	638	0	0
T7	351261	1541	0	0
T8	61163	117	0	0
T9	89754	0	0	0
T10	453670	485	0	0
T11	0	101	0	0
T12	0	192	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T5,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	222718	0	0
GntImpliesValid_A	419235966	222718	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	222718	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2793455	0	0
ReadyAndValidImplyGrant_A	419235966	222718	0	0
ReqAndReadyImplyGrant_A	419235966	222718	0	0
ReqImpliesValid_A	419235966	538024	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	222718	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2793455	0	0
T1	277595	45	0	0
T2	482505	1	0	0
T3	33294	662	0	0
T4	245296	66	0	0
T5	13093	300	0	0
T6	34558	112	0	0
T7	351261	5090	0	0
T8	61163	909	0	0
T9	89754	1477	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	538024	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	777	0	0
T4	245296	12	0	0
T5	13093	66	0	0
T6	34558	110	0	0
T7	351261	4499	0	0
T8	61163	148	0	0
T9	89754	1855	0	0
T10	453670	0	0	0
T11	0	108	0	0
T12	0	322	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	222718	0	0
T1	277595	12	0	0
T2	482505	0	0	0
T3	33294	714	0	0
T4	245296	12	0	0
T5	13093	41	0	0
T6	34558	110	0	0
T7	351261	974	0	0
T8	61163	120	0	0
T9	89754	546	0	0
T10	453670	0	0	0
T11	0	93	0	0
T12	0	213	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	229596	0	0
GntImpliesValid_A	419235966	229596	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	229596	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2796136	0	0
ReadyAndValidImplyGrant_A	419235966	229596	0	0
ReqAndReadyImplyGrant_A	419235966	229596	0	0
ReqImpliesValid_A	419235966	587655	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	229596	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2796136	0	0
T1	277595	56	0	0
T2	482505	1	0	0
T3	33294	497	0	0
T4	245296	29	0	0
T5	13093	201	0	0
T6	34558	141	0	0
T7	351261	4314	0	0
T8	61163	881	0	0
T9	89754	1	0	0
T10	453670	1521	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	587655	0	0
T1	277595	20	0	0
T2	482505	0	0	0
T3	33294	586	0	0
T4	245296	10	0	0
T5	13093	37	0	0
T6	34558	141	0	0
T7	351261	724	0	0
T8	61163	168	0	0
T9	89754	0	0	0
T10	453670	1193	0	0
T11	0	154	0	0
T12	0	305	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	229596	0	0
T1	277595	13	0	0
T2	482505	0	0	0
T3	33294	536	0	0
T4	245296	10	0	0
T5	13093	32	0	0
T6	34558	140	0	0
T7	351261	562	0	0
T8	61163	116	0	0
T9	89754	0	0	0
T10	453670	471	0	0
T11	0	96	0	0
T12	0	204	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	230324	0	0
GntImpliesValid_A	419235966	230324	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	230324	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2779406	0	0
ReadyAndValidImplyGrant_A	419235966	230324	0	0
ReqAndReadyImplyGrant_A	419235966	230324	0	0
ReqImpliesValid_A	419235966	554024	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	230324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2779406	0	0
T1	277595	57	0	0
T2	482505	1363	0	0
T3	33294	283	0	0
T4	245296	28	0	0
T5	13093	331	0	0
T6	34558	196	0	0
T7	351261	5613	0	0
T8	61163	929	0	0
T9	89754	2387	0	0
T10	453670	1674	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	554024	0	0
T1	277595	14	0	0
T2	482505	1123	0	0
T3	33294	280	0	0
T4	245296	16	0	0
T5	13093	56	0	0
T6	34558	1088	0	0
T7	351261	1547	0	0
T8	61163	152	0	0
T9	89754	4109	0	0
T10	453670	1079	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230324	0	0
T1	277595	14	0	0
T2	482505	435	0	0
T3	33294	276	0	0
T4	245296	7	0	0
T5	13093	47	0	0
T6	34558	641	0	0
T7	351261	920	0	0
T8	61163	120	0	0
T9	89754	992	0	0
T10	453670	486	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	236619	0	0
GntImpliesValid_A	419235966	236619	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	236619	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2810210	0	0
ReadyAndValidImplyGrant_A	419235966	236619	0	0
ReqAndReadyImplyGrant_A	419235966	236619	0	0
ReqImpliesValid_A	419235966	586406	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	236619	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2810210	0	0
T1	277595	49	0	0
T2	482505	1516	0	0
T3	33294	292	0	0
T4	245296	41	0	0
T5	13093	251	0	0
T6	34558	116	0	0
T7	351261	4427	0	0
T8	61163	981	0	0
T9	89754	1303	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	586406	0	0
T1	277595	12	0	0
T2	482505	1088	0	0
T3	33294	297	0	0
T4	245296	10	0	0
T5	13093	49	0	0
T6	34558	2126	0	0
T7	351261	4953	0	0
T8	61163	152	0	0
T9	89754	2078	0	0
T10	453670	0	0	0
T11	0	108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	236619	0	0
T1	277595	12	0	0
T2	482505	458	0	0
T3	33294	289	0	0
T4	245296	10	0	0
T5	13093	35	0	0
T6	34558	1120	0	0
T7	351261	933	0	0
T8	61163	113	0	0
T9	89754	511	0	0
T10	453670	0	0	0
T11	0	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	245143	0	0
GntImpliesValid_A	419235966	245143	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	245143	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2948996	0	0
ReadyAndValidImplyGrant_A	419235966	245143	0	0
ReqAndReadyImplyGrant_A	419235966	245143	0	0
ReqImpliesValid_A	419235966	600265	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	245143	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2948996	0	0
T1	277595	26	0	0
T2	482505	3531	0	0
T3	33294	346	0	0
T4	245296	40	0	0
T5	13093	183	0	0
T6	34558	519	0	0
T7	351261	4255	0	0
T8	61163	1404	0	0
T9	89754	636	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	600265	0	0
T1	277595	12	0	0
T2	482505	2458	0	0
T3	33294	345	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	2659	0	0
T7	351261	756	0	0
T8	61163	260	0	0
T9	89754	4370	0	0
T10	453670	0	0	0
T11	0	183	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	245143	0	0
T1	277595	9	0	0
T2	482505	1040	0	0
T3	33294	340	0	0
T4	245296	10	0	0
T5	13093	29	0	0
T6	34558	1588	0	0
T7	351261	602	0	0
T8	61163	199	0	0
T9	89754	438	0	0
T10	453670	0	0	0
T11	0	160	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	243810	0	0
GntImpliesValid_A	419235966	243810	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	243810	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2853570	0	0
ReadyAndValidImplyGrant_A	419235966	243810	0	0
ReqAndReadyImplyGrant_A	419235966	243810	0	0
ReqImpliesValid_A	419235966	623383	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	243810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2853570	0	0
T1	277595	68	0	0
T2	482505	1507	0	0
T3	33294	1061	0	0
T4	245296	25	0	0
T5	13093	304	0	0
T6	34558	148	0	0
T7	351261	9533	0	0
T8	61163	924	0	0
T9	89754	1	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	623383	0	0
T1	277595	14	0	0
T2	482505	1126	0	0
T3	33294	1644	0	0
T4	245296	7	0	0
T5	13093	84	0	0
T6	34558	148	0	0
T7	351261	4146	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	134	0	0
T12	0	355	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	243810	0	0
T1	277595	14	0	0
T2	482505	453	0	0
T3	33294	1347	0	0
T4	245296	7	0	0
T5	13093	44	0	0
T6	34558	147	0	0
T7	351261	1422	0	0
T8	61163	114	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	121	0	0
T12	0	215	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	227926	0	0
GntImpliesValid_A	419235966	227926	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	227926	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2817722	0	0
ReadyAndValidImplyGrant_A	419235966	227926	0	0
ReqAndReadyImplyGrant_A	419235966	227926	0	0
ReqImpliesValid_A	419235966	594136	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	227926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2817722	0	0
T1	277595	62	0	0
T2	482505	3781	0	0
T3	33294	298	0	0
T4	245296	55	0	0
T5	13093	255	0	0
T6	34558	577	0	0
T7	351261	4040	0	0
T8	61163	599	0	0
T9	89754	1369	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	594136	0	0
T1	277595	19	0	0
T2	482505	2537	0	0
T3	33294	297	0	0
T4	245296	16	0	0
T5	13093	63	0	0
T6	34558	745	0	0
T7	351261	593	0	0
T8	61163	127	0	0
T9	89754	4419	0	0
T10	453670	0	0	0
T11	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	227926	0	0
T1	277595	17	0	0
T2	482505	1083	0	0
T3	33294	292	0	0
T4	245296	14	0	0
T5	13093	37	0	0
T6	34558	660	0	0
T7	351261	509	0	0
T8	61163	90	0	0
T9	89754	522	0	0
T10	453670	0	0	0
T11	0	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	228204	0	0
GntImpliesValid_A	419235966	228204	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	228204	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2833208	0	0
ReadyAndValidImplyGrant_A	419235966	228204	0	0
ReqAndReadyImplyGrant_A	419235966	228204	0	0
ReqImpliesValid_A	419235966	578491	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	228204	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2833208	0	0
T1	277595	57	0	0
T2	482505	1626	0	0
T3	33294	295	0	0
T4	245296	21	0	0
T5	13093	207	0	0
T6	34558	118	0	0
T7	351261	3671	0	0
T8	61163	851	0	0
T9	89754	1	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	578491	0	0
T1	277595	16	0	0
T2	482505	1311	0	0
T3	33294	292	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	118	0	0
T7	351261	572	0	0
T8	61163	127	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	113	0	0
T12	0	300	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	228204	0	0
T1	277595	12	0	0
T2	482505	509	0	0
T3	33294	288	0	0
T4	245296	7	0	0
T5	13093	29	0	0
T6	34558	117	0	0
T7	351261	487	0	0
T8	61163	115	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	97	0	0
T12	0	215	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	230370	0	0
GntImpliesValid_A	419235966	230370	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	230370	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2830957	0	0
ReadyAndValidImplyGrant_A	419235966	230370	0	0
ReqAndReadyImplyGrant_A	419235966	230370	0	0
ReqImpliesValid_A	419235966	568601	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	230370	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2830957	0	0
T1	277595	73	0	0
T2	482505	1	0	0
T3	33294	291	0	0
T4	245296	32	0	0
T5	13093	306	0	0
T6	34558	119	0	0
T7	351261	5758	0	0
T8	61163	866	0	0
T9	89754	1034	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	568601	0	0
T1	277595	19	0	0
T2	482505	0	0	0
T3	33294	292	0	0
T4	245296	7	0	0
T5	13093	45	0	0
T6	34558	117	0	0
T7	351261	1572	0	0
T8	61163	128	0	0
T9	89754	4482	0	0
T10	453670	0	0	0
T11	0	144	0	0
T12	0	291	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	230370	0	0
T1	277595	16	0	0
T2	482505	0	0	0
T3	33294	286	0	0
T4	245296	7	0	0
T5	13093	36	0	0
T6	34558	117	0	0
T7	351261	925	0	0
T8	61163	102	0	0
T9	89754	489	0	0
T10	453670	0	0	0
T11	0	107	0	0
T12	0	200	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	217889	0	0
GntImpliesValid_A	419235966	217889	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	217889	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	2774671	0	0
ReadyAndValidImplyGrant_A	419235966	217889	0	0
ReqAndReadyImplyGrant_A	419235966	217889	0	0
ReqImpliesValid_A	419235966	561197	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	0	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	217889	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2774671	0	0
T1	277595	32	0	0
T2	482505	1571	0	0
T3	33294	296	0	0
T4	245296	18	0	0
T5	13093	213	0	0
T6	34558	131	0	0
T7	351261	4763	0	0
T8	61163	1028	0	0
T9	89754	1	0	0
T10	453670	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	561197	0	0
T1	277595	9	0	0
T2	482505	1156	0	0
T3	33294	291	0	0
T4	245296	5	0	0
T5	13093	46	0	0
T6	34558	131	0	0
T7	351261	4392	0	0
T8	61163	146	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	132	0	0
T12	0	369	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	217889	0	0
T1	277595	9	0	0
T2	482505	484	0	0
T3	33294	288	0	0
T4	245296	5	0	0
T5	13093	32	0	0
T6	34558	130	0	0
T7	351261	917	0	0
T8	61163	132	0	0
T9	89754	0	0	0
T10	453670	0	0	0
T11	0	96	0	0
T12	0	255	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	903322	0	0
GntImpliesValid_A	419235966	903322	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	903322	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	10666922	0	0
ReadyAndValidImplyGrant_A	419235966	903322	0	0
ReqAndReadyImplyGrant_A	419235966	903322	0	0
ReqImpliesValid_A	419235966	2207081	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	19351	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	903322	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	10666922	0	0
T1	277595	225	0	0
T2	482505	2465	0	0
T3	33294	11	0	0
T4	245296	155	0	0
T5	13093	907	0	0
T6	34558	2	0	0
T7	351261	18450	0	0
T8	61163	3271	0	0
T9	89754	5710	0	0
T10	453670	1655	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	2207081	0	0
T1	277595	75	0	0
T2	482505	923	0	0
T3	33294	1831	0	0
T4	245296	71	0	0
T5	13093	223	0	0
T6	34558	2204	0	0
T7	351261	4025	0	0
T8	61163	713	0	0
T9	89754	8251	0	0
T10	453670	614	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	19351	0	900
T3	33294	20	0	1
T4	245296	0	0	1
T5	13093	0	0	1
T6	34558	321	0	1
T7	351261	1	0	1
T8	61163	0	0	1
T9	89754	6	0	1
T10	453670	0	0	1
T11	62832	0	0	1
T12	80022	1	0	1
T13	0	898	0	0
T14	0	8	0	0
T15	0	16	0	0
T16	0	2	0	0
T17	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	903322	0	0
T1	277595	66	0	0
T2	482505	726	0	0
T3	33294	1831	0	0
T4	245296	48	0	0
T5	13093	155	0	0
T6	34558	2204	0	0
T7	351261	2846	0	0
T8	61163	504	0	0
T9	89754	1426	0	0
T10	453670	473	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419235966	419101139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419235966	908835	0	0
GntImpliesValid_A	419235966	908835	0	0
GrantKnown_A	419235966	419101139	0	0
IdxKnown_A	419235966	419101139	0	0
IndexIsCorrect_A	419235966	908835	0	0
LockArbDecision_A	419235966	0	0	0
NoReadyValidNoGrant_A	419235966	351200324	0	0
ReadyAndValidImplyGrant_A	419235966	908835	0	0
ReqAndReadyImplyGrant_A	419235966	908835	0	0
ReqImpliesValid_A	419235966	12487321	0	0
ReqStaysHighUntilGranted0_M	419235966	0	0	0
RoundRobin_A	419235966	35146	0	900
ValidKnown_A	419235966	419101139	0	0
gen_data_port_assertion.DataFlow_A	419235966	908835	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	351200324	0	0
T1	277595	231213	0	0
T2	482505	401799	0	0
T3	33294	1	0	0
T4	245296	204215	0	0
T5	13093	11030	0	0
T6	34558	1	0	0
T7	351261	293955	0	0
T8	61163	52304	0	0
T9	89754	76777	0	0
T10	453670	377572	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	12487321	0	0
T1	277595	232	0	0
T2	482505	3382	0	0
T3	33294	2551	0	0
T4	245296	230	0	0
T5	13093	1002	0	0
T6	34558	2108	0	0
T7	351261	28555	0	0
T8	61163	3810	0	0
T9	89754	5502	0	0
T10	453670	6004	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	35146	0	900
T3	33294	134	0	1
T4	245296	0	0	1
T5	13093	0	0	1
T6	34558	420	0	1
T7	351261	2	0	1
T8	61163	2	0	1
T9	89754	0	0	1
T10	453670	5	0	1
T11	62832	0	0	1
T12	80022	0	0	1
T14	0	5	0	0
T16	0	2	0	0
T17	0	6	0	0
T18	0	155	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	419101139	0	0
T1	277595	277558	0	0
T2	482505	482501	0	0
T3	33294	32104	0	0
T4	245296	245276	0	0
T5	13093	13075	0	0
T6	34558	34430	0	0
T7	351261	351041	0	0
T8	61163	61151	0	0
T9	89754	89727	0	0
T10	453670	453663	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419235966	908835	0	0
T1	277595	55	0	0
T2	482505	769	0	0
T3	33294	2551	0	0
T4	245296	53	0	0
T5	13093	129	0	0
T6	34558	2108	0	0
T7	351261	3403	0	0
T8	61163	481	0	0
T9	89754	689	0	0
T10	453670	1274	0	0