Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1618245 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 257570 1 T1 386 T2 322 T3 21


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 636156 1 T1 971 T2 876 T3 40
values[0x0] 602997 1 T1 999 T2 757 T3 50
values[0x1] 636662 1 T1 1048 T2 798 T3 54


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1250676 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 625139 1 T1 950 T2 802 T3 43


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29571 1 T1 28 T2 35 T3 1
valid_sources[0x01] 29497 1 T1 4 T2 57 T3 1
valid_sources[0x02] 29899 1 T1 4 T2 26 T3 1
valid_sources[0x03] 28721 1 T2 33 T3 1 T4 2
valid_sources[0x04] 29539 1 T1 23 T2 39 T3 1
valid_sources[0x05] 28665 1 T1 22 T2 58 T3 4
valid_sources[0x06] 30331 1 T1 122 T2 37 T3 1
valid_sources[0x07] 29322 1 T2 27 T3 2 T4 5
valid_sources[0x08] 29971 1 T1 2 T2 47 T3 3
valid_sources[0x09] 29058 1 T1 1 T2 30 T3 3
valid_sources[0x0a] 28892 1 T1 382 T2 37 T3 5
valid_sources[0x0b] 28968 1 T1 3 T2 36 T3 4
valid_sources[0x0c] 29758 1 T1 6 T2 24 T3 2
valid_sources[0x0d] 29561 1 T1 2 T2 37 T3 4
valid_sources[0x0e] 29538 1 T1 3 T2 44 T3 1
valid_sources[0x0f] 29750 1 T1 6 T2 23 T3 1
valid_sources[0x10] 29675 1 T1 117 T2 20 T3 2
valid_sources[0x11] 29603 1 T1 259 T2 35 T3 1
valid_sources[0x12] 29058 1 T1 128 T2 47 T3 3
valid_sources[0x13] 29093 1 T1 2 T2 29 T3 3
valid_sources[0x14] 30149 1 T2 36 T5 1 T6 77
valid_sources[0x15] 29811 1 T1 2 T2 57 T3 2
valid_sources[0x16] 29495 1 T1 1 T2 41 T3 2
valid_sources[0x17] 29404 1 T1 1 T2 26 T3 1
valid_sources[0x18] 29152 1 T1 8 T2 22 T3 5
valid_sources[0x19] 28951 1 T1 6 T2 39 T3 2
valid_sources[0x1a] 28013 1 T1 131 T2 26 T3 2
valid_sources[0x1b] 29184 1 T1 217 T2 41 T3 3
valid_sources[0x1c] 28496 1 T1 1 T2 67 T3 3
valid_sources[0x1d] 29658 1 T1 21 T2 41 T3 2
valid_sources[0x1e] 28919 1 T1 9 T2 35 T3 2
valid_sources[0x1f] 28513 1 T1 1 T2 41 T3 3
valid_sources[0x20] 29555 1 T1 19 T2 37 T3 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26868 1 T1 26 T2 42 T3 2
values[0x0] all_enables biggest_size 203602 1 T1 314 T2 249 T3 17
values[0x1] all_enables biggest_size 27100 1 T1 46 T2 31 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1625612 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 265307 1 T1 447 T2 366 T3 15


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 647645 1 T1 986 T2 930 T3 31
values[0x0] 597327 1 T1 991 T2 839 T3 31
values[0x1] 645947 1 T1 1028 T2 853 T3 31


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1247511 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 643408 1 T1 1049 T2 892 T3 31


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29326 1 T1 41 T2 51 T4 1
valid_sources[0x01] 29747 1 T1 29 T2 42 T4 1
valid_sources[0x02] 29697 1 T1 46 T2 26 T3 6
valid_sources[0x03] 29216 1 T1 18 T2 52 T4 2
valid_sources[0x04] 29987 1 T1 45 T2 61 T4 2
valid_sources[0x05] 29308 1 T1 72 T2 3 T3 6
valid_sources[0x06] 30148 1 T1 96 T2 27 T3 2
valid_sources[0x07] 29201 1 T1 22 T2 99 T3 2
valid_sources[0x08] 29625 1 T1 22 T2 11 T5 5
valid_sources[0x09] 28951 1 T1 1 T2 37 T3 6
valid_sources[0x0a] 29008 1 T1 57 T2 68 T4 2
valid_sources[0x0b] 29483 1 T1 55 T2 40 T4 5
valid_sources[0x0c] 29151 1 T1 25 T2 64 T4 2
valid_sources[0x0d] 29089 1 T1 46 T2 60 T4 1
valid_sources[0x0e] 29386 1 T1 30 T2 48 T4 1
valid_sources[0x0f] 29856 1 T1 42 T2 47 T4 1
valid_sources[0x10] 29813 1 T1 33 T2 26 T5 4
valid_sources[0x11] 29630 1 T1 32 T2 28 T4 1
valid_sources[0x12] 29088 1 T1 70 T2 15 T3 11
valid_sources[0x13] 28648 1 T1 112 T2 55 T5 3
valid_sources[0x14] 30332 1 T1 10 T2 28 T4 3
valid_sources[0x15] 29173 1 T1 57 T2 34 T3 3
valid_sources[0x16] 30343 1 T1 26 T2 49 T3 8
valid_sources[0x17] 29217 1 T1 201 T2 24 T4 1
valid_sources[0x18] 29563 1 T1 52 T2 25 T4 2
valid_sources[0x19] 30103 1 T1 47 T2 24 T4 4
valid_sources[0x1a] 29234 1 T1 41 T2 40 T4 1
valid_sources[0x1b] 30118 1 T1 50 T2 29 T4 1
valid_sources[0x1c] 29375 1 T1 39 T2 36 T3 2
valid_sources[0x1d] 29457 1 T1 35 T2 55 T4 2
valid_sources[0x1e] 29464 1 T1 58 T2 66 T4 1
valid_sources[0x1f] 29316 1 T1 44 T2 25 T4 2
valid_sources[0x20] 30166 1 T1 32 T2 33 T4 3


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27962 1 T1 37 T2 30 T3 1
values[0x0] all_enables biggest_size 209808 1 T1 358 T2 299 T3 12
values[0x1] all_enables biggest_size 27537 1 T1 52 T2 37 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1628436 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 259150 1 T1 402 T2 342 T3 21


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 641654 1 T1 985 T2 900 T3 65
values[0x0] 607076 1 T1 993 T2 883 T3 40
values[0x1] 638856 1 T1 934 T2 898 T3 43


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1258614 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 628972 1 T1 971 T2 890 T3 50


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 29830 1 T1 44 T2 28 T4 2
valid_sources[0x01] 30227 1 T1 48 T2 42 T3 1
valid_sources[0x02] 29639 1 T1 37 T2 41 T3 4
valid_sources[0x03] 28808 1 T1 42 T2 44 T3 3
valid_sources[0x04] 29359 1 T1 46 T2 48 T4 1
valid_sources[0x05] 30645 1 T1 33 T2 42 T3 1
valid_sources[0x06] 29726 1 T1 75 T2 43 T5 3
valid_sources[0x07] 29326 1 T1 48 T2 38 T3 4
valid_sources[0x08] 29232 1 T1 32 T2 32 T4 3
valid_sources[0x09] 29072 1 T1 45 T2 46 T4 3
valid_sources[0x0a] 29306 1 T1 35 T2 39 T3 7
valid_sources[0x0b] 29406 1 T1 45 T2 29 T3 2
valid_sources[0x0c] 30073 1 T1 41 T2 40 T3 2
valid_sources[0x0d] 29220 1 T1 63 T2 47 T3 2
valid_sources[0x0e] 29955 1 T1 45 T2 40 T3 4
valid_sources[0x0f] 29611 1 T1 46 T2 41 T3 4
valid_sources[0x10] 29995 1 T1 50 T2 41 T4 2
valid_sources[0x11] 30399 1 T1 46 T2 55 T3 3
valid_sources[0x12] 28761 1 T1 28 T2 42 T4 1
valid_sources[0x13] 29256 1 T1 52 T2 26 T3 1
valid_sources[0x14] 30313 1 T1 56 T2 42 T4 2
valid_sources[0x15] 30046 1 T1 54 T2 38 T4 5
valid_sources[0x16] 28948 1 T1 41 T2 43 T3 1
valid_sources[0x17] 29135 1 T1 40 T2 46 T3 1
valid_sources[0x18] 29223 1 T1 57 T2 46 T3 2
valid_sources[0x19] 29606 1 T1 53 T2 52 T3 4
valid_sources[0x1a] 29751 1 T1 47 T2 43 T3 4
valid_sources[0x1b] 28608 1 T1 26 T2 32 T3 8
valid_sources[0x1c] 30213 1 T1 56 T2 51 T3 1
valid_sources[0x1d] 29693 1 T1 52 T2 41 T3 3
valid_sources[0x1e] 29209 1 T1 56 T2 46 T3 6
valid_sources[0x1f] 28741 1 T1 23 T2 36 T3 3
valid_sources[0x20] 30071 1 T1 41 T2 38 T4 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27168 1 T1 42 T2 35 T3 4
values[0x0] all_enables biggest_size 204870 1 T1 337 T2 273 T3 13
values[0x1] all_enables biggest_size 27112 1 T1 23 T2 34 T3 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%