Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8151490	0	0
GntImpliesValid_A	2147483647	8151490	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8151490	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	486161796	0	0
ReadyAndValidImplyGrant_A	2147483647	8151490	0	0
ReqAndReadyImplyGrant_A	2147483647	8151490	0	0
ReqImpliesValid_A	2147483647	36343249	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45041	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8151490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	449688	449088	0	0
T2	2144256	2143296	0	0
T3	9646032	9645024	0	0
T4	222360	221928	0	0
T5	3837528	3834360	0	0
T6	18055248	18055176	0	0
T7	15575976	15571272	0	0
T8	18411144	18410712	0	0
T9	148488	147312	0	0
T10	2901024	2848848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	449688	449088	0	0
T2	2144256	2143296	0	0
T3	9646032	9645024	0	0
T4	222360	221928	0	0
T5	3837528	3834360	0	0
T6	18055248	18055176	0	0
T7	15575976	15571272	0	0
T8	18411144	18410712	0	0
T9	148488	147312	0	0
T10	2901024	2848848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	449688	449088	0	0
T2	2144256	2143296	0	0
T3	9646032	9645024	0	0
T4	222360	221928	0	0
T5	3837528	3834360	0	0
T6	18055248	18055176	0	0
T7	15575976	15571272	0	0
T8	18411144	18410712	0	0
T9	148488	147312	0	0
T10	2901024	2848848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	486161796	0	0
T1	412214	1161	0	0
T2	2144256	136443	0	0
T3	9646032	521406	0	0
T4	222360	10760	0	0
T5	3837528	203968	0	0
T6	18055248	690625	0	0
T7	15575976	937801	0	0
T8	18411144	652093	0	0
T9	148488	8560	0	0
T10	2901024	68205	0	0
T11	688230	43547	0	0
T12	0	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36343249	0	0
T1	224844	20704	0	0
T2	2144256	18866	0	0
T3	9646032	16508	0	0
T4	222360	769	0	0
T5	3837528	57613	0	0
T6	18055248	42828	0	0
T7	15575976	167355	0	0
T8	18411144	5771	0	0
T9	148488	982	0	0
T10	2901024	80454	0	0
T11	4129380	81366	0	0
T12	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45041	0	21600
T1	18737	490	0	1
T2	89344	2	0	1
T3	401918	0	0	1
T4	9265	0	0	1
T5	159897	1	0	1
T6	1504604	36	0	2
T7	1297998	8	0	2
T8	1534262	0	0	2
T9	12374	0	0	2
T10	241752	614	0	2
T11	344115	13	0	1
T12	2027	0	0	1
T13	117392	1	0	1
T14	4855	10	0	1
T15	127917	1857	0	1
T16	0	8	0	0
T17	0	2	0	0
T18	0	19	0	0
T19	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	449688	449088	0	0
T2	2144256	2143296	0	0
T3	9646032	9645024	0	0
T4	222360	221928	0	0
T5	3837528	3834360	0	0
T6	18055248	18055176	0	0
T7	15575976	15571272	0	0
T8	18411144	18410712	0	0
T9	148488	147312	0	0
T10	2901024	2848848	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8151490	0	0
T1	224844	8935	0	0
T2	2144256	7729	0	0
T3	9646032	385	0	0
T4	222360	401	0	0
T5	3837528	12537	0	0
T6	18055248	14869	0	0
T7	15575976	48515	0	0
T8	18411144	3556	0	0
T9	148488	520	0	0
T10	2901024	54731	0	0
T11	4129380	15004	0	0
T12	0	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	901565	0	0
GntImpliesValid_A	441374735	901565	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	901565	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	13295407	0	0
ReadyAndValidImplyGrant_A	441374735	901565	0	0
ReqAndReadyImplyGrant_A	441374735	901565	0	0
ReqImpliesValid_A	441374735	2581850	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	901565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	13295407	0	0
T1	18737	488	0	0
T2	89344	6528	0	0
T3	401918	9009	0	0
T4	9265	341	0	0
T5	159897	8254	0	0
T6	752302	4285	0	0
T7	648999	35839	0	0
T8	767131	1644	0	0
T9	6187	308	0	0
T10	120876	4893	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	2581850	0	0
T1	18737	861	0	0
T2	89344	1586	0	0
T3	401918	737	0	0
T4	9265	74	0	0
T5	159897	1653	0	0
T6	752302	1431	0	0
T7	648999	13942	0	0
T8	767131	574	0	0
T9	6187	63	0	0
T10	120876	7887	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	901565	0	0
T1	18737	674	0	0
T2	89344	880	0	0
T3	401918	36	0	0
T4	9265	45	0	0
T5	159897	1142	0	0
T6	752302	1035	0	0
T7	648999	5349	0	0
T8	767131	408	0	0
T9	6187	41	0	0
T10	120876	6382	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	904439	0	0
GntImpliesValid_A	441374735	904439	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	904439	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	13264414	0	0
ReadyAndValidImplyGrant_A	441374735	904439	0	0
ReqAndReadyImplyGrant_A	441374735	904439	0	0
ReqImpliesValid_A	441374735	2658697	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	904439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	13264414	0	0
T1	18737	507	0	0
T2	89344	5640	0	0
T3	401918	15847	0	0
T4	9265	353	0	0
T5	159897	9486	0	0
T6	752302	4258	0	0
T7	648999	37678	0	0
T8	767131	1583	0	0
T9	6187	518	0	0
T10	120876	4563	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	2658697	0	0
T1	18737	898	0	0
T2	89344	1403	0	0
T3	401918	763	0	0
T4	9265	63	0	0
T5	159897	8658	0	0
T6	752302	1469	0	0
T7	648999	11866	0	0
T8	767131	553	0	0
T9	6187	78	0	0
T10	120876	7108	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	904439	0	0
T1	18737	702	0	0
T2	89344	845	0	0
T3	401918	41	0	0
T4	9265	52	0	0
T5	159897	1841	0	0
T6	752302	1038	0	0
T7	648999	6106	0	0
T8	767131	385	0	0
T9	6187	66	0	0
T10	120876	5828	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	231387	0	0
GntImpliesValid_A	441374735	231387	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	231387	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3391771	0	0
ReadyAndValidImplyGrant_A	441374735	231387	0	0
ReqAndReadyImplyGrant_A	441374735	231387	0	0
ReqImpliesValid_A	441374735	619279	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	231387	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3391771	0	0
T1	18737	1	0	0
T2	89344	1537	0	0
T3	401918	4654	0	0
T4	9265	89	0	0
T5	159897	1052	0	0
T6	752302	4810	0	0
T7	648999	10054	0	0
T8	767131	340	0	0
T9	6187	85	0	0
T10	120876	1165	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	619279	0	0
T2	89344	297	0	0
T3	401918	455	0	0
T4	9265	16	0	0
T5	159897	145	0	0
T6	752302	3316	0	0
T7	648999	4252	0	0
T8	767131	105	0	0
T9	6187	12	0	0
T10	120876	4992	0	0
T11	344115	4929	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231387	0	0
T2	89344	211	0	0
T3	401918	15	0	0
T4	9265	12	0	0
T5	159897	145	0	0
T6	752302	1467	0	0
T7	648999	1882	0	0
T8	767131	92	0	0
T9	6187	12	0	0
T10	120876	3071	0	0
T11	344115	866	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	229892	0	0
GntImpliesValid_A	441374735	229892	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	229892	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3345487	0	0
ReadyAndValidImplyGrant_A	441374735	229892	0	0
ReqAndReadyImplyGrant_A	441374735	229892	0	0
ReqImpliesValid_A	441374735	585957	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	229892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3345487	0	0
T1	18737	10	0	0
T2	89344	1749	0	0
T3	401918	2181	0	0
T4	9265	76	0	0
T5	159897	1057	0	0
T6	752302	1	0	0
T7	648999	10241	0	0
T8	767131	324	0	0
T9	6187	133	0	0
T10	120876	985	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	585957	0	0
T1	18737	1083	0	0
T2	89344	338	0	0
T3	401918	8	0	0
T4	9265	13	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	4391	0	0
T8	767131	112	0	0
T9	6187	20	0	0
T10	120876	2173	0	0
T11	0	8328	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	229892	0	0
T1	18737	546	0	0
T2	89344	235	0	0
T3	401918	8	0	0
T4	9265	11	0	0
T5	159897	150	0	0
T6	752302	0	0	0
T7	648999	1899	0	0
T8	767131	96	0	0
T9	6187	20	0	0
T10	120876	1571	0	0
T11	0	1379	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	230508	0	0
GntImpliesValid_A	441374735	230508	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	230508	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	5540099	0	0
ReadyAndValidImplyGrant_A	441374735	230508	0	0
ReqAndReadyImplyGrant_A	441374735	230508	0	0
ReqImpliesValid_A	441374735	1144738	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	230508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	5540099	0	0
T2	89344	11565	0	0
T3	401918	2610	0	0
T4	9265	92	0	0
T5	159897	5519	0	0
T6	752302	24442	0	0
T7	648999	67865	0	0
T8	767131	554	0	0
T9	6187	163	0	0
T10	120876	6911	0	0
T11	344115	16986	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	1144738	0	0
T2	89344	2031	0	0
T3	401918	10	0	0
T4	9265	20	0	0
T5	159897	5571	0	0
T6	752302	10700	0	0
T7	648999	6040	0	0
T8	767131	102	0	0
T9	6187	19	0	0
T10	120876	1580	0	0
T11	344115	1491	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230508	0	0
T2	89344	206	0	0
T3	401918	10	0	0
T4	9265	14	0	0
T5	159897	526	0	0
T6	752302	1468	0	0
T7	648999	840	0	0
T8	767131	87	0	0
T9	6187	19	0	0
T10	120876	958	0	0
T11	344115	416	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	216574	0	0
GntImpliesValid_A	441374735	216574	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	216574	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	5714599	0	0
ReadyAndValidImplyGrant_A	441374735	216574	0	0
ReqAndReadyImplyGrant_A	441374735	216574	0	0
ReqImpliesValid_A	441374735	1173101	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	216574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	5714599	0	0
T2	89344	2380	0	0
T3	401918	4055	0	0
T4	9265	104	0	0
T5	159897	1370	0	0
T6	752302	0	0	0
T7	648999	12683	0	0
T8	767131	1286	0	0
T9	6187	139	0	0
T10	120876	12737	0	0
T11	344115	15152	0	0
T12	0	70	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	1173101	0	0
T2	89344	312	0	0
T3	401918	8	0	0
T4	9265	18	0	0
T5	159897	120	0	0
T6	752302	0	0	0
T7	648999	1075	0	0
T8	767131	217	0	0
T9	6187	23	0	0
T10	120876	4439	0	0
T11	344115	1410	0	0
T12	0	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	216574	0	0
T2	89344	199	0	0
T3	401918	8	0	0
T4	9265	10	0	0
T5	159897	119	0	0
T6	752302	0	0	0
T7	648999	829	0	0
T8	767131	103	0	0
T9	6187	14	0	0
T10	120876	1317	0	0
T11	344115	407	0	0
T12	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	217863	0	0
GntImpliesValid_A	441374735	217863	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	217863	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	5005447	0	0
ReadyAndValidImplyGrant_A	441374735	217863	0	0
ReqAndReadyImplyGrant_A	441374735	217863	0	0
ReqImpliesValid_A	441374735	1021124	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	217863	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	5005447	0	0
T1	18737	5	0	0
T2	89344	2800	0	0
T3	401918	11268	0	0
T4	9265	58	0	0
T5	159897	3109	0	0
T6	752302	0	0	0
T7	648999	16049	0	0
T8	767131	813	0	0
T9	6187	123	0	0
T10	120876	6514	0	0
T11	0	11409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	1021124	0	0
T1	18737	2517	0	0
T2	89344	467	0	0
T3	401918	302	0	0
T4	9265	18	0	0
T5	159897	6781	0	0
T6	752302	0	0	0
T7	648999	7389	0	0
T8	767131	110	0	0
T9	6187	34	0	0
T10	120876	5840	0	0
T11	0	18606	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	217863	0	0
T1	18737	495	0	0
T2	89344	226	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	604	0	0
T6	752302	0	0	0
T7	648999	1236	0	0
T8	767131	98	0	0
T9	6187	17	0	0
T10	120876	1621	0	0
T11	0	1469	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	227228	0	0
GntImpliesValid_A	441374735	227228	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	227228	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	5638530	0	0
ReadyAndValidImplyGrant_A	441374735	227228	0	0
ReqAndReadyImplyGrant_A	441374735	227228	0	0
ReqImpliesValid_A	441374735	1228326	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	227228	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	5638530	0	0
T1	18737	22	0	0
T2	89344	4248	0	0
T3	401918	15655	0	0
T4	9265	194	0	0
T5	159897	2732	0	0
T6	752302	2463	0	0
T7	648999	42718	0	0
T8	767131	766	0	0
T9	6187	82	0	0
T10	120876	14722	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	1228326	0	0
T1	18737	5419	0	0
T2	89344	483	0	0
T3	401918	717	0	0
T4	9265	10	0	0
T5	159897	156	0	0
T6	752302	1370	0	0
T7	648999	19236	0	0
T8	767131	196	0	0
T9	6187	11	0	0
T10	120876	9519	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227228	0	0
T1	18737	437	0	0
T2	89344	194	0	0
T3	401918	11	0	0
T4	9265	10	0	0
T5	159897	144	0	0
T6	752302	461	0	0
T7	648999	2332	0	0
T8	767131	119	0	0
T9	6187	11	0	0
T10	120876	1750	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	218947	0	0
GntImpliesValid_A	441374735	218947	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	218947	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3331096	0	0
ReadyAndValidImplyGrant_A	441374735	218947	0	0
ReqAndReadyImplyGrant_A	441374735	218947	0	0
ReqImpliesValid_A	441374735	593991	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	218947	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3331096	0	0
T1	18737	2	0	0
T2	89344	1469	0	0
T3	401918	5514	0	0
T4	9265	92	0	0
T5	159897	5423	0	0
T6	752302	3561	0	0
T7	648999	9634	0	0
T8	767131	412	0	0
T9	6187	108	0	0
T10	120876	907	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	593991	0	0
T1	18737	947	0	0
T2	89344	337	0	0
T3	401918	251	0	0
T4	9265	30	0	0
T5	159897	7108	0	0
T6	752302	2025	0	0
T7	648999	7093	0	0
T8	767131	101	0	0
T9	6187	16	0	0
T10	120876	1949	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	218947	0	0
T1	18737	474	0	0
T2	89344	210	0	0
T3	401918	17	0	0
T4	9265	13	0	0
T5	159897	1226	0	0
T6	752302	998	0	0
T7	648999	1728	0	0
T8	767131	93	0	0
T9	6187	16	0	0
T10	120876	1420	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	224879	0	0
GntImpliesValid_A	441374735	224879	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	224879	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3371714	0	0
ReadyAndValidImplyGrant_A	441374735	224879	0	0
ReqAndReadyImplyGrant_A	441374735	224879	0	0
ReqImpliesValid_A	441374735	580367	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	224879	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3371714	0	0
T1	18737	1	0	0
T2	89344	1668	0	0
T3	401918	4624	0	0
T4	9265	75	0	0
T5	159897	2393	0	0
T6	752302	1	0	0
T7	648999	8198	0	0
T8	767131	454	0	0
T9	6187	86	0	0
T10	120876	1337	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	580367	0	0
T2	89344	359	0	0
T3	401918	449	0	0
T4	9265	11	0	0
T5	159897	1722	0	0
T6	752302	0	0	0
T7	648999	4908	0	0
T8	767131	117	0	0
T9	6187	14	0	0
T10	120876	1623	0	0
T11	344115	5428	0	0
T12	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	224879	0	0
T2	89344	228	0	0
T3	401918	14	0	0
T4	9265	11	0	0
T5	159897	613	0	0
T6	752302	0	0	0
T7	648999	1770	0	0
T8	767131	105	0	0
T9	6187	11	0	0
T10	120876	1473	0	0
T11	344115	935	0	0
T12	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	232154	0	0
GntImpliesValid_A	441374735	232154	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	232154	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3310934	0	0
ReadyAndValidImplyGrant_A	441374735	232154	0	0
ReqAndReadyImplyGrant_A	441374735	232154	0	0
ReqImpliesValid_A	441374735	592213	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	232154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3310934	0	0
T1	18737	1	0	0
T2	89344	1735	0	0
T3	401918	3836	0	0
T4	9265	82	0	0
T5	159897	1010	0	0
T6	752302	1	0	0
T7	648999	9172	0	0
T8	767131	438	0	0
T9	6187	77	0	0
T10	120876	905	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	592213	0	0
T2	89344	290	0	0
T3	401918	13	0	0
T4	9265	27	0	0
T5	159897	148	0	0
T6	752302	0	0	0
T7	648999	3166	0	0
T8	767131	117	0	0
T9	6187	14	0	0
T10	120876	921	0	0
T11	344115	486	0	0
T12	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	232154	0	0
T2	89344	222	0	0
T3	401918	13	0	0
T4	9265	16	0	0
T5	159897	138	0	0
T6	752302	0	0	0
T7	648999	1343	0	0
T8	767131	98	0	0
T9	6187	12	0	0
T10	120876	905	0	0
T11	344115	403	0	0
T12	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	230975	0	0
GntImpliesValid_A	441374735	230975	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	230975	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3411552	0	0
ReadyAndValidImplyGrant_A	441374735	230975	0	0
ReqAndReadyImplyGrant_A	441374735	230975	0	0
ReqImpliesValid_A	441374735	633149	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	230975	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3411552	0	0
T1	18737	1	0	0
T2	89344	1802	0	0
T3	401918	4229	0	0
T4	9265	65	0	0
T5	159897	1016	0	0
T6	752302	1	0	0
T7	648999	6103	0	0
T8	767131	426	0	0
T9	6187	86	0	0
T10	120876	964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	633149	0	0
T2	89344	296	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	155	0	0
T6	752302	0	0	0
T7	648999	873	0	0
T8	767131	120	0	0
T9	6187	17	0	0
T10	120876	1904	0	0
T11	344115	8784	0	0
T12	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	230975	0	0
T2	89344	230	0	0
T3	401918	11	0	0
T4	9265	11	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	784	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1426	0	0
T11	344115	1387	0	0
T12	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	227925	0	0
GntImpliesValid_A	441374735	227925	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	227925	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3350282	0	0
ReadyAndValidImplyGrant_A	441374735	227925	0	0
ReqAndReadyImplyGrant_A	441374735	227925	0	0
ReqImpliesValid_A	441374735	622328	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	227925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3350282	0	0
T1	18737	3	0	0
T2	89344	1331	0	0
T3	401918	4005	0	0
T4	9265	84	0	0
T5	159897	1153	0	0
T6	752302	1	0	0
T7	648999	6005	0	0
T8	767131	432	0	0
T9	6187	164	0	0
T10	120876	1826	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	622328	0	0
T1	18737	2010	0	0
T2	89344	259	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	145	0	0
T6	752302	0	0	0
T7	648999	924	0	0
T8	767131	107	0	0
T9	6187	22	0	0
T10	120876	2158	0	0
T11	0	4567	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	227925	0	0
T1	18737	1006	0	0
T2	89344	192	0	0
T3	401918	14	0	0
T4	9265	9	0	0
T5	159897	144	0	0
T6	752302	0	0	0
T7	648999	792	0	0
T8	767131	103	0	0
T9	6187	21	0	0
T10	120876	1984	0	0
T11	0	871	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	231076	0	0
GntImpliesValid_A	441374735	231076	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	231076	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3308474	0	0
ReadyAndValidImplyGrant_A	441374735	231076	0	0
ReqAndReadyImplyGrant_A	441374735	231076	0	0
ReqImpliesValid_A	441374735	636408	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	231076	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3308474	0	0
T1	18737	1	0	0
T2	89344	1617	0	0
T3	401918	2390	0	0
T4	9265	124	0	0
T5	159897	1163	0	0
T6	752302	1837	0	0
T7	648999	9049	0	0
T8	767131	484	0	0
T9	6187	96	0	0
T10	120876	1255	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	636408	0	0
T2	89344	295	0	0
T3	401918	11	0	0
T4	9265	28	0	0
T5	159897	184	0	0
T6	752302	1177	0	0
T7	648999	10221	0	0
T8	767131	154	0	0
T9	6187	11	0	0
T10	120876	2627	0	0
T11	344115	9216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231076	0	0
T2	89344	220	0	0
T3	401918	11	0	0
T4	9265	16	0	0
T5	159897	151	0	0
T6	752302	535	0	0
T7	648999	1895	0	0
T8	767131	113	0	0
T9	6187	11	0	0
T10	120876	1933	0	0
T11	344115	1412	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	228929	0	0
GntImpliesValid_A	441374735	228929	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	228929	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3330741	0	0
ReadyAndValidImplyGrant_A	441374735	228929	0	0
ReqAndReadyImplyGrant_A	441374735	228929	0	0
ReqImpliesValid_A	441374735	609472	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	228929	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3330741	0	0
T1	18737	1	0	0
T2	89344	1554	0	0
T3	401918	4257	0	0
T4	9265	42	0	0
T5	159897	1188	0	0
T6	752302	1347	0	0
T7	648999	8866	0	0
T8	767131	387	0	0
T9	6187	72	0	0
T10	120876	1117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	609472	0	0
T2	89344	264	0	0
T3	401918	251	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	1063	0	0
T7	648999	1955	0	0
T8	767131	104	0	0
T9	6187	11	0	0
T10	120876	1206	0	0
T11	344115	8470	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228929	0	0
T2	89344	203	0	0
T3	401918	11	0	0
T4	9265	7	0	0
T5	159897	155	0	0
T6	752302	427	0	0
T7	648999	1263	0	0
T8	767131	94	0	0
T9	6187	11	0	0
T10	120876	1154	0	0
T11	344115	2788	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	228986	0	0
GntImpliesValid_A	441374735	228986	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	228986	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3437322	0	0
ReadyAndValidImplyGrant_A	441374735	228986	0	0
ReqAndReadyImplyGrant_A	441374735	228986	0	0
ReqImpliesValid_A	441374735	611890	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	228986	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3437322	0	0
T1	18737	1	0	0
T2	89344	1520	0	0
T3	401918	4468	0	0
T4	9265	88	0	0
T5	159897	1204	0	0
T6	752302	1	0	0
T7	648999	5864	0	0
T8	767131	391	0	0
T9	6187	195	0	0
T10	120876	1031	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	611890	0	0
T2	89344	318	0	0
T3	401918	15	0	0
T4	9265	20	0	0
T5	159897	196	0	0
T6	752302	0	0	0
T7	648999	932	0	0
T8	767131	120	0	0
T9	6187	24	0	0
T10	120876	1965	0	0
T11	344115	8035	0	0
T12	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	228986	0	0
T2	89344	205	0	0
T3	401918	15	0	0
T4	9265	14	0	0
T5	159897	171	0	0
T6	752302	0	0	0
T7	648999	802	0	0
T8	767131	98	0	0
T9	6187	24	0	0
T10	120876	1490	0	0
T11	344115	1364	0	0
T12	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	240399	0	0
GntImpliesValid_A	441374735	240399	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	240399	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3504902	0	0
ReadyAndValidImplyGrant_A	441374735	240399	0	0
ReqAndReadyImplyGrant_A	441374735	240399	0	0
ReqImpliesValid_A	441374735	621064	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	240399	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3504902	0	0
T1	18737	1	0	0
T2	89344	1786	0	0
T3	401918	3303	0	0
T4	9265	48	0	0
T5	159897	1211	0	0
T6	752302	1881	0	0
T7	648999	8457	0	0
T8	767131	487	0	0
T9	6187	181	0	0
T10	120876	1039	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	621064	0	0
T2	89344	272	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	167	0	0
T6	752302	1214	0	0
T7	648999	4989	0	0
T8	767131	120	0	0
T9	6187	53	0	0
T10	120876	1893	0	0
T11	344115	587	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	240399	0	0
T2	89344	222	0	0
T3	401918	10	0	0
T4	9265	10	0	0
T5	159897	166	0	0
T6	752302	551	0	0
T7	648999	1356	0	0
T8	767131	111	0	0
T9	6187	23	0	0
T10	120876	1458	0	0
T11	344115	479	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	223726	0	0
GntImpliesValid_A	441374735	223726	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	223726	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3312838	0	0
ReadyAndValidImplyGrant_A	441374735	223726	0	0
ReqAndReadyImplyGrant_A	441374735	223726	0	0
ReqImpliesValid_A	441374735	607510	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	223726	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3312838	0	0
T1	18737	1	0	0
T2	89344	1741	0	0
T3	401918	5400	0	0
T4	9265	110	0	0
T5	159897	3164	0	0
T6	752302	1	0	0
T7	648999	6666	0	0
T8	767131	422	0	0
T9	6187	109	0	0
T10	120876	942	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	607510	0	0
T2	89344	392	0	0
T3	401918	362	0	0
T4	9265	12	0	0
T5	159897	2375	0	0
T6	752302	0	0	0
T7	648999	1017	0	0
T8	767131	100	0	0
T9	6187	13	0	0
T10	120876	1894	0	0
T11	344115	563	0	0
T12	0	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223726	0	0
T2	89344	237	0	0
T3	401918	17	0	0
T4	9265	12	0	0
T5	159897	584	0	0
T6	752302	0	0	0
T7	648999	862	0	0
T8	767131	88	0	0
T9	6187	13	0	0
T10	120876	1410	0	0
T11	344115	412	0	0
T12	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	219335	0	0
GntImpliesValid_A	441374735	219335	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	219335	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3331221	0	0
ReadyAndValidImplyGrant_A	441374735	219335	0	0
ReqAndReadyImplyGrant_A	441374735	219335	0	0
ReqImpliesValid_A	441374735	580408	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	219335	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3331221	0	0
T1	18737	36	0	0
T2	89344	1523	0	0
T3	401918	4528	0	0
T4	9265	82	0	0
T5	159897	2063	0	0
T6	752302	1390	0	0
T7	648999	9920	0	0
T8	767131	420	0	0
T9	6187	48	0	0
T10	120876	922	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	580408	0	0
T1	18737	1073	0	0
T2	89344	263	0	0
T3	401918	101	0	0
T4	9265	14	0	0
T5	159897	4906	0	0
T6	752302	1033	0	0
T7	648999	11202	0	0
T8	767131	130	0	0
T9	6187	9	0	0
T10	120876	2034	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	219335	0	0
T1	18737	554	0	0
T2	89344	210	0	0
T3	401918	13	0	0
T4	9265	12	0	0
T5	159897	663	0	0
T6	752302	429	0	0
T7	648999	2106	0	0
T8	767131	102	0	0
T9	6187	9	0	0
T10	120876	1470	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	220765	0	0
GntImpliesValid_A	441374735	220765	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	220765	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3298923	0	0
ReadyAndValidImplyGrant_A	441374735	220765	0	0
ReqAndReadyImplyGrant_A	441374735	220765	0	0
ReqImpliesValid_A	441374735	546109	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	220765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3298923	0	0
T1	18737	1	0	0
T2	89344	1730	0	0
T3	401918	6999	0	0
T4	9265	26	0	0
T5	159897	1135	0	0
T6	752302	3825	0	0
T7	648999	6082	0	0
T8	767131	449	0	0
T9	6187	91	0	0
T10	120876	1064	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	546109	0	0
T2	89344	281	0	0
T3	401918	18	0	0
T4	9265	8	0	0
T5	159897	157	0	0
T6	752302	2326	0	0
T7	648999	879	0	0
T8	767131	153	0	0
T9	6187	10	0	0
T10	120876	1956	0	0
T11	344115	466	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	220765	0	0
T2	89344	240	0	0
T3	401918	18	0	0
T4	9265	6	0	0
T5	159897	157	0	0
T6	752302	1088	0	0
T7	648999	810	0	0
T8	767131	108	0	0
T9	6187	10	0	0
T10	120876	1502	0	0
T11	344115	416	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	223577	0	0
GntImpliesValid_A	441374735	223577	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	223577	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3331999	0	0
ReadyAndValidImplyGrant_A	441374735	223577	0	0
ReqAndReadyImplyGrant_A	441374735	223577	0	0
ReqImpliesValid_A	441374735	606959	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	223577	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3331999	0	0
T1	18737	2	0	0
T2	89344	1758	0	0
T3	401918	2769	0	0
T4	9265	58	0	0
T5	159897	2232	0	0
T6	752302	1599	0	0
T7	648999	9854	0	0
T8	767131	397	0	0
T9	6187	164	0	0
T10	120876	1451	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	606959	0	0
T1	18737	995	0	0
T2	89344	298	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	4692	0	0
T6	752302	1174	0	0
T7	648999	2479	0	0
T8	767131	139	0	0
T9	6187	19	0	0
T10	120876	1744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	223577	0	0
T1	18737	498	0	0
T2	89344	225	0	0
T3	401918	10	0	0
T4	9265	11	0	0
T5	159897	656	0	0
T6	752302	517	0	0
T7	648999	1322	0	0
T8	767131	103	0	0
T9	6187	19	0	0
T10	120876	1590	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	231667	0	0
GntImpliesValid_A	441374735	231667	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	231667	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	3409365	0	0
ReadyAndValidImplyGrant_A	441374735	231667	0	0
ReqAndReadyImplyGrant_A	441374735	231667	0	0
ReqImpliesValid_A	441374735	595943	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	0	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	231667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	3409365	0	0
T1	18737	74	0	0
T2	89344	1365	0	0
T3	401918	2657	0	0
T4	9265	112	0	0
T5	159897	2892	0	0
T6	752302	1682	0	0
T7	648999	9080	0	0
T8	767131	469	0	0
T9	6187	58	0	0
T10	120876	938	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	595943	0	0
T1	18737	2777	0	0
T2	89344	257	0	0
T3	401918	12	0	0
T4	9265	30	0	0
T5	159897	1487	0	0
T6	752302	1076	0	0
T7	648999	1989	0	0
T8	767131	120	0	0
T9	6187	7	0	0
T10	120876	970	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	231667	0	0
T1	18737	1425	0	0
T2	89344	199	0	0
T3	401918	12	0	0
T4	9265	15	0	0
T5	159897	621	0	0
T6	752302	473	0	0
T7	648999	1305	0	0
T8	767131	111	0	0
T9	6187	7	0	0
T10	120876	946	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	908972	0	0
GntImpliesValid_A	441374735	908972	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	908972	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	12901850	0	0
ReadyAndValidImplyGrant_A	441374735	908972	0	0
ReqAndReadyImplyGrant_A	441374735	908972	0	0
ReqImpliesValid_A	441374735	2515008	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	15948	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	908972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	12901850	0	0
T1	18737	1	0	0
T2	89344	4702	0	0
T3	401918	7534	0	0
T4	9265	198	0	0
T5	159897	7078	0	0
T6	752302	7045	0	0
T7	648999	34520	0	0
T8	767131	1144	0	0
T9	6187	431	0	0
T10	120876	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	2515008	0	0
T1	18737	722	0	0
T2	89344	1384	0	0
T3	401918	507	0	0
T4	9265	35	0	0
T5	159897	1520	0	0
T6	752302	4679	0	0
T7	648999	9442	0	0
T8	767131	448	0	0
T9	6187	94	0	0
T10	120876	5698	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	15948	0	900
T6	752302	22	0	1
T7	648999	3	0	1
T8	767131	0	0	1
T9	6187	0	0	1
T10	120876	50	0	1
T11	344115	0	0	1
T12	2027	0	0	1
T13	117392	1	0	1
T14	4855	7	0	1
T15	127917	494	0	1
T16	0	2	0	0
T17	0	2	0	0
T18	0	19	0	0
T19	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	908972	0	0
T1	18737	722	0	0
T2	89344	826	0	0
T3	401918	28	0	0
T4	9265	35	0	0
T5	159897	1114	0	0
T6	752302	2504	0	0
T7	648999	5358	0	0
T8	767131	373	0	0
T9	6187	63	0	0
T10	120876	5698	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441374735	441257410	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	441374735	899722	0	0
GntImpliesValid_A	441374735	899722	0	0
GrantKnown_A	441374735	441257410	0	0
IdxKnown_A	441374735	441257410	0	0
IndexIsCorrect_A	441374735	899722	0	0
LockArbDecision_A	441374735	0	0	0
NoReadyValidNoGrant_A	441374735	371022829	0	0
ReadyAndValidImplyGrant_A	441374735	899722	0	0
ReqAndReadyImplyGrant_A	441374735	899722	0	0
ReqImpliesValid_A	441374735	14377358	0	0
ReqStaysHighUntilGranted0_M	441374735	0	0	0
RoundRobin_A	441374735	29093	0	900
ValidKnown_A	441374735	441257410	0	0
gen_data_port_assertion.DataFlow_A	441374735	899722	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	371022829	0	0
T1	18737	1	0	0
T2	89344	72695	0	0
T3	401918	389614	0	0
T4	9265	8167	0	0
T5	159897	137064	0	0
T6	752302	626193	0	0
T7	648999	557204	0	0
T8	767131	637571	0	0
T9	6187	5043	0	0
T10	120876	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	14377358	0	0
T1	18737	1402	0	0
T2	89344	6384	0	0
T3	401918	11473	0	0
T4	9265	269	0	0
T5	159897	9262	0	0
T6	752302	8775	0	0
T7	648999	37095	0	0
T8	767131	1652	0	0
T9	6187	388	0	0
T10	120876	6374	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	29093	0	900
T1	18737	490	0	1
T2	89344	2	0	1
T3	401918	0	0	1
T4	9265	0	0	1
T5	159897	1	0	1
T6	752302	14	0	1
T7	648999	5	0	1
T8	767131	0	0	1
T9	6187	0	0	1
T10	120876	564	0	1
T11	0	13	0	0
T14	0	3	0	0
T15	0	1363	0	0
T16	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	441257410	0	0
T1	18737	18712	0	0
T2	89344	89304	0	0
T3	401918	401876	0	0
T4	9265	9247	0	0
T5	159897	159765	0	0
T6	752302	752299	0	0
T7	648999	648803	0	0
T8	767131	767113	0	0
T9	6187	6138	0	0
T10	120876	118702	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441374735	899722	0	0
T1	18737	1402	0	0
T2	89344	864	0	0
T3	401918	28	0	0
T4	9265	38	0	0
T5	159897	1162	0	0
T6	752302	1878	0	0
T7	648999	4546	0	0
T8	767131	368	0	0
T9	6187	57	0	0
T10	120876	6374	0	0